CN203941545U - A kind of demodulator circuit for passive ultra-high frequency RFID label chip - Google Patents
A kind of demodulator circuit for passive ultra-high frequency RFID label chip Download PDFInfo
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- CN203941545U CN203941545U CN201420375904.8U CN201420375904U CN203941545U CN 203941545 U CN203941545 U CN 203941545U CN 201420375904 U CN201420375904 U CN 201420375904U CN 203941545 U CN203941545 U CN 203941545U
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Abstract
The utility model discloses a kind ofly for passive ultra-high frequency RFID label chip demodulator circuit, comprise rectification circuit, get envelope circuit, low-pass filter circuit, average produce circuit, comparer, shaping circuit, enable control circuit, biasing circuit.Rectification circuit consists of main and compole, employing valve value compensation is realized, get envelope circuit and enabling to extract envelope under control circuit control, low-pass filter circuit directly adopts reinforced concrete structure, average produces circuit by operational amplifier, diode and electric capacity form, utilize the principle that peak value detects to realize, comparer adopts the operational amplifier of open loop to realize, shaping circuit consists of the phase inverter of two cascades, enabling control circuit adopts the mode of three grades of phase inverter cascades to control average generation circuit, comparer, shaping circuit, greatly reduced the idle power consumption of demodulator circuit, biasing circuit is to rectification circuit, average produces circuit, comparer provides nA level electric current.Demodulator circuit has high sensitivity, wide input range, low-power consumption, area is little and feature cheaply.
Description
Technical field
The utility model belongs to REID field, more specifically, relates to a kind of demodulator circuit for passive ultra-high frequency RFID label chip.
Background technology
Along with ultrahigh frequency RFID systems technology constantly develops, market is also more and more higher to the performance requirement of system, telecommunication, high reliability, low error rate, low distortion have increased design difficulty, when reader sends to modulated signal after label, label obtains baseband signal by antenna receiving signal demodulation.Demodulation techniques are divided into simulating signal solution mediation digital demodulation signal at present, by changing amplitude, frequency and the phase place of carrier signal, realize.Demodulation method can adopt synchronous detection method and envelope detected method, and synchronous detection method principle is based on coherent demodulation mode, yet in realization, needs the more complicated circuit such as phaselocked loop, multiplier to recover baseband signal, has increased greatly cost.Envelope detected method principle is that circuit structure is simple based on non-coherent demodulation mode, is easy to realize, and cost is low.At present passive ultra-high frequency RFID label chip demodulator circuit is that amplitude shift keying (ASK) modulation signal that read write line is sent to label carries out demodulation mostly, the implementation that adopts envelope detected method to carry out demodulation to amplitude shift keying (ASK) modulation signal, the feature such as that its demodulator circuit has is simple in structure, low in energy consumption, area is little and cost is low.
For super high frequency radio frequency recognition technology, for the ease of reader, the product specification such as label, all formulated the popularization that corresponding consensus standard promotes globalisation of production both at home and abroad, domestic standard < < infotech radio-frequency (RF) identification 800～900MHz air interface protocol > > regulation reader is 840～845MHz and 920～925MHz to the working frequency range of label, data rate is 45.7kb/s～91.4kb/s, modulation system adopts DSB-ASK, SSB-ASK, adjusting the degree of depth is 30%～100%, coded system is TPP.International standard ISO/IEC180006C and EPCglobal C1G2 regulation reader are 860～960MHz to the working frequency range of label, data rate is 40～160kb/s, modulation system adopts DSB-ASK, SSB-ASK and PR-ASK, and adjusting the degree of depth is 80%～100%, and coded system is PIE.
Utility model content
For the defect of prior art, the purpose of this utility model is to provide a kind of demodulator circuit for passive ultra-high frequency RFID label chip, is intended to solve label chip poor sensitivity, input range is low and power consumption is large problem.
The utility model provides a kind of demodulator circuit for passive ultra-high frequency RFID label chip, comprises rectification circuit, gets envelope circuit, low-pass filter circuit, average produce circuit, comparer, shaping circuit, enable control circuit and biasing circuit; The input end of described rectification circuit is connected with exterior antenna, and the control end of described rectification circuit is connected to the output terminal of described biasing circuit; The described input end of getting envelope circuit is connected to the output terminal of described rectification circuit, described in get envelope circuit control end for connecting external control signal Ena; Described in being connected to, gets the input end of described low-pass filter circuit the output terminal of envelope circuit; The input end of described average generation circuit is connected to the output terminal of described low-pass filter circuit, enables the second output terminal of control circuit described in the control end of described average generation circuit is connected to; The first input end of described comparer is connected to the first output terminal that described average produces circuit, the second input end of described comparer is connected to the output terminal of described low-pass filter circuit, enables the first output terminal of control circuit described in the control end of described comparer connects; The input end of described shaping circuit is connected to the first output terminal of described comparer, enables the first output terminal of control circuit described in the control end of described shaping circuit connects, and the output terminal of described shaping circuit is used for exporting restituted signal; The input end of described biasing circuit produces the second output terminal of circuit with described average and the second output terminal of described comparer is connected; The described input end that enables control circuit, for connecting external control signal Ena, enables control signal Enb and second according to described control signal Ena generation first and enables control signal Enc.
Wherein, during work, the radiofrequency signal that RFID label antenna receives enters after demodulator circuit, by described rectification circuit, AC signal is converted to direct current signal, and improves the amplitude of output signal, by getting the envelope in envelope circuit extraction radiofrequency signal, envelope signal enters low-pass filter circuit by HF noise signal filtering thereupon, the reference voltage that output signal and average generation circuit obtain simultaneously, through after comparer, inputs to shaping circuit and carries out shaping, exports final restituted signal.
Wherein, described rectification circuit comprises capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, PMOS pipe MP1, NMOS pipe MN1, NMOS pipe MN2 and NMOS pipe MN3; After being connected in parallel with one end of described capacitor C 2, one end of described capacitor C 1 is connected with the anodal ANT2 of antenna, the source electrode of described MP1 is connected to the other end of described capacitor C 1, the source electrode of described MP1 is also connected to the grid of described MN3, after the drain electrode of described MP1 is connected with the drain electrode of described MN1 as the control end of described rectification circuit; The source electrode of described MN1 is connected to antenna negative pole ANT1; The drain electrode of described MN3 is as the output terminal of described rectification circuit, and the source electrode of described MN3 is connected with the drain electrode of described MN2, and the source electrode of described MN3 is also connected with the grid of described MP1; The source electrode of described MN2 is connected to antenna negative pole ANT1; The grid of described MN2 is connected with the grid of described MN1; The grid of described MN2 is also connected with the drain electrode of described MN1, and the grid of described MN2 is also connected to antenna negative pole ANT1 by described capacitor C 3; The other end of described capacitor C 2 is connected to the source electrode of described MN3 and the drain electrode link of described MN2; One end of described capacitor C 4 is connected to the drain electrode of described MN3, and the other end of described capacitor C 4 is connected to described antenna negative pole ANT1.
Wherein, described in, getting envelope circuit comprises: NMOS pipe MN4, NMOS pipe MN5, PMOS pipe MP2, PMOS pipe MP3, PMOS pipe MP4, resistance R 1 and capacitor C 5; After being connected, the grid of described MP2, the grid of described MP3, the grid of described MN4 and the grid of described MP4 get the control end of envelope circuit described in conduct, the source electrode of described MP3 is connected to power vd D, the drain electrode of described MP3 is connected with the drain electrode of described MN4, the drain electrode of described MP3 is also connected with the grid of described MN5, and the source electrode of described MN4 is connected to antenna negative pole ANT1; The source electrode of described MP4 is as the described output terminal of getting envelope circuit, and the drain electrode of described MP4 is connected with the drain electrode of described MN5, and the source electrode of described MN5 is connected to antenna negative pole ANT1; The drain electrode of described MP2 is connected to antenna negative pole ANT1 by described resistance R 1; The source electrode of described MP2 is connected to the drain electrode of described MP4; The source electrode of described MP4 is as the described input end of getting envelope circuit; One end of described capacitor C 5 is connected to the source electrode of described MP4, and the other end of described capacitor C 5 is connected to antenna negative pole ANT1.
Wherein, described average generation circuit comprises: operational amplifier A 1, diode MP5 and capacitor C 7; The normal phase input end of described operational amplifier A 1 produces the input end of circuit as described average, the inverting input of described operational amplifier A 1 produces the first output terminal of circuit as described average, the cathode power supply end of described operational amplifier A 1 produces the control end of circuit as described average, the negative electricity source of described operational amplifier A 1 produces the second output terminal of circuit as described average; The positive pole of described diode MP5 is connected with the output terminal of described operational amplifier A 1, and the negative pole of described diode MP5 is connected with the inverting input of described operational amplifier A 1; The positive pole of described capacitor C 7 is connected to the inverting input of described operational amplifier A 1, and the negative pole of described capacitor C 7 is used for being connected to antenna negative pole ANT1.
Wherein, described in, enable control circuit and comprise NMOS pipe MN8, PMOS pipe MP9, NMOS pipe MN9, NMOS pipe MN10, PMOS pipe MP10, NMOS pipe MN11 and PMOS pipe MP11; After the grid of described MP9 is connected with the grid of described MN8, described in conduct, enable the input end of control circuit, the source electrode of described MP9 connects power vd D, and the drain electrode of described MP9 is connected with the drain electrode of described MN8, and the source electrode of described MN8 is connected to antenna negative pole ANT1; After being connected with the grid of described MN10, the grid of described MP10 is connected with the drain electrode link of described MP9 and MN8, the source electrode of described MP10 connects power vd D, enables the second output terminal of control circuit after the drain electrode of described MP10 is connected with the drain electrode of described MN10 described in conduct; The source electrode of described MP10 is connected with the drain electrode of described MN9, and the source electrode of described MN9 is connected to antenna negative pole ANT1; After being connected with the grid of described MN11, the grid of described MP11 is connected with the drain electrode link of described MP10 and described MN10, the source electrode of described MP11 connects power vd D, enables the first output terminal of control circuit after the drain electrode of described MP11 is connected with the drain electrode of described MN11 described in conduct; The source electrode of described MN11 is connected to antenna negative pole ANT1.
Wherein, described biasing circuit comprises: current source I, PMOS pipe MP12 and PMOS pipe MP13; The source electrode of described PMOS pipe MP12 is connected to power vd D, and the drain electrode of described PMOS pipe MP12 is connected to the positive pole of described current source I, and the drain electrode of described PMOS pipe MP12 is also connected with its grid; The negative pole of described current source I is connected to antenna negative pole ANT1; The source electrode of described PMOS pipe MP13 is connected to power vd D, and after the grid of described PMOS pipe MP13 is connected with the grid of described PMOS pipe MP12, as the input end of described biasing circuit, the drain electrode of described PMOS pipe MP13 is as the output terminal of described biasing circuit.
In the demodulator circuit that the utility model provides, by adopting the rectification circuit of threshold voltage compensation to realize rectification, improved the performance characteristic of tag sensitivity and input range; By biasing circuit, provide nA level electric current, thus the power consumption while having reduced demodulator circuit work; Employing enables control circuit and has reduced power consumption when demodulator circuit is not worked.Whole demodulator circuit compared with prior art, the problem such as solve label chip poor sensitivity, input range is low, power consumption is large, thus guarantee that between reader and label, communication distance is far away, reliability is high, the bit error rate is low.
Accompanying drawing explanation
Fig. 1 is the modular structure schematic diagram of the demodulator circuit for passive ultra-high frequency RFID label chip that provides of the utility model embodiment;
Fig. 2 is the structural representation of the demodulator circuit rectification circuit for passive ultra-high frequency RFID label chip that provides of the utility model embodiment;
Fig. 3 is that the demodulator circuit for passive ultra-high frequency RFID label chip that the utility model embodiment provides is got envelope electrical block diagram;
Fig. 4 is the demodulator circuit low-pass filter circuit structural representation for passive ultra-high frequency RFID label chip that the utility model embodiment provides;
Fig. 5 is that the demodulator circuit average for passive ultra-high frequency RFID label chip that the utility model embodiment provides produces electrical block diagram;
Fig. 6 is the structural representation of the demodulator circuit comparer for passive ultra-high frequency RFID label chip that provides of the utility model embodiment;
Fig. 7 is the structural representation of the demodulator circuit shaping circuit for passive ultra-high frequency RFID label chip that provides of the utility model embodiment;
Fig. 8 is the structural representation that the demodulator circuit for passive ultra-high frequency RFID label chip that the utility model embodiment provides enables control circuit;
Fig. 9 is the structural representation of the demodulator circuit biasing circuit for passive ultra-high frequency RFID label chip that provides of the utility model embodiment;
Figure 10 is the waveform schematic diagram of each port of the demodulator circuit demodulator circuit for passive ultra-high frequency RFID label chip that provides of the utility model embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.
The utility model belongs to integrated circuit (IC) design and REID field, relate to a kind of demodulator circuit for passive ultra-high frequency RFID label chip, this circuit has high sensitivity, wide input range, low-power consumption, area is little and feature cheaply, can be applied to the short-distance wireless communication system of passive or low-power consumption, as passive ultra-high frequency RFID label.
The utility model provides a kind of demodulator circuit for passive ultra-high frequency RFID label chip, in demodulator circuit, by adopting the rectification circuit 1 of threshold voltage compensation to realize rectification, has improved the performance characteristic of tag sensitivity and input range; By biasing circuit 7, provide nA level electric current, thus the power consumption while having reduced demodulator circuit work; Employing enables control circuit 5 and has reduced power consumption when demodulator circuit is not worked.Whole demodulator circuit compared with prior art, the problem such as solve label chip poor sensitivity, input range is low, power consumption is large, thus guarantee that between reader and label, communication distance is far away, reliability is high, the bit error rate is low.
The demodulator circuit that the utility model provides, comprises rectification circuit 1, gets envelope circuit 2, low-pass filter circuit 3, average produce circuit 4, comparer 6, shaping circuit 8, enable control circuit 5, biasing circuit 7.Rectification circuit 1 input port is connected with negative pole port with exterior antenna is anodal, and biasing circuit 7 provides bias voltage to rectification circuit; Get envelope circuit 2 input ports and be connected with rectification circuit 1 output port, get envelope circuit 2 simultaneously and be subject to outside and enable control port and control; Low-pass filter circuit 3 input ports with get envelope circuit 2 output ports and be connected; Average produces circuit 4 input ports and is connected with low-pass filter circuit 3 output ports, and biasing circuit 7 produces circuit 4 to average bias voltage is provided, and is subject to enabling control circuit 5 controls; Comparer 6 input ports produce circuit 4 output ports with low-pass filter circuit 3 output ports and average respectively and are connected, and biasing circuit 7 provides bias voltage to comparer 6, and are subject to enabling control circuit 5 controls; Shaping circuit 8 input ports are connected with comparer 6 output ports, are subject to enabling the control of control circuit 5, shaping circuit 8 output port output restituted signals; Enable control circuit 5 input ports and by outside, enable control port and control, outside enables control port, and to enable control port be same port with getting outside that envelope circuit 2 is subject to; The control signal that enables that comparer 6 and shaping circuit 8 are subject to is same signal; The bias voltage that biasing circuit 7 produces circuit 4 and comparer 6 and provides to average is same signal.
Rectification circuit 1 primary structure consists of main and compole, main comprises two NMOS pipes and two electric capacity, the source electrode of first NMOS pipe is connected with antenna negative pole, drain electrode is connected together with the positive pole of first electric capacity and the source electrode of second NMOS pipe, the negative pole of first electric capacity is connected with antenna positive pole, the drain electrode of second NMOS pipe is connected with the positive pole of second electric capacity, and the negative pole of second electric capacity is connected with antenna negative pole, compole comprises a NMOS pipe and a PMOS pipe, and two electric capacity, grid and the drain electrode of compole NMOS pipe, the drain electrode of compole PMOS pipe, the bias voltage that the positive pole of first electric capacity of compole also has the grid of first NMOS pipe of main to provide with external bias circuit is connected, the source electrode of compole NMOS pipe, the negative pole of first electric capacity of compole is connected with antenna negative pole, the grid of compole PMOS pipe is connected with the positive pole of first electric capacity of main, second electric capacity negative pole of the source electrode of compole PMOS pipe and compole, the grid of second NMOS pipe of main is connected, second capacitance cathode of compole is connected with antenna positive pole.
Getting envelope circuit 2 is managed by two NMOS, three PMOS pipes, a resistance and an electric capacity form, first NMOS pipe forms phase inverter with second PMOS pipe, the input end of phase inverter, the grid of first PMOS pipe, the grid of the 3rd PMOS pipe enables control port with outside and is connected, inverter output is connected with second NMOS tube grid, the drain electrode of first PMOS pipe is connected with the positive pole of resistance, the negative pole of resistance, the source electrode of first NMOS pipe, the source electrode of second NMOS pipe, the negative pole of electric capacity is connected with antenna negative pole, the source electrode of first PMOS pipe, the drain electrode of second NMOS pipe is connected with the drain electrode of the 3rd PMOS pipe, the 3rd source electrode of PMOS pipe and the positive pole of electric capacity are connected, capacitance cathode is as the output port of getting envelope circuit 2.
Low-pass filter circuit 3 consists of a resistance and an electric capacity, and resistance positive pole is as input port, and resistance negative pole is as output port, and the positive pole of resistance negative pole and electric capacity is connected, and the negative pole of electric capacity is connected with antenna negative pole.
Average produces circuit 4 and consists of operational amplifier, diode and electric capacity, biasing circuit 7 provides average to produce circuit 4 bias voltages, be subject to enabling control circuit 5 controls simultaneously, operational amplifier electrode input end mouth produces the input port of circuit 4 as average, negative input mouth produces the output port of circuit 4 as average, the output port of operational amplifier is connected with diode cathode, diode cathode, capacitance cathode and operational amplifier negative input mouth are connected, and electric capacity negative pole is connected with antenna negative pole.
Comparer 6 consists of the operational amplifier of open loop, the both positive and negative polarity input port of operational amplifier is the input port of device 6 as a comparison, the output port of operational amplifier is the output port of device 6 as a comparison, and biasing circuit 7 provides comparator offset voltages, is subject to enabling control circuit 5 and controls.
Shaping circuit 8 structures consist of two phase inverter cascades, and input port signal is subject to enabling control circuit 5 and controls, cascaded inverters output restituted signal.
Enabling control circuit 5 consists of three phase inverter cascades, input signal enables control port by outside to be provided, the control signal that enables of second level phase inverter output is controlled average generation circuit 4, and the control signal that enables of third level phase inverter output is controlled comparer 6 and shaping circuit 8.
Biasing circuit 7 consists of current source and current mirror, current mirror consists of two PMOS pipes, current source negative pole is connected with antenna negative pole, the grid of the grid of first PMOS pipe of current mirror and drain electrode, second PMOS pipe is connected with current source positive pole, the source electrode of first PMOS pipe of current mirror, the source electrode of second PMOS pipe are connected with antenna positive pole, and the drain electrode of the grid of first PMOS pipe of current mirror, the grid of second PMOS pipe and second PMOS pipe provides bias voltage.
The utility model is large for the traditional demodulation circuit area of passive ultra-high frequency RFID label chip, cost is high, demodulation sensitivity is low, power consumption is high, the shortcomings such as demodulating error is large, have designed a kind of Novel demodulation circuit, have the feature of high sensitivity, low-power consumption, wide input range, meet domestic, international protocol, its technique effect:
(1) in the utility model, the first order adopts the rectification circuit 1 of valve value compensation to realize rectification, has guaranteed the lower normally demodulation of demodulator circuit of low-power input, has embodied highly sensitive feature; Adopt one-level rectification circuit 1 structure to reduce area; NMOS pipe in rectification circuit 1 and PMOS pipe are adopted to high-voltage tube, under larger power input, realize equally demodulation, embodied the feature of wide input range.
(2) by enabling control circuit 5, control averages and produce circuit 4, comparer 6, shaping circuit 8 and whether work, the power consumption when greatly reducing demodulator circuit and not working.
(3) low-pass filter circuit 3 directly adopts RC filtering circuit, has reduced the area of chip.
(4) by 7 pairs of rectification circuits 1 of biasing circuit, average generation circuit 4, comparer 6, provide nA level electric current, the operational amplifier input PMOS pipe differential pair that average is produced in circuit 4 and comparer 6 works in sub-threshold region, greatly reduces the power consumption of whole demodulator circuit.
(5) 8 pairs of restituted signals of shaping circuit carry out shaping, have reduced burr signal, have improved driving force simultaneously.
According to accompanying drawing, progressively analyze a kind of demodulator circuit for passive ultra-high frequency RFID label chip, first illustrated example does not constitute any limitation the application of demodulator circuit.Involved technical characterictic in each embodiment of described the utility model just can not combine mutually as long as do not form each other conflict.
Fig. 1 is demodulator circuit structural representation, in the middle of the structure of this demodulator circuit, comprises rectification circuit 1, gets envelope circuit 2, low-pass filter circuit 3, average produce circuit 4, comparer 6, shaping circuit 8, enable control circuit 5 and biasing circuit 7.Rectification circuit 1 input port is connected with ANT2 port with exterior antenna ANT1 port, and biasing circuit 7 provides offset signal Vbn to rectification circuit, rectification circuit 1 output rectified signal Rec; Get envelope circuit 2 input port access rectified signal Rec, and the envelope signal Env of extraction is sent to low-pass filter circuit, get envelope circuit 2 simultaneously and be subject to enabling the Ena signal controlling that control circuit EN port provides; Low-pass filter circuit 3 input port input envelope signal Env, output port output signal Ina; Average produces circuit 4 input port access signal Ina, is subject to enabling the Enc signal controlling of control circuit, and biasing circuit 7 provides offset signal Vbp to it, output port output signal Inb; Comparer 6 input ports access signal Ina and Inb, are subject to enabling the Enb signal controlling of control circuit, and biasing circuit 7 provides offset signal Vbp to it, output port output signal Com; Shaping circuit 8 input ports access signal Com, are subject to enabling the Enb signal controlling of control circuit 5, output port output restituted signal Demo; Enable control circuit 5 input port EN and provide signal Ena by outside, envelope circuit 2 is got in access simultaneously, and produces control signal Enb control comparer 6 and shaping circuit 8, produces control signal Enc and controls average generation circuit; Biasing circuit 7, to rectification circuit output offset signal Vbn, produces circuit 4 and comparer 6 output offset signal Vbp to average.
When antenna port ANT1 access ground level " 0 " signal, port ANT2 accesses when the radiofrequency signal of ovennodulation, enable control circuit 5 input port EN simultaneously and remain low level " 0 " always, radiofrequency signal is through rectification circuit 1 rectification, AC signal is converted to direct current signal, and improve output signal Rec amplitude, get envelope circuit 2 the Rec signal after improving is carried out to envelope extraction, output envelope signal Env, low-pass filter circuit 3 is by the high fdrequency component filtering of envelope signal Env, output does not contain the signal Ina of high fdrequency component, average produces circuit 4 signal Ina is converted to mean value signal or reference signal Inb, together with signal Ina in input comparator 6, comparer 6 is by comparison output signal Com, signal Com obtains baseband signal or restituted signal Demo through the Shape correction of shaping circuit 8.Demodulator circuit is compared with traditional demodulator circuit, and highly sensitive, input range is large, and area is little, and static current of lcd is lower than 1 μ A, and demodulating error meets national and foreign standards protocol requirement.
Fig. 2 is rectification circuit 1 structural representation, is divided into main and compole, and main comprises metal-oxide-semiconductor MN2, MN3 and capacitor C 2, C4, and compole comprises metal-oxide-semiconductor MN1, MP1 and capacitor C 1, C3.
Described rectification circuit 1 connects low level " 0 " and port ANT1 while connecing high level " 1 " as port ANT2, according to the charge balance of capacitor C 3, the grid level of MN2 will be lifted to a current potential higher than original level, thereby MN2 conducting, signal charges to C2 from port ANT1, and now MN1 disconnects, under the offset signal Vbp effect providing at biasing circuit 7, the electric charge of C3 shifts to C1 by MP1 pipe, and along with the constantly increase disconnection the most at last of grid potential of MP1, MN3 also disconnects; When port ANT2 connects high level " 1 " and port ANT1 while connecing low level " 0 ", according to the charge balance of capacitor C 1 and C2, will cause the unlatching of MN3, C2 charges to capacitor C 4 by MN3, when being charged to certain time, MP1 grid potential is by step-down, thereby MP1 opens, by C1, by MP1, to C3, charged, finally may cause the unlatching of MN1 and MN2, the grid of MN3, because the electric discharge behavior of C1 will make its current potential more and more lower, finally disconnects, and now to the charging process of C4, completed, the signal Rec current potential on C4 will remain unchanged.When port ANT1 and ANT2 add periodic signal, by continuous charge and discharge process, finally realize the rectification to direct current signal by AC signal.Rectification circuit 1 compared with prior art, adopt the mode of valve value compensation to realize, utilize capacitance energy storage and charge balance characteristic, control unlatching and the cut-off state of primary circuit metal-oxide-semiconductor, thereby improved output voltage values, directly solved the low problem of conventional demodulator circuit sensitivity, circuit is realized simple simultaneously.
Fig. 3 gets envelope circuit 2 structural representations, and the phase inverter consisting of MP3 and MN4 is controlled the envelope process of getting, and the circuit equivalent that envelope is got in realization is the parallel connection of a resistance R and capacitor C 5, equivalent resistance R=(R
1+ R
mP2) || R
mN5+ R
mP4, R
1for the resistance of resistance R 1, R
mP2for the source electrode of MP2 and the equivalent resistance between drain electrode, R
mN5for the source electrode of MP5 and the equivalent resistance between drain electrode, R
mP4for the source electrode of MP4 and the equivalent resistance between drain electrode.When signal Ena is low level " 0 ", get envelope process effective, take out envelope signal Env.Get envelope circuit and get envelope with conventional RC and compare, by employing, enable control circuit and control metal-oxide-semiconductor and realize, reduced the area of chip, reduced the power consumption of demodulator circuit off position simultaneously.
Fig. 4 is low-pass filter circuit 3 structural representations, consists of the transfer function H of input/output signal (S)=1/ (1+R resistance R 2 and C6
2c
6s), R
2for the resistance of resistance R 2, C
6for the capacitance of capacitor C 6, the effect of low-pass filter circuit 3 is the high-frequency signal in filtering envelope signal Env, and output does not contain the signal Ina of high fdrequency component.
Fig. 5 is that average produces circuit 4 structural representations, also can be called peak detection circuit, by operational amplifier A 1, the diode MP5 that PMOS pipe forms and capacitor C 7 form, biasing circuit 7 provides bias voltage Vbp to operational amplifier A 1, simultaneously, operational amplifier A 1 is subject to enabling control circuit 5 enable signal Enc and controls, positive terminal input signal Ina, negative pole end input signal Inb, the output terminal of operational amplifier A 1 is connected with one end of diode MP5, the other end of diode MP5 is connected with one end of capacitor C 7 with operational amplifier negative terminal, the other end of capacitor C 7 is connected with port ANT1.
Described average produces circuit 4 and offset signal Vbp is provided and enables under the enable signal Enc condition for validity of control circuit 5 at biasing circuit 7, when input signal Ina is during higher than the turn-on threshold voltage of operational amplifier A 1, the electric current of operational amplifier A 1 output terminal by diode MP5 to capacitor C 7 chargings; When input signal Ina is during lower than the turn-on threshold voltage of operational amplifier A 1, diode MP5 disconnects, and the voltage Inb in capacitor C 7 remains unchanged.So when input signal Ina is periodic signal, average produces circuit Ina is carried out to peak value detection, output signal Inb.Generally speaking, tradition average produces circuit and adopts RC low-pass filter circuit or RC high-pass filtering circuit to realize, and its average generation circuit of the utility model utilizes peak value to detect principle realization, by thering is the load capacitance C7 of energy storage characteristic, obtain more satisfactory mean value signal.
Fig. 6 is comparer 6 structural representations, and biasing circuit 7 provides offset signal Vbp, and enabling control circuit 5 provides and enable control signal Enb, and input anode and negative pole meet respectively signal Ina and signal Inb, output signal Com.
Fig. 7 is shaping circuit 8 structural representations, the phase inverter cascade that the phase inverter being comprised of MN6, MP7 and MN7, MP8 form forms, input signal Com is subject to enable signal Enb and controls by MP6, and 8 pairs of restituted signals of shaping circuit carry out last shaping, output signal Demo.
Fig. 8 enables control circuit 5 structural representations, input port EN provides signal Ena by outside, the phase inverter cascade structure forming with MN9, MN10, MP10 with the phase inverter being comprised of MN8, MP9 is connected, wherein, the grid of MN9 is connected with power supply signal vdd terminal mouth, phase inverter output signal Enc after cascade, phase inverter output enable signal Enb that output signal Enc access is comprised of MN11, MP11.Compared with prior art, whole demodulator circuit has increased and enables control circuit 5 modules and control and get envelope circuit 2, average and produce circuit 4, comparer 6, shaping circuit 8, and when demodulator circuit is not worked, power consumption is extremely low.
Fig. 9 is biasing circuit 7 structural representations, and current source I provides bias voltage Vbp and Vbn by the current mirror consisting of MP12 and MP13.Compared with prior art, biasing circuit 7 provides nA level electric current to rectification circuit 1, average generation circuit 4, comparer 6, and while making whole demodulator circuit work, power consumption is extremely low.
Figure 10 is the waveform schematic diagram of each port of demodulator circuit, and its course of work is as follows,
During step 1:T0, ANT1 port access low level " 0 " signal, ANT2 port access modulated signal, carrier frequency is 922.5MHz, baseband signal speed is 80kb/s.
During step 2:T1, power supply voltage signal VDD powers on and transfers high level " 1 " signal to by low level " 0 " signal.
During step 3:T2, enable port EN transfers low level " 0 " signal to by high level " 1 " signal, enable effectively, demodulator circuit is started working, and rectification circuit 1 output signal REC, low-pass filter circuit 3 output signal Ina, average produce circuit 4 output signal Inb, demodulation waveforms Demo and start normal output.
During step 4:T3, enable port EN transfers high level " 1 " signal to by low level " 0 " signal, and it is invalid to enable, and demodulator circuit quits work.
During step 5:T4, power supply voltage signal VDD transfers low level " 0 " signal to by high level " 1 " signal, and whole demodulator circuit quits work.
During step 6:T5, Transient finishes.
Above said content is only in conjunction with the embodiment in reality; therefore the more embodiment of the utility model can not be restricted; to being familiar with the personnel in this field, according to know-why of the present utility model and embodiment, make some modifications and replacement; all be encompassed in the protection domain of this utility model, the final protection domain of this utility model is as the criterion with claim scope.
Claims (5)
1. the demodulator circuit for passive ultra-high frequency RFID label chip, it is characterized in that, comprise rectification circuit (1), get envelope circuit (2), low-pass filter circuit (3), average produce circuit (4), comparer (6), shaping circuit (8), enable control circuit (5) and biasing circuit (7);
The input end of described rectification circuit (1) is connected with exterior antenna, and the control end of described rectification circuit (1) is connected to the output terminal of described biasing circuit (7); The described input end of getting envelope circuit (2) is connected to the output terminal of described rectification circuit (1), described in get envelope circuit (2) control end connect external control signal; Described in being connected to, gets the input end of described low-pass filter circuit (3) output terminal of envelope circuit (2); The input end of described average generation circuit (4) is connected to the output terminal of described low-pass filter circuit (3), enables the second output terminal of control circuit (5) described in the control end of described average generation circuit (4) is connected to; The first input end of described comparer (6) is connected to the first output terminal that described average produces circuit (4), the second input end of described comparer (6) is connected to the output terminal of described low-pass filter circuit (3), enables the first output terminal of control circuit (5) described in the control end of described comparer (6) connects; The input end of described shaping circuit (8) is connected to the first output terminal of described comparer (6), the first output terminal that enables control circuit (5) described in the control end of described shaping circuit (8) connects, the output terminal of described shaping circuit (8) is used for exporting restituted signal; The input end of described biasing circuit (7) is connected with the second output terminal of described comparer (6) with the second output terminal that described average produces circuit (4); The described input end that enables control circuit (5) connects external control signal, enables control signal and second enable control signal according to described control signal generation first;
Described rectification circuit (1) comprises capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, PMOS pipe MP1, NMOS pipe MN1, NMOS pipe MN2 and NMOS pipe MN3;
After being connected in parallel with one end of described capacitor C 2, one end of described capacitor C 1 is connected with the anodal ANT2 of antenna, the source electrode of described MP1 is connected to the other end of described capacitor C 1, the source electrode of described MP1 is also connected to the grid of described MN3, after the drain electrode of described MP1 is connected with the drain electrode of described MN1 as the control end of described rectification circuit (1); The source electrode of described MN1 is connected to antenna negative pole ANT1;
The drain electrode of described MN3 is as the output terminal of described rectification circuit (1), and the source electrode of described MN3 is connected with the drain electrode of described MN2, and the source electrode of described MN3 is also connected with the grid of described MP1; The source electrode of described MN2 is connected to antenna negative pole ANT1; The grid of described MN2 is connected with the grid of described MN1; The grid of described MN2 is also connected with the drain electrode of described MN1, and the grid of described MN2 is also connected to antenna negative pole ANT1 by described capacitor C 3;
The other end of described capacitor C 2 is connected to the source electrode of described MN3 and the drain electrode link of described MN2; One end of described capacitor C 4 is connected to the drain electrode of described MN3, and the other end of described capacitor C 4 is connected to described antenna negative pole ANT1.
2. demodulator circuit as claimed in claim 1, is characterized in that, described in get envelope circuit (2) and comprising: NMOS pipe MN4, NMOS pipe MN5, PMOS pipe MP2, PMOS pipe MP3, PMOS pipe MP4, resistance R 1 and capacitor C 5;
After being connected, the grid of described MP2, the grid of described MP3, the grid of described MN4 and the grid of described MP4 get the control end of envelope circuit (2) described in conduct, the source electrode of described MP3 is connected to power vd D, the drain electrode of described MP3 is connected with the drain electrode of described MN4, the drain electrode of described MP3 is also connected with the grid of described MN5, and the source electrode of described MN4 is connected to antenna negative pole ANT1;
The source electrode of described MP4 is as the described output terminal of getting envelope circuit (2), and the drain electrode of described MP4 is connected with the drain electrode of described MN5, and the source electrode of described MN5 is connected to antenna negative pole ANT1;
The drain electrode of described MP2 is connected to antenna negative pole ANT1 by described resistance R 1; The source electrode of described MP2 is connected to the drain electrode of described MP4; The source electrode of described MP4 is as the described input end of getting envelope circuit (2);
One end of described capacitor C 5 is connected to the source electrode of described MP4, and the other end of described capacitor C 5 is connected to antenna negative pole ANT1.
3. demodulator circuit as claimed in claim 1, is characterized in that, described average produces circuit (4) and comprising: operational amplifier A 1, diode MP5 and capacitor C 7;
The normal phase input end of described operational amplifier A 1 produces the input end of circuit (4) as described average, the inverting input of described operational amplifier A 1 produces the first output terminal of circuit (4) as described average, the cathode power supply end of described operational amplifier A 1 produces the control end of circuit (4) as described average, the negative electricity source of described operational amplifier A 1 produces the second output terminal of circuit (4) as described average;
The positive pole of described diode MP5 is connected with the output terminal of described operational amplifier A 1, and the negative pole of described diode MP5 is connected with the inverting input of described operational amplifier A 1;
The positive pole of described capacitor C 7 is connected to the inverting input of described operational amplifier A 1, and the negative pole of described capacitor C 7 is used for being connected to antenna negative pole ANT1.
4. demodulator circuit as claimed in claim 1, is characterized in that, described in enable control circuit (5) and comprise NMOS pipe MN8, PMOS pipe MP9, NMOS pipe MN9, NMOS pipe MN10, PMOS pipe MP10, NMOS pipe MN11 and PMOS pipe MP11;
After being connected with the grid of described MN8, the grid of described MP9 enables the input end of control circuit (5) described in conduct, the source electrode of described MP9 connects power vd D, the drain electrode of described MP9 is connected with the drain electrode of described MN8, and the source electrode of described MN8 is connected to antenna negative pole ANT1;
After being connected with the grid of described MN10, the grid of described MP10 is connected with the drain electrode link of described MP9 and MN8, the source electrode of described MP10 connects power vd D, enables the second output terminal of control circuit (5) after the drain electrode of described MP10 is connected with the drain electrode of described MN10 described in conduct; The source electrode of described MP10 is connected with the drain electrode of described MN9, and the source electrode of described MN9 is connected to antenna negative pole ANT1;
After being connected with the grid of described MN11, the grid of described MP11 is connected with the drain electrode link of described MP10 and described MN10, the source electrode of described MP11 connects power vd D, enables the first output terminal of control circuit (5) after the drain electrode of described MP11 is connected with the drain electrode of described MN11 described in conduct; The source electrode of described MN11 is connected to antenna negative pole ANT1.
5. demodulator circuit as claimed in claim 1, is characterized in that, described biasing circuit (7) comprising: current source I, PMOS pipe MP12 and PMOS pipe MP13;
The source electrode of described PMOS pipe MP12 is connected to power vd D, and the drain electrode of described PMOS pipe MP12 is connected to the positive pole of described current source I, and the drain electrode of described PMOS pipe MP12 is also connected with its grid; The negative pole of described current source I is connected to antenna negative pole ANT1;
The source electrode of described PMOS pipe MP13 is connected to power vd D, after the grid of described PMOS pipe MP13 is connected with the grid of described PMOS pipe MP12, as the input end of described biasing circuit (7), the drain electrode of described PMOS pipe MP13 is as the output terminal of described biasing circuit (7).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420375904.8U CN203941545U (en) | 2014-07-07 | 2014-07-07 | A kind of demodulator circuit for passive ultra-high frequency RFID label chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420375904.8U CN203941545U (en) | 2014-07-07 | 2014-07-07 | A kind of demodulator circuit for passive ultra-high frequency RFID label chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104091194B (en) * | 2014-07-07 | 2017-01-25 | 华中科技大学 | Demodulation circuit used for passive ultrahigh frequency RFID label chip |
| CN108268807A (en) * | 2017-12-22 | 2018-07-10 | 中国电子科技集团公司第三十研究所 | A kind of demodulation method to ultrahigh frequency RFID signal under low signal-to-noise ratio |
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2014
- 2014-07-07 CN CN201420375904.8U patent/CN203941545U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104091194B (en) * | 2014-07-07 | 2017-01-25 | 华中科技大学 | Demodulation circuit used for passive ultrahigh frequency RFID label chip |
| CN108268807A (en) * | 2017-12-22 | 2018-07-10 | 中国电子科技集团公司第三十研究所 | A kind of demodulation method to ultrahigh frequency RFID signal under low signal-to-noise ratio |
| CN108268807B (en) * | 2017-12-22 | 2020-10-23 | 中国电子科技集团公司第三十研究所 | Demodulation method for ultrahigh frequency RFID signal under low signal-to-noise ratio |
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