CN100499617C - Comparison and decision circuit in amplitude keying signal demodulation circuit module - Google Patents
Comparison and decision circuit in amplitude keying signal demodulation circuit module Download PDFInfo
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- CN100499617C CN100499617C CNB2006100013670A CN200610001367A CN100499617C CN 100499617 C CN100499617 C CN 100499617C CN B2006100013670 A CNB2006100013670 A CN B2006100013670A CN 200610001367 A CN200610001367 A CN 200610001367A CN 100499617 C CN100499617 C CN 100499617C
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Abstract
The invention relates to a compare and decide circuit of amplitude key-control signal demodulation circuit, belonging to the analogue signal process and radio frequency recognize technique. Said circuit comprises: a differential coefficient circuit, a reference voltage generation circuit, a hysteresis comparator circuit, and a bias voltage generate circuit. Wherein, said differential coefficient circuit is formed by a PMOS tube, a NMOS tube and a capacitor; said reference voltage generation circuit is formed by a PMOS tube, a NMOS tube and a capacitor. The invention can solve the problem that modulation depth is too shallow of the modulation signal sent from the Reader to the Tag in RFID protocol (as ISO/IEC FDIS 18000-6 protocol), and it can simple structure, small and high sensitivity.
Description
Technical field
The invention belongs to analog and REID (RFID) field, particularly RFID label (Tag) is gone up the comparison decision circuit in amplitude keying (ASK) the signal demodulating circuit module.
Background technology
In rfid system, Reader (card reader) is by communicating to Tag (label) emission rf modulated signal and Tag.In ISO/IEC FDIS 18000-6 agreement, this modulation signal is amplitude keying (ASK) signal of the degree of depth more shallow when the most shallow (can reach 27%).The effect of the demodulator circuit module on the Tag is demodulated into standard digital signals with the ASK signal exactly, exports to digital circuit and uses.The general demodulator circuit structure that is used for the more shallow ASK signal of the demodulation degree of depth as shown in Figure 1, form by envelope detection circuit, comparison decision circuit, shaping output circuit, its operation principle is: at first extract signal envelope by envelope detection circuit, r-f component in the filtered signal, by comparing decision circuit the high-low level of envelope detection output signal is adjudicated then, the output signal that last shaping output circuit will compare decision circuit is carried out shaping, and providing high level is that supply voltage, low level are 0 digital signal.
The composition of the comparison decision circuit in the above-mentioned demodulator circuit module generally as shown in Figure 2, comprise: differential circuit, generating circuit from reference voltage, hysteresis loop comparator circuit and bias-voltage generating circuit, wherein, differential circuit, generating circuit from reference voltage, hysteresis loop comparator circuit and bias-voltage generating circuit, wherein, the output of described differential circuit and generating circuit from reference voltage links to each other with the input of hysteresis loop comparator circuit, and described bias-voltage generating circuit links to each other with differential circuit, generating circuit from reference voltage and hysteresis loop comparator circuit respectively.Its operation principle is: differential circuit, and be used for rising edge, the trailing edge of detected envelope detecting circuit output signal, and provide a forward spike at rising edge, provide a negative sense spike at trailing edge; Generating circuit from reference voltage is used to provide stable reference voltage; The hysteresis loop comparator circuit is used for the output and the reference voltage of differential circuit are compared, and provides decision signal; Bias-voltage generating circuit is used to differential circuit, generating circuit from reference voltage, hysteresis loop comparator circuit that stable direct current biasing is provided.
Differential circuit in the above-mentioned relatively decision circuit generally is made of resistance R capacitor C network, as shown in Figure 3.
The comparison decision circuit of said structure has the following disadvantages:
Owing to used resistance in the differential circuit, when realizing, exist the problem that area is big, noise is big with method integrated on the sheet, be unfavorable for dwindling the area of RFID Tag and improve demodulation accuracy.
Summary of the invention
The objective of the invention is the demodulation problem for the more shallow ASK signal of modulation depth, propose the comparison decision circuit in a kind of amplitude keying signal demodulation circuit module, have characteristics simple in structure, that area is little, demodulation sensitivity is high at RFID Tag.
Comparison decision circuit in amplitude keying of the present invention (ASK) the signal demodulating circuit module, comprise: differential circuit, generating circuit from reference voltage, hysteresis loop comparator circuit and bias-voltage generating circuit, the output of described differential circuit and generating circuit from reference voltage links to each other with the input of hysteresis loop comparator circuit, described bias-voltage generating circuit respectively with differential circuit, generating circuit from reference voltage and hysteresis loop comparator circuit link to each other, wherein, differential circuit, the rising edge that is used for detected envelope detecting circuit output signal, trailing edge, and provide a forward spike at rising edge, provide a negative sense spike at trailing edge; Generating circuit from reference voltage is used to provide stable reference voltage; The hysteresis loop comparator circuit is used for the output and the reference voltage of differential circuit are compared, and provides decision signal; Bias-voltage generating circuit is used to differential circuit, generating circuit from reference voltage, hysteresis loop comparator circuit that stable direct current biasing is provided; It is characterized in that, described differential circuit by a PMOS manage, NMOS pipe and an electric capacity constitutes, wherein the grid of NMOS pipe and drain electrode are connected together, the drain electrode of the drain electrode of PMOS pipe and NMOS pipe links to each other and links to each other with an input of hysteresis loop comparator circuit, the grid of PMOS pipe connects the direct current biasing that is provided by bias-voltage generating circuit, the source ground of NMOS pipe, the source electrode of PMOS pipe connects power supply, the input (connect the signal output of grade envelope detection circuit) of one end of described electric capacity for comparing decision circuit, the grid of the described NMOS pipe of another termination; Described generating circuit from reference voltage by a PMOS manage, NMOS pipe and an electric capacity constitutes, wherein the grid of NMOS pipe and drain electrode are connected together, the drain electrode of the drain electrode of PMOS pipe and NMOS pipe links to each other and links to each other with another input of hysteresis loop comparator circuit, the grid of PMOS pipe connects the direct current biasing that is provided by bias-voltage generating circuit, the source ground of NMOS pipe, the source electrode of PMOS pipe connects power supply, the grid of a termination NMOS pipe of described electric capacity, other end ground connection.
Characteristics of the present invention and technique effect:
The present invention has adopted along the mode that detects for the envelope detection signal, uses the rising of differential circuit detection signal, trailing edge.The realization of differential circuit is not to adopt common RC network (resistance can take bigger area and produce bigger noise), but has adopted the metal-oxide-semiconductor under the constant bias to replace resistance, does like this to have reduced chip area, has reduced noise; Simultaneously, the structure of receiving the differential circuit module of two inputs of comparator and generating circuit from reference voltage module respectively except the size of electric capacity with connection is different, all the other structures are identical, and this helps eliminating among the passive RFID Tag common-mode signal that the fluctuation owing to supply voltage produces.
Differential circuit and generating circuit from reference voltage cooperate highly sensitive hysteresis loop comparator to make this circuit effectively to detect the ASK signal that amplitude is little in the rfid system, modulation depth is shallow with simple circuit configuration and less circuit area again.
Description of drawings
Fig. 1 is the general structure schematic diagram of common ASK demodulator circuit.
Fig. 2 is existing a kind of relatively decision circuit structural representation.
Fig. 3 is existing a kind of differential circuit schematic diagram
Fig. 4 is a differential circuit schematic diagram of the present invention.
Fig. 5 is input, the signal output waveform figure of differential circuit of the present invention.
Fig. 6 is a generating circuit from reference voltage structural representation of the present invention.
Fig. 7 is an exemplary construction schematic diagram of the used hysteresis loop comparator of the present invention.
Embodiment
The present invention proposes be used for RFID Tag, be described with reference to the accompanying drawings as follows at the demodulator circuit of the more shallow ASK signal of modulation depth:
Relatively decision circuit general structure of the present invention as shown in Figure 2.Comprise differential circuit, generating circuit from reference voltage, hysteresis loop comparator circuit and bias-voltage generating circuit, wherein, the output of described differential circuit and generating circuit from reference voltage links to each other with the input of hysteresis loop comparator circuit, described bias-voltage generating circuit links to each other with differential circuit, generating circuit from reference voltage and hysteresis loop comparator circuit respectively, for differential circuit, generating circuit from reference voltage, hysteresis loop comparator circuit provide stable direct current biasing; Radio frequency ASK signal provides a forward and negative sense spike by differential circuit respectively at signal rising edge and falling edge after the envelope detection circuit rectification, hysteresis loop comparator compares the output and the reference voltage of differential circuit, provides decision signal.
Wherein, the structure of differential circuit of the present invention as shown in Figure 4.This differential circuit is made of PMOS pipe M6, a NMOS pipe M7 and a capacitor C 3; Wherein grid and the drain electrode of NMOS pipe M7 are connected together, the drain electrode of PMOS pipe M6 links to each other and links to each other with an input of hysteresis loop comparator circuit with the drain electrode of NMOS pipe M7, the grid of PMOS pipe M6 connects the direct current biasing that is provided by bias-voltage generating circuit, the source ground of NMOS pipe M7, the source electrode of PMOS pipe M6 connects power supply; The input (connect the signal output of grade envelope detection circuit) of one end of capacitor C 3 for comparing decision circuit, the grid of another termination NMOS pipe M7; Pbias is the dc offset voltage that is provided by bias-voltage generating circuit, the output of IN termination envelope detection circuit, an input of COMP1 termination comparator.The operation principle of circuit is: when direct voltage of IN end input, because electric capacity is equivalent to open circuit for direct current signal, so the voltage of COMP1 end output is not subjected to the influence of IN end level, only by the size decision of voltage pbias and M6, M7, is made as Vs; When the IN end signal takes place just (bearing) to saltus step, since the coupling of electric capacity, the voltage of COMP1 end also can just produce thereupon (bear) to saltus step, but owing to the effect that discharges and recharges of M6, M7, after through an extremely short time, the voltage of COMP1 end still can return to steady-state value Vs.So the general effect of this circuit is: when the envelope detection output signal was in high level or low level, the output voltage of COMP1 all was Vs; When the envelope detection output signal becomes low level by high level, produce a positive spike at the COMP1 end, and when the envelope detection output signal becomes high level by low level, produce a negative spike, as shown in Figure 5 at the COMP1 end.
The structure of generating circuit from reference voltage of the present invention as shown in Figure 6.Constitute by PMOS pipe M8, a NMOS pipe M9 and a capacitor C 4; Wherein grid and the drain electrode of NMOS pipe M9 are connected together, the drain electrode of PMOS pipe M8 links to each other and links to each other with another input of hysteresis loop comparator circuit with the drain electrode of NMOS pipe M9, the grid of PMOS pipe M8 connects the direct current biasing that is provided by bias-voltage generating circuit, the source ground of NMOS pipe M9, the source electrode of PMOS pipe M8 connects power supply; One end ground connection of capacitor C 4, the grid of another termination NMOS pipe M9; Pbias is the dc offset voltage that is provided by bias-voltage generating circuit, and is identical with pbias shown in Figure 4, another input of COMP2 termination comparator; The size of M8, M9 is identical with the size difference of M6, M7 among Fig. 4, and the voltage of COMP2 just equals the steady-state value Vs of COMP1 like this; The value of capacitor C 4 is greater than the value of C3 among Fig. 4, this be for RFID the startup stage, make the rate of climb of COMP2 less than the rate of climb of COMP1, thereby give initial set value of comparator; The general function of generating circuit from reference voltage just provides a galvanic current and presses Vs, is used for comparing with the differential circuit output signal.
Hysteresis loop comparator of the present invention can adopt a variety of implementations.Fig. 7 provides an existing a kind of structure as embodiments of the invention.The hysteresis loop comparator of present embodiment manages M153, M3, M4 by PMOS and NMOS pipe M44, M45, M47, M48 form, and BIAS is a direct current biasing, is provided by generating circuit from reference voltage, and COMP1 and COMP2 are two inputs, and OUT is an output.
Bias-voltage generating circuit of the present invention is made of common a reference source.
The course of work of whole relatively decision circuit is: the startup stage of RFID, the value of COMP1 and COMP2 is all rising, but because the varying in size of node capacitance C3, C4, the speed that COMP1 rises is greater than COMP2, so high level of hysteresis loop comparator output.Final COMP1 and COMP2 will rise to Vs.Next interim when the signal trailing edge, COMP1 produces a negative-going pulse, and COMP2 remains unchanged, so low level of hysteresis loop comparator output; When COMP1 returned to Vs, because the lagging characteristics of comparator, the OUT end kept low level constant, comes temporarily up to the signal rising edge, and COMP1 produces a direct impulse, and the output of comparator is just overturn and is high level.
Claims (1)
1, the comparison decision circuit in a kind of amplitude keying signal demodulation circuit module, this circuit comprises: differential circuit, generating circuit from reference voltage, hysteresis loop comparator circuit and bias-voltage generating circuit, wherein, the output of described differential circuit and generating circuit from reference voltage links to each other with the input of hysteresis loop comparator circuit, and described bias-voltage generating circuit links to each other with differential circuit, generating circuit from reference voltage and hysteresis loop comparator circuit respectively; It is characterized in that, described differential circuit is by first PMOS pipe, first NMOS pipe and first electric capacity constitute, wherein the grid of first NMOS pipe and drain electrode are connected together, the drain electrode of the drain electrode of first PMOS pipe and NMOS pipe links to each other and links to each other with an input of hysteresis loop comparator circuit, the grid of first PMOS pipe connects the direct current biasing that is provided by bias-voltage generating circuit, the source ground of first NMOS pipe, the source electrode of first PMOS pipe connects power supply, one end of described first electric capacity is for comparing the input of decision circuit, the grid of described first NMOS pipe of another termination; Described generating circuit from reference voltage by second PMOS manage, second NMOS pipe and second electric capacity constitutes, wherein the grid of second NMOS pipe and drain electrode are connected together, the drain electrode of the drain electrode of second PMOS pipe and second NMOS pipe links to each other and links to each other with another input of hysteresis loop comparator circuit, the grid of second PMOS pipe connects the direct current biasing that is provided by bias-voltage generating circuit, the source ground of second NMOS pipe, the source electrode of second PMOS pipe connects power supply, the grid of second NMOS pipe of one termination of described second electric capacity, other end ground connection; The structure of receiving the differential circuit of two inputs of comparator and generating circuit from reference voltage respectively except the size of electric capacity with connection is different, all the other structures are identical.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100013670A CN100499617C (en) | 2006-01-20 | 2006-01-20 | Comparison and decision circuit in amplitude keying signal demodulation circuit module |
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| CNB2006100013670A CN100499617C (en) | 2006-01-20 | 2006-01-20 | Comparison and decision circuit in amplitude keying signal demodulation circuit module |
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| CN1805416A CN1805416A (en) | 2006-07-19 |
| CN100499617C true CN100499617C (en) | 2009-06-10 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105635011A (en) * | 2014-11-20 | 2016-06-01 | 联发科技（新加坡）私人有限公司 | Signal demodulation apparatus |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010267253A (en) * | 2009-04-16 | 2010-11-25 | Semiconductor Energy Lab Co Ltd | Demodulation signal generation circuit, and semiconductor device with the same |
| CN102103679B (en) * | 2009-12-18 | 2014-10-15 | 上海华虹集成电路有限责任公司 | A/B mode detection circuit adaptive to variation of field intensity |
| CN102446286B (en) * | 2010-10-12 | 2014-02-26 | 上海华虹宏力半导体制造有限公司 | ASK (Amplitude Shift Keying) demodulator of RFID (Radio Frequency Identification) label analog front-end circuit |
| CN102004939B (en) * | 2010-11-30 | 2012-05-30 | 电子科技大学 | Demodulator circuit for the UHF (Ultrahigh Frequency) radio frequency identification label chip |
| CN103714374B (en) * | 2012-09-28 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | The demodulator circuit of A type contactless IC card |
| CN104299024B (en) * | 2013-07-19 | 2018-08-21 | 上海华虹宏力半导体制造有限公司 | The demodulator circuit of contactless IC card |
| CN110995402B (en) * | 2019-11-29 | 2021-09-07 | 三维通信股份有限公司 | Synchronization pulse transmission method, device and system |
| CN114244389A (en) * | 2021-11-12 | 2022-03-25 | 北京智芯微电子科技有限公司 | Terminal chip, base station device, and bidirectional wireless communication system |
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| US5875126A (en) * | 1995-09-29 | 1999-02-23 | California Institute Of Technology | Autozeroing floating gate amplifier |
| CN1325581A (en) * | 1998-11-05 | 2001-12-05 | 因芬尼昂技术股份公司 | Method for ASK demodulation and ASK demodulator |
| CN1492591A (en) * | 2002-10-26 | 2004-04-28 | 深圳市中兴通讯股份有限公司 | Failure protective circuit for low voltage differential receiver |
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2006
- 2006-01-20 CN CNB2006100013670A patent/CN100499617C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5875126A (en) * | 1995-09-29 | 1999-02-23 | California Institute Of Technology | Autozeroing floating gate amplifier |
| CN1325581A (en) * | 1998-11-05 | 2001-12-05 | 因芬尼昂技术股份公司 | Method for ASK demodulation and ASK demodulator |
| CN1492591A (en) * | 2002-10-26 | 2004-04-28 | 深圳市中兴通讯股份有限公司 | Failure protective circuit for low voltage differential receiver |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105635011A (en) * | 2014-11-20 | 2016-06-01 | 联发科技（新加坡）私人有限公司 | Signal demodulation apparatus |
| CN105635011B (en) * | 2014-11-20 | 2018-12-28 | 联发科技（新加坡）私人有限公司 | Signal demodulating equipment and method |
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| CN1805416A (en) | 2006-07-19 |
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