CN203896321U - Multi-mode signal generating device - Google Patents
Multi-mode signal generating device Download PDFInfo
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- CN203896321U CN203896321U CN201320873876.8U CN201320873876U CN203896321U CN 203896321 U CN203896321 U CN 203896321U CN 201320873876 U CN201320873876 U CN 201320873876U CN 203896321 U CN203896321 U CN 203896321U
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Abstract
The utility model relates to a multi-mode signal generating device, and the device comprises a DSP controller. The input/output end of the DSP controller is connected with the input/output end of an FPGA controller. The output ends of the FPGA controller and a second local oscillator unit LO2 are respectively connected with the input end of a second frequency-mixing unit. The output end of the second frequency-mixing unit and a first local oscillator unit LO1 are respectively connected with the input end of a first frequency-mixing unit. The output end of the first frequency-mixing unit is connected with the input end of a radio-frequency signal-conditioning module, and the output end of the radio-frequency signal-conditioning module serves as the output end of the device. The input/output end of a CPU (central processing unit) is connected with the input end of the FPGA controller, the input end of the second local oscillator unit LO2 and the input end of the second local oscillator unit LO1. The device achieves the quick and dynamic scheduling in different modes, improves the execution speed of a system, reduces the risk of test errors, and improves the stability of a multi-mode signal source.
Description
Technical field
The utility model relates to GSM, WCDMA, TD_SCDMA and the calibration of TD_LTE mobile communication terminal and mobile communication teaching field, especially a kind of multimode signal generating means and signal generating method thereof.
Background technology
Along with the propelling that deepens continuously of LTE industrialization, tester more and more receives the concern of industry as the important component part of industrial chain.At present, in the situation that LTE, 3G and 2G multiple network coexist, must ensure the compatibility of terminal in various mode networks.For meeting the demand of terminal research and development, certification, production line, special on production line for the consideration to testing cost, need to support 2G/3G/4G multimode test instrumentation simultaneously.China takes a firm foundation in the research and development of terminal test instrument, support the research and development of LTE multimode test instrumentation to produce important meaning to improving industrial chain aspect, wherein multimode signal source is encircled as the key one in the research and development of multimode instrument, and the research and development of chip, terminal are played to critical effect.At present, on market including external instrument, the signal generation apparatus of including GSM, WCDMA, TD_SCDMA, TD_LTE standard simultaneously and can loading subscriber simulation data does not also exist, therefore support GSM, WCDMA, TD_SCDMA, TD_LTE standard and can load research and development and the popularization of the signal source of subscriber simulation data, also have great importance for competition and the development of instrument industry and mobile terminal production industry.
Traditional multimode signal source adopts many radio frequencies hardware conventionally, and multisystem simulator is relatively wasted resource, and switching complexity brings switch speed slow.In addition, often occur that a multimode signal source cannot include the problem of GSM, WCDMA, TD_SCDMA, TD_LTE standard, therefore research and develop a signal source that comprises four kinds of standards above extremely urgent.Even have above-mentioned standard also to exist multi-clock conversion and pattern to switch the problem that need to reload for traditional multimode signal source, then digital medium-frequency signal is carried out to D/A switch, and in the time that different mode signal switches, need to upgrade the system simulator of required standard.
Utility model content
The purpose of this utility model is to provide one to support GSM, WCDMA, TD_SCDMA, tetra-kinds of patterns of TD_LTE simultaneously, can load the multimode signal generating means of subscriber simulation data.
For achieving the above object, the utility model has adopted following technical scheme: a kind of multimode signal generating means, comprise dsp controller, its input/output terminal is connected with the input/output terminal of FPGA controller, FPGA controller, the output of the second local oscillator unit LO2 is all connected with the input of the second mixing unit, the second mixing unit, the output of the first local oscillator unit LO1 is all connected with the input of the first mixing unit, the output of the first mixing unit is connected with the input of radiofrequency signal conditioning module, the output of radiofrequency signal conditioning module is as device output, the input/output terminal of central processor CPU respectively with FPGA controller, the second local oscillator unit LO2, the input/output terminal of the first local oscillator unit LO1 is connected.
The output of clock-generating device module is connected with the input of dsp controller, FPGA controller respectively.
Described dsp controller comprises GSM base band generation module, TD_SCDMA base band generation module, WCDMA base band generation module and TD_LTE base band generation module, described FPGA controller comprise all-digital IF processing module and with D/A modular converter, GSM base band generation module, TD_SCDMA base band generation module, WCDMA base band generation module, the input/output terminal of TD_LTE base band generation module is all connected with the input/output terminal of all-digital IF processing module, the output of all-digital IF processing module is connected with the input of D/A modular converter, the output of D/A modular converter is connected with the input of the second mixing unit.
The output of described central processor CPU is connected with the input of subscriber simulation data module, and the output of subscriber simulation data module is connected with the input of FPGA controller by pci bus.
The input/output terminal of described central processor CPU is connected with the input/output terminal of FPGA controller, the second local oscillator unit LO2, the first local oscillator unit LO1 respectively by pci bus.
Described clock-generating device module comprises phase discriminator, its input connects respectively 10MHZ reference clock, the output of 1/200 frequency divider, its output is connected with the input of the first low pass filter, the output of the first low pass filter is connected with the input of voltage controlled oscillator VCO, the output of voltage controlled oscillator VCO is connected with the input of the first power splitter, the output of the first power splitter respectively with Direct Digital Frequency Synthesizers AD9858, the input of 1/200 frequency divider is connected, the output of Direct Digital Frequency Synthesizers AD9858 is connected with the input of the second low pass filter, the output of the second low pass filter is connected with the input of the second power splitter, the first output of the second power splitter is connected with the input end of clock of the D/A modular converter of FPGA controller, the second output of the second power splitter is connected with the input end of clock of dsp controller by 1/5 frequency divider.
The input/output terminal of described GSM base band generation module, TD_SCDMA base band generation module, WCDMA base band generation module, TD_LTE base band generation module is all connected with the input/output terminal of all-digital IF processing module by high-speed serial bus RAPIDIO.
As shown from the above technical solution, in the utility model, not only the base band signal process of different mode is parallel processing in dsp controller, and in the Digital IF Processing of different mode, be also parallel processing, then fixed intermediate frequency output, only need to upgrade model selection mark by central processor CPU when switching.Due to the modularized design of base band and intermediate frequency, thereby a difficult problem for the poor stability bringing because of switching radio-frequency module, clock generation module and all-digital IF processing module in traditional approach has been avoided in parallel processing, different mode long problem switching time, thereby realize the quick dynamic dispatching of different mode, improve system execution speed, reduce the risk that test makes mistakes, improved the stability in multimode signal source.
Brief description of the drawings
Fig. 1 is circuit block diagram of the present utility model;
Fig. 2 is the circuit block diagram of clock-generating device module in Fig. 1;
Fig. 3 is the method flow schematic diagram of multimode baseband processing method of the present utility model;
Fig. 4 is the method flow schematic diagram of Digital IF Processing method of the present utility model.
Embodiment
A kind of multimode signal generating means, comprise dsp controller 1, its input/output terminal is connected with the input/output terminal of FPGA controller 2, FPGA controller 2, the output of the second local oscillator unit LO2 is all connected with the input of the second mixing unit, the second mixing unit, the output of the first local oscillator unit LO1 is all connected with the input of the first mixing unit, the output of the first mixing unit is connected with the input of radiofrequency signal conditioning module, the output of radiofrequency signal conditioning module is as device output, the input/output terminal of central processor CPU respectively with FPGA controller 2, the second local oscillator unit LO2, the input/output terminal of the first local oscillator unit LO1 is connected, the output of clock-generating device module 3 respectively with dsp controller 1, the input of FPGA controller 2 is connected, as shown in Figure 1.Clock-generating device module 3 produces the work clock of the D/A work clock of 614.4MHz and the dsp controller 1 of 122.88MHz.
As shown in Figure 1, described dsp controller 1 comprises GSM base band generation module, TD_SCDMA base band generation module, WCDMA base band generation module and TD_LTE base band generation module, described FPGA controller 2 comprise all-digital IF processing module and with D/A modular converter, GSM base band generation module, TD_SCDMA base band generation module, WCDMA base band generation module, the input/output terminal of TD_LTE base band generation module is all connected with the input/output terminal of all-digital IF processing module, the output of all-digital IF processing module is connected with the input of D/A modular converter, the output of D/A modular converter is connected with the input of the second mixing unit.The output of described central processor CPU is connected with the input of subscriber simulation data module, and the output of subscriber simulation data module is connected with the input of FPGA controller 2 by pci bus.The input/output terminal of described central processor CPU is connected with the input/output terminal of FPGA controller 2, the second local oscillator unit LO2, the first local oscillator unit LO1 respectively by pci bus.The input/output terminal of described GSM base band generation module, TD_SCDMA base band generation module, WCDMA base band generation module, TD_LTE base band generation module is all connected with the input/output terminal of all-digital IF processing module by high-speed serial bus RAPIDIO.
As shown in Figure 2, described clock-generating device module 3 comprises phase discriminator, its input connects respectively 10MHZ reference clock, the output of 1/200 frequency divider, its output is connected with the input of the first low pass filter, the output of the first low pass filter is connected with the input of the voltage controlled oscillator VCO of 2GHz, the output of voltage controlled oscillator VCO is connected with the input of the first power splitter, the output of the first power splitter respectively with Direct Digital Frequency Synthesizers AD9858, the input of 1/200 frequency divider is connected, Direct Digital Frequency Synthesizers AD9858 internal control has phase accumulator, look-up table, DAC, the clock of output 614.4MHz, the output of Direct Digital Frequency Synthesizers AD9858 is connected with the input of the second low pass filter, the output of the second low pass filter is connected with the input of the second power splitter, the first output of the second power splitter is connected with the input end of clock of the D/A modular converter of FPGA controller 2, the second output of the second power splitter is connected with the input end of clock of dsp controller 1 by 1/5 frequency divider, export 122.88MHz to dsp controller 1 through 1/5 frequency divider.
In the time of work, its workflow comprises the step of following order: (1) dsp controller 1 carries out multimode Base-Band Processing, generates respectively GSM base band, TD_SCDMA base band, WCDMA base band, the output of TD_LTE base band data; (2) under the control of central processor CPU, FPGA controller 2 carries out parallel Digital IF Processing to the base band data of different mode, output analog if signal; (3) analog if signal is successively after the second, first local oscillator mixing, then gain and filtering conditioning generates RF signal and exports through radiofrequency signal conditioning module.
As shown in Figure 3, described multimode baseband processing method refers to, carry out parallel processing in multimode base band, for GSM base band generation module, the signal source that gsm system simulator configures by central processor CPU and relevant parameter configure the processing of first encoding, modulate and pass through real empty separation through GMSK and generate the I/Q data that chip rate is 270.833Ksps, carry out Digital Up Convert in all-digital IF processing module again, then filtering interpolation closes the output of roadbed band; For WCDMA base band generation module, first the signal source that WCDMA system simulator configures by central processor CPU and relevant parameter configure the processing of first encoding, carry out OVSF orthogonal sequence spread spectrum according to different channels again, produce required scrambler by m sequence according to up-downgoing channel, then carry out physical channel merging, the real empty I/Q data that generation chip rate is 3.84Msps that separate, then in all-digital IF processing module, carry out Digital Up Convert, filtering interpolation so finally closes the output of roadbed band; For TD-SCDMA base band generation module, TD-SCDMA system simulator configures according to the signal source of central processor CPU configuration and relevant parameter the processing of first encoding, enter spread spectrum, scrambling, generated midamble code according to midamble code table, and select user, subframe forms and generate chip rate after real empty separation is 1.28 Msps I/Q data, then in all-digital IF processing module, carries out Digital Up Convert, closes road and then carries out base band output; For TD-LTE base band generation module, TD-LTE system simulator also will configure the processing of first encoding according to the signal source of central processor CPU configuration and relevant parameter, after inserting CP, scrambling, modulation, layer mapping, precoding and IFFT generate again the I/Q data of chip rate 30.72Msps, through filtering interpolation and then the output of generation base band data.
As shown in Figure 4, described Digital IF Processing method refers to, the I/Q data of the 270.833Kcps producing for GSM base band generation module, carry out 32 times of interpolation and generate 8.66Msps data, carry out nonuniform sampling processing and FIR formed filter generation 7.68Msps data through oversampling clock, generate 307.2MspsI/Q data through 3 grade of half band HB interpolation and 5 times of CIC again, then carry out sending into the D/A modular converter that work clock is 614.4MHz behind I/QHe road, the analog if signal of output 153.6M; The I/Q data of the 3.84Mcps producing for WCDMA base band generation module, carry out 4 times of interpolation, generate 15.36Msps data through clock sampling and FIR formed filter, generate 307.2Msps through 2 grade of half band HB interpolation and 5 times of CIC again, same JingI/QHe sends into the D/A modular converter that work clock is 614.4MHz behind road, the analog if signal of output 153.6M; The I/Q data of the 1.28Mcps producing for TD-SCDMA base band generation module, carry out 6 times of interpolation, generate 7.68Msps data through clock sampling and FIR formed filter, generate 307.2Msps through 3 grade of half band HB interpolation and 5 times of CIC again, behind JingI/QHe road, sending into work clock is the D/A modular converter of 614.4MHz, the analog if signal of output 153.6M; The I/Q data of the 30.72Msps producing for TD-LTE base band generation module, carry out 2 times of interpolation, generate 61.44Msps data through clock sampling and FIR formed filter, generate 307.2Msps data through 5 times of CIC again, same I/QHe sends into the D/A modular converter that work clock is 614.4MHz behind road, the analog if signal of output 153.6M; Central processor CPU loads subscriber simulation data module, and user arranges interpolation multiple, half band and CIC interpolation multiple by subscriber simulation data module.
In sum, in the utility model, not only the base band signal process of different mode is parallel processing in dsp controller 1, and in the Digital IF Processing of different mode, be also parallel processing, then fixed intermediate frequency output, only need to upgrade model selection mark by central processor CPU when switching.Due to the modularized design of base band and intermediate frequency, thereby a difficult problem for the poor stability bringing because of switching radio-frequency module, clock generation module and all-digital IF processing module in traditional approach has been avoided in parallel processing, different mode long problem switching time, thereby realize the quick dynamic dispatching of different mode, improve system execution speed, reduce the risk that test makes mistakes, improved the stability in multimode signal source.
Claims (7)
1. a multimode signal generating means, it is characterized in that: comprise dsp controller (1), its input/output terminal is connected with the input/output terminal of FPGA controller (2), FPGA controller (2), the output of the second local oscillator unit LO2 is all connected with the input of the second mixing unit, the second mixing unit, the output of the first local oscillator unit LO1 is all connected with the input of the first mixing unit, the output of the first mixing unit is connected with the input of radiofrequency signal conditioning module, the output of radiofrequency signal conditioning module is as device output, the input/output terminal of central processor CPU respectively with FPGA controller (2), the second local oscillator unit LO2, the input/output terminal of the first local oscillator unit LO1 is connected.
2. multimode signal generating means according to claim 1, is characterized in that: the output of clock-generating device module (3) is connected with the input of dsp controller (1), FPGA controller (2) respectively.
3. multimode signal generating means according to claim 1, it is characterized in that: described dsp controller (1) comprises GSM base band generation module, TD_SCDMA base band generation module, WCDMA base band generation module and TD_LTE base band generation module, described FPGA controller (2) comprise all-digital IF processing module and with D/A modular converter, GSM base band generation module, TD_SCDMA base band generation module, WCDMA base band generation module, the input/output terminal of TD_LTE base band generation module is all connected with the input/output terminal of all-digital IF processing module, the output of all-digital IF processing module is connected with the input of D/A modular converter, the output of D/A modular converter is connected with the input of the second mixing unit.
4. multimode signal generating means according to claim 1, it is characterized in that: the output of described central processor CPU is connected with the input of subscriber simulation data module, the output of subscriber simulation data module is connected with the input of FPGA controller (2) by pci bus.
5. multimode signal generating means according to claim 1, is characterized in that: the input/output terminal of described central processor CPU is connected with the input/output terminal of FPGA controller (2), the second local oscillator unit LO2, the first local oscillator unit LO1 respectively by pci bus.
6. multimode signal generating means according to claim 2, it is characterized in that: described clock-generating device module (3) comprises phase discriminator, its input connects respectively 10MHZ reference clock, the output of 1/200 frequency divider, its output is connected with the input of the first low pass filter, the output of the first low pass filter is connected with the input of voltage controlled oscillator VCO, the output of voltage controlled oscillator VCO is connected with the input of the first power splitter, the output of the first power splitter respectively with Direct Digital Frequency Synthesizers AD9858, the input of 1/200 frequency divider is connected, the output of Direct Digital Frequency Synthesizers AD9858 is connected with the input of the second low pass filter, the output of the second low pass filter is connected with the input of the second power splitter, the first output of the second power splitter is connected with the input end of clock of the D/A modular converter of FPGA controller (2), the second output of the second power splitter is connected with the input end of clock of dsp controller (1) by 1/5 frequency divider.
7. multimode signal generating means according to claim 3, is characterized in that: the input/output terminal of described GSM base band generation module, TD_SCDMA base band generation module, WCDMA base band generation module, TD_LTE base band generation module is all connected with the input/output terminal of all-digital IF processing module by high-speed serial bus RAPIDIO.
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| CN201320873876.8U CN203896321U (en) | 2013-12-26 | 2013-12-26 | Multi-mode signal generating device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103647529A (en) * | 2013-12-26 | 2014-03-19 | 中国电子科技集团公司第四十一研究所 | Multimode signal generating device and signal generating method thereof |
| CN115022141A (en) * | 2022-06-17 | 2022-09-06 | 四川九洲电器集团有限责任公司 | GMSK signal digital modulation transmitting device and method |
-
2013
- 2013-12-26 CN CN201320873876.8U patent/CN203896321U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103647529A (en) * | 2013-12-26 | 2014-03-19 | 中国电子科技集团公司第四十一研究所 | Multimode signal generating device and signal generating method thereof |
| CN103647529B (en) * | 2013-12-26 | 2017-03-22 | 中国电子科技集团公司第四十一研究所 | Multimode signal generating device and signal generating method thereof |
| CN115022141A (en) * | 2022-06-17 | 2022-09-06 | 四川九洲电器集团有限责任公司 | GMSK signal digital modulation transmitting device and method |
| CN115022141B (en) * | 2022-06-17 | 2023-05-26 | 四川九洲电器集团有限责任公司 | GMSK signal digital modulation transmitting device and method |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20141022 Effective date of abandoning: 20171114 |
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| AV01 | Patent right actively abandoned |