CN103595373A - Nine-component mixed signal generator and generation method of nine-component mixed signal - Google Patents
Nine-component mixed signal generator and generation method of nine-component mixed signal Download PDFInfo
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Abstract
The invention discloses a nine-component mixed signal generator and a generation method of a nine-component mixed signal. The nine-component mixed signal comprises a direct current component, a pulse component and seven sine components, and the amplitude, the frequency, the pulse width and the initial phase of each component can be set. A waveform generation circuit comprises a single FPGA and an analog circuit, wherein the analog circuit comprises four links of amplitude transformation, impulse wave transformation, sine wave mixing and full-component overlapping, and the FPGA and the analog circuit are provided with 15 logic signal connecting lines. The waveform generation circuit does not use a storage or a DAC or an analog multiplier, and is low in hardware cost of circuits. The nine-component mixed signal generator permits the input of four external signals in order to increase the total number of the components. When multiple groups of analog circuits are controlled by the single high-capacity FPGA and work, the nine-component mixed signal generator can be upgraded to be a multi-path nine-component mixed signal generator, and signals among channels can be synchronized.
Description
(1) technical field
The present invention relates to nine component mixed signal generators, mixed signal comprises 1 DC component, 1 pulse component, 7 sinusoidal components, the low-cost mixed signal generator that particularly a kind of waveform is complicated, many components independently superpose.
(2) background technology
It can produce complicated waveform having a wide range of applications aspect Electronic Testing and excitation simulation to Arbitrary Waveform Generator, has become a kind of base electronic measuring instrument.The wave generator circuit of AWG (Arbitrary Waveform Generator) comprises three parts: for the external interface circuit (as USN, LAN etc.) of Wave data transmission, Digital Logical Circuits and analog circuit.Digital Logical Circuits forms DDS circuit by unit such as control logic, wave memorizer, phase accumulators, with higher rate to artificial circuit part output waveform data; Artificial circuit part is arranged the unit such as DAC, low pass filter, multiplier and forms by waveform transformation DAC, amplitude, DAC receives with phase same rate the Wave data that digital circuit is partly exported.
The skill upgrading of AWG (Arbitrary Waveform Generator) mainly contains three: one, the raising of waveform transformation DAC switching rate and relevant High-speed Board Design, the 2nd, the expansion of waveform memory capacity, the 3rd, random waveform generation method and Wave data transmission.The source of random waveform data mainly contains two: one, the signals of reality time series directly gathering, the 2nd, the time series after complicated function of time constant duration sampling.
Natural signal is complicated, often the mixing of the independent signal in a plurality of sources; According to Fourier transform principle, the periodic signal of single complexity can be launched into multistage multifrequency sinusoid sum.During natural sign electricity consumption signal imitation, toward contact therefore with DC component and pulsation, with the mixing of DC component, a plurality of pulse component and sinusoidal component natural sign that is virtually reality like reality well.Yet during the complicated wave form that AWG (Arbitrary Waveform Generator) is mixed to form at a plurality of components of simulation, incapability is on simple operation degree and waveform really degree, all has significant deficiency.
When one or more parameters of mixed signal need to change, will make random waveform data all change.First computer will recalculate and generate new Wave data, then by external interface, new Wave data is sent to Arbitrary Waveform Generator, and Arbitrary Waveform Generator is transformed to complicated wave form by new Wave data again.Every change primary parameter, just need to repeat said process once, complex operation, and need to be by area of computer aided, parameter change required time is long; If there is no area of computer aided, mixed signal parameter change almost cannot be realized.
The mixed signal that several isolated components form can be considered a random signal in time.But due to the wave memorizer finite capacity of Arbitrary Waveform Generator, its output random waveform remains one-period signal in time, and the complicated function of time quantizes the meeting of formation generation truncated error.After the long-time output signal of Arbitrary Waveform Generator, because of the periodicity of its waveform and the accumulative total of truncated error, compare with the mixed signal ideal value of isolated component stack, can produce distortion, the time is longer, and distortion is larger.
With many function/Arbitrary Waveform Generator output signal stacks, can simulate required many components mixed signal.Increasing of instrument can bring inconvenience; Base homology not during every instrument, increases in time and also can cause superposed signal wave distortion to strengthen.
(3) summary of the invention
The object of the present invention is to provide the digital circuit part that a kind of waveform occurs need not use memory, only need to use monolithic FPGA; Artificial circuit part need not be used integrated DAC and analog multiplier, only needs to use common operation amplifier, analog multichannel switch, and resistance, electric capacity, inductance element, the nine component mixed signal generators that hardware cost is low.
The object of the present invention is achieved like this: it comprises programmable logic device and analog circuit unit, in programmable logic device, be provided with Microprocessor Interface unit, clock generating circuit unit, amplitude control logic unit, pulse control logic unit and 7 phase frequency control logic unit, Microprocessor Interface unit connects clock generating circuit unit, Microprocessor Interface unit, clock generating circuit unit connects respectively amplitude control logic unit, pulse control logic unit and 7 phase frequency control logic unit, clock generating circuit unit, amplitude control logic unit, pulse control logic unit and 7 phase frequency control logic unit difference connecting analog circuit units.
The present invention also has some technical characterictics like this:
1, described clock generating circuit unit comprises digital phase-locked loop frequency multiplication unit, even frequency division unit sum counter frequency unit, external crystal-controlled oscillation connects digital phase-locked loop frequency multiplication unit, digital phase-locked loop frequency multiplication unit connects respectively even frequency division unit sum counter frequency unit, even frequency division unit sum counter frequency unit connects respectively amplitude control logic unit, pulse control logic unit and 7 phase frequency control logic unit, even frequency division unit connecting analog circuit unit;
2, described amplitude control logic unit comprises that nine component amplitude parameter setting circuits, 4 select 1 bus data switch and data comparator, Microprocessor Interface unit connects range parameter circuit is set, range parameter arranges circuit connection 4 and selects 1 bus data switch, 4 select 1 bus data switch connection data comparator, counter frequency unit connects respectively 4 and selects 1 bus data switch and data comparator, data comparator connecting analog circuit unit;
3, described pulse control logic circuit comprises pulse parameter latch, pulse logical number controlled oscillator, pulse logic phase place adder and data comparator, digital phase-locked loop frequency multiplication unit connects pulse logical number controlled oscillator, pulse logical number controlled oscillator connects pulse logic phase place adder, pulse logic phase place adder connection data comparator, data comparator connecting analog circuit unit;
4, described phase frequency control logic unit comprises phase frequency parameter latch, phase frequency logical number controlled oscillator and phase frequency logic phase place adder, digital phase-locked loop frequency multiplication unit connects phase frequency logical number controlled oscillator, phase frequency logical number controlled oscillator connects phase frequency logic phase place adder, phase frequency logic phase place adder connecting analog circuit unit;
5, described analog circuit unit comprises component amplitude converter unit, impulse wave converter unit, sinusoidal component mixed cell and the full component superpositing unit connecting successively, component amplitude converter unit comprises first alternative analog switch, first active low-pass filter, second alternative analog switch, second active low-pass filter, the 3rd alternative analog switch, the 3rd active low-pass filter, two four select an analog switch and sampling holder, the data comparator of amplitude control logic unit connects respectively first alternative analog switch, second alternative analog switch and the 3rd alternative analog switch, first alternative analog switch, second alternative analog switch and the 3rd alternative analog switch are connected respectively first active low-pass filter, second active low-pass filter and the 3rd active low-pass filter, first active low-pass filter connects full component superpositing unit, second active low-pass filter is connected two four and selects an analog switch with the 3rd active low-pass filter, two four select an analog switch to connect sampling holder, impulse wave converter unit comprises impulse wave conversion differential amplifier and impulse wave conversion alternative analog switch, sampling holder connects impulse wave conversion alternative analog switch, impulse wave conversion alternative analog switch connects impulse wave conversion differential amplifier, and pulse control logic unit is connected respectively impulse wave conversion alternative analog switch with 7 phase frequency control logic unit, sinusoidal component mixes and comprises that the passive low pass filtered of first order adder, the first order connecting successively involves in-phase amplifier, sinusoidal component alternative analog switch, sinusoidal component differential amplifier and second level passive low ventilating filter and in-phase amplifier, impulse wave conversion differential amplifier connects first order adder and full component superpositing unit, and the passive low pass filtered in the second level involves in-phase amplifier and connects full component superpositing unit.
Another object of the present invention is to overcome the deficiencies in the prior art, a kind of nine component mixed signal method for generation are provided, mixed signal consists of 1 DC component, 1 pulse component, 7 sinusoidal components, the amplitude of each component, frequency, pulsewidth, initial phase all can independently arrange, signal generating circuit consists of analog circuit and monolithic FPGA, in analog circuit, need not use integrated DAC and analog multiplier, FPGA need not be used memory resource.Analog circuit can be divided into amplitude conversion, impulse wave conversion, sinusoidal component mixing, full component stack four processes.FPGA is built-in Microprocessor Interface unit, clock generating circuit, amplitude control logic unit, pulse control logic unit, 7 phase frequency control logic unit.The model of FPGA can be determined according to the parameter index of each component.Phase frequency control logic and pulse control logic all need to use the digital controlled oscillator with phase place preparatory function, and its operation principle has detailed discussion in DDS Waveform Synthesis Technology, thereby directly use.
The present invention's nine component mixed signal method for generation comprise the following steps:
(1) interface unit will be converted into the inner parallel bus BUS of conversion from microprocessor universal serial bus, so that all component parameters to be set; Interface unit is also introduced the global reset signal SRST from microprocessor.
(2) clock generation unit produces three kinds of clock signals: first is high frequency clock signal Fsys, and it is that external crystal-controlled oscillation clock produces after digital phase-locked loop frequency multiplication, as the system clock of all phase frequency control logic unit and pulse control logic unit; Second is the fundamental frequency square-wave signal FBAS being obtained after even frequency division by Fsys, the difference frequency clock while converting as sinusoidal component mixing; The 3rd is Fsys clock array Fout[27..0 out after counter frequency division], as the control signal of amplitude control logic unit.
(3) 1 frequency of amplitude control logic unit output fix, logical signal that can preset pulsewidth, characterize the amplitude PWMA of DC component; Export the amplitude that 2 frequencies are fixed, 4 pulsewidths of constant duration change successively logical signal PWMB and PWMC(characterize 1 pulse component and 7 sinusoidal components); Export 2 channel selecting signal CH[1..0] and 1 maintenance permission signal OUTE.Fout[27..26] as the selection signal controlling CH[1..0 of 4 passages], Fout[25] for sampling allows signal OUTE, Fout low level is determined the frequency of amplitude logical signal.
Internal bus BUS arranges 9 range parameters.Fout low level and the comparison of DC component range parameter, the output of data comparator (being less than or equal to defeated logical relation) PWMA characterization DC component; Channel selecting signal CH[1..0] control 24 and select 1 bus data switch, by 2 groups, characterize each 4 amplitude data and become respectively 2 variable data streams, Fout low level respectively with 2 variable datas stream relatively, the output of 2 data comparators (being less than or equal to defeated logical relation) PWMB and PWMC signal frequency is fixed, pulsewidth successively constant duration change.
(4) pulse control logic circuit is comprised of digital controlled oscillator, phase place adder, data comparator etc.Digital controlled oscillator work clock is Fsys, and by SRST signal synchronous reset, parameters is frequency word, phase place word, pulsewidth word; High position output and the phase place word of digital controlled oscillator are added; High position output and the comparison of pulsewidth word of adder, the output that is less than or equal to of data comparator is required pulse logical signal SW
0; Frequency word, phase place word, pulsewidth word are arranged by microprocessor.
(5) 7 phase frequency control logic element circuit structures are identical, produce 7 phase frequency logical signal SW
1 ~ 7.Phase frequency control logic circuit consists of digital controlled oscillator, phase place adder etc.; Digital controlled oscillator work clock is Fsys, and by SRST signal synchronous reset, parameters is frequency word; High position output and the phase place word of digital controlled oscillator are added, and the output of adder highest order is phase frequency logical signal; Frequency word and phase place word are arranged by microprocessor.
(6) in analog circuit, two inputs that logical signal PWMA controls first alternative analog switch connect respectively positive and negative benchmark, and switch common port signal connects first active low-pass filter, and filter output VDC has characterized the DC component of mixed signal; Two inputs that logical signal PWMB controls second alternative analog switch connect respectively positive benchmark and ground, and switch common port signal connects second active low-pass filter, and this filter output has characterized 4 components of mixed signal; Good the input that logical signal PWMC controls the 3rd alternative analog switch connects respectively positive benchmark and ground, and switch common port signal connects the 3rd active low-pass filter, and this filter output has also characterized another 4 components of mixed signal.At channel selecting signal CH[1..0] and under conducting enable signal OUTE controls, two 4 select 2 common ports of 1 analog switch to connect respectively second and the 3rd active low-pass filter output, 8 outputs of analog switch connect respectively sampling holder (being comprised of resistance, electric capacity and voltage follower), produce 8 direct current signal V
0 ~ 7.This partial simulation circuit can be considered as component amplitude transform part.
The common port of 8 alternative analog switches meets respectively 8 direct current signal V
0 ~ 7, two outputs of each analog switch are respectively as being two inputs of each differential amplifier, the output signal of differential amplifier is respectively AS
0 ~ 7, the driving signal of 8 analog switches is respectively SW
0 ~ 7.AS
0characterize the pulse component of mixed signal, AS
1 ~ 7characterize 7 sinusoidal components of mixed signal.This partial circuit can be considered as impulse wave transform part.
In analog circuit of the present invention, AS
1 ~ 7through first order adder equal weight, be added, adder power resistance adopts an exclusion that 8 resistance are integrated, to guarantee equal weight.Signal after stack send the common port of alternative analog switch through the filtering of first order passive low ventilating filter, homophase after amplifying, fundamental frequency square-wave signal FBAS controls this alternative analog switch, two outputs of this analog switch are respectively as two inputs of differential amplifier, the output of differential amplifier is SINS through the passive low-pass filtering in the second level, homophase after amplifying, and SINS has mixed all sinusoidal components.This partial circuit can be considered as sinusoidal component and mix link.
In analog circuit of the present invention, second level adder has 7 inputs: 1 is the mixed signal SINS of sinusoidal component, 1 is pulse component AS0, and 1 is DC component VDC, other 4 inputs as external signal input to realize more multicomponent stack; This adder respectively input equal weight, adder power resistance adopts an exclusion that 8 resistance are integrated, to realize equal weight, the output of adder is the nine component mixed signal SMIX that the present invention will occur.This partial simulation circuit can be considered full component stack link.
In analog circuit of the present invention, for producing the mixed signal of 7 sinusoidal components, 2 grades of passive low ventilating filter filtering have been adopted.Known according to signal filtering theory: the signal after first order filter filtering can be considered as 7 sinusoidal component stacks; The phase frequency signal of the frequency of each sinusoidal component and its phase frequency control logic unit output is with frequently, and amplitude proportional changes, phase shift with by himself frequency and first order filter parameter, determined; The high order harmonic component decay of each sinusoidal component is very large, can be considered as noise.Signal after the filter filtering of the second level can be considered as superposeing after 7 sinusoidal component frequency conversion; The frequency of each sinusoidal component is the poor of the phase frequency logical signal of its phase frequency control logic unit output and the frequency of fundamental frequency square wave FBAS, and each component amplitude ratio changes, each component phase shift and being determined by himself frequency and two-stage passive low ventilating filter parameter.
When the analog circuit of generation nine component mixed signals of the present invention is considered as to a mixed signal analog converting unit, can make the concurrent working under monolithic FPGA and microprocessor support of a plurality of mixed signal analog convertings unit, become multichannel nine component mixed signal generators.Each passage important synchronous and adopt identical system clock by SRST, can realize multichannel mixed signal synchronous.Now, the sinusoidal component of passage can continue stack by external input terminals, can reach at most 35 sinusoidal components.
By finding Analog Circuits Analysis, the amplitude gain of DC component, pulse component, sinusoidal component is different, and the amplitude-frequency characteristic of each sinusoidal component is consistent with phase-frequency characteristic.Therefore need the parameter of calibration to comprise: DC component gain, pulse component gain, sinusoidal component gain, the amplitude-frequency characteristic of sinusoidal component are, the phase-frequency characteristic of sinusoidal component.Calibration process is as follows:
The amplitude gain calibration process of DC component is as follows: by microprocessor, arrange that important amplitude is zero, each sinusoidal component frequency is the upper limit, pulse component frequency is 0; Change DC component amplitude code value, by digital multimeter, survey the DC voltage value of mixed signal output, through converting, can determine the gain coefficient of DC component.
The amplitude gain calibration process of sinusoidal component is as follows: by the important amplitude of microprocessor be zero, each sinusoidal component frequency is the upper limit, pulse component frequency is 0; Change the amplitude code value of the 7th passage, SW
7frequency be that fundamental frequency square wave FBAS frequency adds 1kHz; By digital multimeter, survey the ac voltage of mixed signal output, through converting, can determine the gain coefficient of alternating current component.
The amplitude-frequency characteristic calibration process of sinusoidal component is as follows: by the important amplitude of microprocessor be zero, sinusoidal component frequency is the upper limit, pulse component frequency is that the amplitude of 0, the 7 passage is full scale; Changing SW
7frequency values, SW
7frequency on fundamental frequency square wave FBAS frequency basis, with specific step value (as 1kHz), increase progressively, with the ac voltage when different frequency of oscilloscope measurement mixed signal output, through converting, can determine the amplitude-frequency characteristic of sinusoidal signal.
The phase-frequency characteristic calibration process of sinusoidal component is as follows: by the important amplitude of microprocessor, be zero, SW
1 ~ 5frequency be the upper limit, pulse component frequency is that the amplitude of 0, the 7 passage is full scale, SW
1 ~ 7initial phase be 0.SW
7frequency be with specific step value (as 1kHz), to increase progressively on fundamental frequency square wave FBAS frequency basis, SW
6frequency be SW
7frequency deduct the frequency of fundamental frequency square wave FBAS, every SW that arranges a time
7frequency, once, the phase difference (both are with frequently) under different frequency condition with the output of oscilloscope measurement mixed signal and SW6, determines the phase-frequency characteristic of sinusoidal component with this to SRST synchronously.
Advantage of the present invention is also: the digital circuit part that waveform occurs need not be used memory, only needs to use monolithic FPGA; Artificial circuit part need not be used integrated DAC and analog multiplier, only needs to use common operation amplifier, analog multichannel switch, and resistance, electric capacity, inductance element, therefore nine component mixed signal generator hardware costs of the present invention are low.
(4) accompanying drawing explanation
Fig. 1 is for implementing nine component mixed signal generator the general frame of the present invention.
Fig. 2 is the built-in amplitude control logic unit theory diagram of monolithic FPGA in Fig. 1.
Fig. 3 is the built-in pulse control logic unit theory diagram of monolithic FPGA in Fig. 1.
Fig. 4 is the built-in phase frequency control logic unit theory diagram of monolithic FPGA in Fig. 1.
Fig. 5 is amplitude conversion and the impulse wave transform part theory diagram in Fig. 1 analog circuit.
Fig. 6 is that the sinusoidal component in Fig. 1 analog circuit mixes and full component stack link theory diagram.
Fig. 7 is two-way nine component mixed signal generator the general frame.
(5) embodiment
Below in conjunction with accompanying drawing, introduce two kinds of preferred embodiments of the present invention.
Embodiment mono-:
In conjunction with Fig. 1, be the first preferred embodiments of the present invention, mixed signal is formed by stacking by 1 DC component, 1 pulse component, 7 sinusoidal components, totally 9 components, its wave generator circuit is comprised of monolithic EP2C5T144 and analog circuit.In FPGA, microprocessor is arranged all component parameters and global synchronizing signal SRST is provided by interface circuit.Crystal oscillator clock is exported radio frequency system clock Fsys after digital phase-locked loop frequency multiplication, and Fsys is generally 280MHz, controls control logic unit same system clock is provided for pulse control logic unit and phase frequency; Fsys produces the fundamental frequency square-wave signal FBAS of 140kHz after even frequency division, as sinusoidal component in analog circuit, mixes required difference frequency signal; Fsys clock array Fout[27..0 out after 28Bit binary counter frequency division], as the control signal of amplitude control logic unit.
Fig. 2 is the amplitude control logic cellular construction schematic diagram in Fig. 1, and its circuit working principle is as follows: clock array Fout[15..0] and the comparison of 16Bit direct current amplitude word, the data comparator of 16Bit is less than or equal to output and is PWMA, for characterizing direct current amplitude.Clock array Fout[27..26] to control 2 data widths be 16Bit 4 selects 1 data switch, 8 16Bit data that characterize a pulse component amplitude and 7 sinusoidal component amplitudes become to the variable data stream of 2 16Bit; Clock array Fout[15..0] compare with the variable data stream of 2 16Bit respectively, the data comparator of 2 16it is less than or equal to output and is PWMB, PWMC, and the frequency of PWMB and PWMC is fixed, pulsewidth constant duration changes successively; Fout[27..26] export as channel selecting signal CH[1..0], Fout[25] output conduct sampling permission OUTE signal.
Fig. 3 is the pulse control logic cellular construction schematic diagram in Fig. 1, and its circuit working principle is as follows: parameter setting circuit arranges the phase place word of 40Bit frequency word, 12Bit and the pulsewidth word of 10Bit; The frequency word of 40Bit is inputted as digital controlled oscillator, and its work clock is Fsys, by SRST signal synchronous reset; The high 12Bit output of digital controlled oscillator is added with 12Bit phase place word; The high 10Bit of adder and the Pulse width comparision of 10Bit, the output that is less than or equal to of comparator is pulse logical signal SW
0; SW
0normal working frequency scope is that 0 ~ 100kHz, frequency resolution are better than that 1mHz, initial phase resolution are better than 0.1 degree, pulse width resolution is better than 0.1%.
Fig. 4 is the single phase frequency control logic element circuit structural representation in Fig. 1, has 7 phase frequency control logic unit in FPGA.Phase frequency control logic element circuit operation principle is as follows: parameter setting circuit arranges the phase place word of 40Bit frequency word, 12Bit; The frequency word of 40Bit is inputted as digital controlled oscillator, and its work clock is Fsys, by SRST signal synchronous reset; The high 12Bit output of digital controlled oscillator is added with 12Bit phase place word; The output of adder highest order is phase frequency logical signal.The output SW of 7 phase frequency control logic unit
1 ~ 7operating frequency range is that 140kHz ~ 240kHz, frequency resolution are better than 1mHz, initial phase resolution is better than 0.1 degree.
Fig. 5 is amplitude conversion and the impulse wave transform part theory diagram in Fig. 1 analog circuit, and Fig. 6 is that the sinusoidal component in Fig. 1 analog circuit mixes and full component stack link theory diagram, and the operation principle summary of the invention part of four processes circuit is discussed in detail.The first order 9 passive elliptic filter band connection frequencies in rank are 150kHz, and the second level 9 passive elliptic filter band connection frequencies in rank are 110kHz.Artificial circuit part is used chip to have 4 Pian San road alternative analog switches (as 74HC4053), select 1 analog switch (as 74HC4052), 5 four high guaily units (as AD8513), 2 exclusions (8 resistance integration packagings) for 1 two 4.
In the execution mode of the mixed signal generator of above-mentioned nine components, need to be to DC component, pulse component, sinusoidal component gain calibration, calibration steps is discussed in detail in invention part.
Embodiment bis-:
In conjunction with Fig. 7, for the second preferred embodiments of the present invention, can produce two-way mixed signal.Compare with Fig. 2, in the monolithic FPGA of this figure, the quantity of amplitude control logic unit, pulse control logic unit, phase frequency control logic unit is all multiplied, and the logical resource therefore using is almost double, and EP2C5T144 still can realize.Each analog circuit in this figure is identical with the analog circuit in Fig. 2.Because each component of two-way mixed signal all adopts same clock Fsys and same global synchronization SRST, two-way mixed signal can realize synchronously.Described in its calibration steps and single channel mixed signal generator, calibration steps is basically identical.
Above-described is only specific embodiments of the invention, and the protection range being not intended to limit the present invention, is equal to replacement, improvement etc., within all should being included in protection scope of the present invention at all any modifications within the present invention spirit and principle.
Claims (7)
1. a component mixed signal generator, it is characterized in that: it is to consist of analog circuit and monolithic programmable logic device, programmable logic device is embedded with interface unit, clock generation unit, amplitude logic generating unit, pulse logic generating unit, phase frequency logic generating unit; Interface circuit connects microprocessor, clock generation unit connects outside input clock, interface circuit connects respectively amplitude logic generating unit, pulse logic generating unit and phase frequency logic generating unit, and clock generation unit connects respectively amplitude logic generating unit, pulse logic generating unit, phase frequency logic generating unit and analog circuit; Amplitude logic generating unit comprises that range parameter arranges latch, 4 and selects 1 bus data switch, pulse logic generating unit comprises that pulse parameter arranges latch, pulse logic generation digital controlled oscillator, pulse logic generation phase place adder and data comparator, clock generation unit connects pulse logic generation digital controlled oscillator, pulse logic generation digital controlled oscillator connects pulse logic generation phase place adder, pulse logic generation phase place adder connection data comparator, data comparator connecting analog circuit; Phase frequency logic generating unit comprises phase frequency parameter latch, phase frequency logic generation digital controlled oscillator and phase frequency logic generation phase place adder, clock generation unit connects phase frequency logic generation digital controlled oscillator, phase frequency logic generation digital controlled oscillator connects phase frequency logic generation phase place adder, phase frequency logic generation phase place adder connecting analog circuit.
2. a kind of nine component mixed signal generators according to claim 1, it is characterized in that: described clock generation unit comprises frequency multiplication of phase locked loop unit and even frequency division unit, outside input clock connects frequency multiplication of phase locked loop unit, frequency multiplication of phase locked loop unit connects respectively even frequency division unit, amplitude logic generating unit, pulse logic generating unit and phase frequency logic generating unit, even frequency division unit connecting analog circuit.
3. a kind of nine component mixed signal generators according to claim 1, is characterized in that: described analog circuit comprises amplitude converter unit, impulse wave converter unit, sinusoidal component mixed cell, full component superpositing unit four parts; Amplitude converter unit connects impulse wave converter unit, impulse wave converter unit is connected sinusoidal component mixed cell with even frequency division unit, sinusoidal component mixed cell, amplitude converter unit, impulse wave converter unit and outside input are connected full component superpositing unit, and full component superpositing unit output is final output.
4. a kind of nine component mixed signal generators according to claim 3, it is characterized in that: described amplitude converter unit comprises first order alternative analog switch, first order active low-pass filter, second level alternative analog switch, second level active low-pass filter, third level alternative analog switch, third level active low-pass filter, two four select an analog switch and sampling holder, the data comparator of amplitude logic generating unit connects respectively first order alternative analog switch, second level alternative analog switch and third level alternative analog switch, first order alternative analog switch, second level alternative analog switch and third level alternative analog switch are connected respectively first order active low-pass filter, second level active low-pass filter and third level active low-pass filter, first order active low-pass filter connects full component superpositing unit, second level active low-pass filter is connected two four and selects an analog switch with third level active low-pass filter, two four select an analog switch to connect sampling holder.
5. a kind of nine component mixed signal generators according to claim 3, it is characterized in that: described impulse wave converter unit comprises impulse wave conversion differential amplifier and impulse wave conversion alternative analog switch, sampling holder connects impulse wave conversion alternative analog switch, impulse wave conversion alternative analog switch connects impulse wave conversion differential amplifier, and pulse logic generating unit is connected respectively impulse wave conversion alternative analog switch with 7 phase frequency logic generating units.
6. a kind of nine component mixed signal generators according to claim 3, it is characterized in that: described sinusoidal component mixed cell comprises the first order adder connecting successively, the passive low pass filtered of the first order involves in-phase amplifier, sinusoidal component alternative analog switch, sinusoidal component differential amplifier, second level passive low ventilating filter and in-phase amplifier, impulse wave conversion differential amplifier connects first order adder and full component superpositing unit, first order active filter, the passive low pass filtered in the second level involves in-phase amplifier, external analog input connects full component superpositing unit.
7. a kind of nine component mixed signal method for generation according to claim 1, is characterized in that: mixed signal is comprised of 1 DC component, 1 pulse component, 7 sinusoidal components, and all component parameters all independently arrange; Signal generating circuit is comprised of monolithic FPGA and analog circuit, programmable logic device is built-in interface circuit, clock generating circuit, amplitude logic generating unit, pulse logic generating unit and 7 groups of phase frequency logic generating units, and the method step comprises:
(1) interface circuit changes the universal serial bus of microprocessor into inner parallel bus, so that frequency word, the phase place word of each sinusoidal component of mixed signal to be set, the amplitude word of frequency word, phase place word, pulsewidth word and the DC component of pulse component is set, and interface circuit is also introduced reset signal SRST from microprocessor;
(2) clock generation unit produces three kinds of clock signals: first is high frequency clock signal Fsys, and it is that external crystal-controlled oscillation clock produces after digital phase-locked loop frequency multiplication, as the system clock of all phase frequency logic generating units and pulse logic generating unit; Second is the fundamental frequency square-wave signal FBAS being obtained after even frequency division by Fsys, the difference frequency clock while converting as sinusoidal component mixing; The 3rd is Fsys clock array Fout[27..0 out after counter frequency division], as the control signal of amplitude logic generating unit;
(3) 1 frequency of amplitude logic generating unit output fix, logical signal that can preset pulsewidth, characterize the amplitude PWMA of DC component; Export the amplitude that 2 frequencies are fixed, 4 pulsewidths of constant duration change successively logical signal PWMB and PWMC(characterize 1 pulse component and 7 sinusoidal components); Export 2 channel selecting signal CH[1..0] and 1 maintenance permission signal CH[2]; Fout[27..26] as the selection signal controlling CH[1..0 of 4 passages], Fout[25] allow signal CH[2 for sampling], Fout low level is determined the frequency of amplitude logical signal;
(4) pulse logic generating unit produces pulse control signal SW
0, in pulse logic generating unit, parameters is frequency word, phase place word, pulsewidth word, and work clock is Fsys, resets and is realized by SRST, and high position output and the phase place word of digital controlled oscillator are added; High position output and the comparison of pulsewidth word of adder, the output that is less than or equal to of data comparator is required pulse logical signal SW
0;
(5) 7 phase frequency logic generating units produce phase frequency control signal SW
1 ~ 7, 7 phase frequency logic generating unit circuit structures are identical; In each phase frequency logic generating unit, parameters with the phase frequency logic generation digital controlled oscillator of phase place preparatory function is frequency word and phase place word, work clock is Fsys, reset is realized by SRST, the highest order output of phase frequency logic generation digital controlled oscillator be phase frequency control signal, and corresponding sinusoidal component frequency is the poor of this phase frequency control signal and fundamental frequency square-wave signal FBAS frequency;
(6) analog circuit comprises amplitude converter unit, impulse transfer unit, sinusoidal component mixed cell and full component superpositing unit, controlled by FPGA; Amplitude converter unit is at PWMA, PWMB, PWMC, the CH[2:0 of FPGA output] control pass through alternative analog switch down, active low-pass filter, four selects an analog switch, sampling holder obtains characterizing the direct voltage of whole 9 component amplitude; Impulse transfer unit is at the SW of FPGA output
0 ~ 7under control, through the conversion of 8 groups of alternative analog switches and differential amplifier, obtain characterizing amplitude, the frequency of 1 pulse component and 7 sinusoidal components, the pulse signal AS of phase place respectively
0 ~ 7, sinusoidal component mixed cell after equal weight stack, low-pass filtering and homophase amplify, amplifies through either-or switch conversion, low-pass filtering, homophase the mixed signal that obtains 7 sinusoidal components by 7 pulse signals under the FBAS of FPGA output controls; Full component superpositing unit obtains full component signal SMIX by direct current signal, pulse signal, sinusoidal component mixed signal and 4 external input signal stacks;
(7) when a plurality of analog circuits are under monolithic FPGA and microprocessor are supported during concurrent working, i.e. upgrading becomes many components of multichannel mixed signal generator, and it is synchronous to realize multichannel mixed signal, the sinusoidal component of passage can continue stack by external input terminals, can reach at most 35 sinusoidal components.
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| CN108710404A (en) * | 2018-05-23 | 2018-10-26 | 中国科学技术大学 | A kind of mixed signal generator |
| CN110429923A (en) * | 2019-07-30 | 2019-11-08 | 天津讯联科技有限公司 | A kind of laser pick-off signal digitalized processing method |
| CN110838835A (en) * | 2019-11-19 | 2020-02-25 | 天津津航计算技术研究所 | Random signal generating circuit based on high-speed dynamic comparator |
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| CN110838835A (en) * | 2019-11-19 | 2020-02-25 | 天津津航计算技术研究所 | Random signal generating circuit based on high-speed dynamic comparator |
| CN110838835B (en) * | 2019-11-19 | 2023-04-28 | 天津津航计算技术研究所 | Random signal generating circuit based on high-speed dynamic comparator |
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