CN203734631U - Stacked-type LC filter - Google Patents
Stacked-type LC filter Download PDFInfo
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- CN203734631U CN203734631U CN201290000776.8U CN201290000776U CN203734631U CN 203734631 U CN203734631 U CN 203734631U CN 201290000776 U CN201290000776 U CN 201290000776U CN 203734631 U CN203734631 U CN 203734631U
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- 230000008878 coupling Effects 0.000 description 12
- 238000010168 coupling process Methods 0.000 description 12
- 238000005859 coupling reaction Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
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- 239000000463 material Substances 0.000 description 2
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- 230000015556 catabolic process Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0013—Printed inductances with stacked layers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/17—Structural details of sub-circuits of frequency selective networks
- H03H7/1708—Comprising bridging elements, i.e. elements in a series path without own reference to ground and spanning branching nodes of another series path
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/17—Structural details of sub-circuits of frequency selective networks
- H03H7/1741—Comprising typical LC combinations, irrespective of presence and location of additional resistors
- H03H7/1758—Series LC in shunt or branch path
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/17—Structural details of sub-circuits of frequency selective networks
- H03H7/1741—Comprising typical LC combinations, irrespective of presence and location of additional resistors
- H03H7/1775—Parallel LC in shunt or branch path
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0013—Printed inductances with stacked layers
- H01F2017/0026—Multilayer LC-filter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
- H03H2001/0021—Constructional details
- H03H2001/0085—Multilayer, e.g. LTCC, HTCC, green sheets
Abstract
The objective of the utility model lies in providing a stacked-type LC filter which is not liable to be affected by the stray capacitance generated between the filter and a surface electrode. The filter (1) is characterized in that the filter (1) is provided with a stacked body (10); the stacked body (10) is formed by the stacking of a plurality of dielectric layers (11), wherein the surface of each dielectric layer (11) is provided with an internal electrode pattern; the dielectric layers (11) and the internal electrode patterns form coils and capacitors; the stacked body (10) is provided with two main surfaces perpendicular to the stack direction; the filter (11) is also provided with a surface electrode (41) which is formed on one main surface of the stacked body (10), thereby enabling the relative dielectric constant of the dielectric layer (11) between the main surface of the surface electrode (41) and the internal electrode pattern closest to the main surface to be less than the relative dielectric constant of the dielectric layers forming the capacitors.
Description
Technical field
The utility model relates to a kind of cascade type LC filter, be particularly related to the cascade type LC filter being laminated by the multiple dielectric layers that are formed with internal electrode pattern on surface, this cascade type LC filter possesses the duplexer that is made up of coil and capacitor dielectric layer and internal electrode pattern.
Background technology
In the past, for example, in patent documentation 1, recorded following cascade type LC filter:, be laminated by the multiple dielectric layers that are formed with internal electrode pattern on surface, possess the duplexer that has dielectric layer and internal electrode pattern to form coil and capacitor.
As shown in figure 12, this cascade type LC filter has dielectric layer 101～105.And, be formed with grounding electrode 109 on the surface of dielectric layer 101.In addition, be formed with electrode for capacitors 111 on the surface of dielectric layer 102.In addition, be formed with line electrode 116 on the surface of dielectric layer 104.
Through hole electrode 131 is connect the mode of dielectric layer 103,104 and form.And through hole electrode 131 connects electrode for capacitors 111 and line electrode 116.In addition, through hole electrode 141 is connect the mode of dielectric layer 102～104 and form.And through hole electrode 141 connects grounding electrode 109 and line electrode 116.
Electrode for capacitors 111 and grounding electrode 109 across dielectric layer 102 relative to, thereby form capacitor.In addition, through hole electrode 131,141 and line electrode 116 form coil.This capacitor is connected with coils from parallel connection of coils, and becomes 1 LC parallel resonator.
And the cascade type LC filter disclosing in background document has 5 above-mentioned LC parallel resonators, thereby electromagnetic coupled occurs mutually, thereby play a role as the band pass filter that only signal with special frequency band is passed through.
Patent documentation 1: International Publication WO2007/119356 communique
Utility model content
But, may form surface electrode on the surface of the duplexer of the cascade type LC of Figure 12 filter.This surface electrode is for example the identification mark of the direction for identifying this cascade type LC filter, or the installing electrodes using in the installation of cascade type LC filter.Now, may between surface electrode and internal electrode pattern, produce parasitic capacitance, thereby change filter characteristic.
Given this utility model completes, and its object is to provide a kind of cascade type LC filter of the impact that is not vulnerable to the parasitic capacitance producing between internal electrode pattern and surface electrode.
Utility model technical problem to be solved
Cascade type LC filter of the present utility model is characterised in that, have: duplexer, this duplexer is laminated by the multiple dielectric layers that are formed with internal electrode pattern on surface, and form coil and capacitor by dielectric layer and internal electrode pattern, and there are 2 interareas vertical with stacked direction; And surface electrode, this surface electrode is formed at the interarea of duplexer, from the interarea that is formed with surface electrode to the relative dielectric constant that approaches most the dielectric layer the internal electrode pattern of this interarea lower than the relative dielectric constant of dielectric layer that forms capacitor.
In addition, in cascade type LC filter of the present utility model, preferred surface electrode is the identification mark for identifying, and an interarea of duplexer forms the installed surface of duplexer, and surface electrode is formed at another interarea of duplexer.
In addition,, in cascade type LC filter of the present utility model, preferably, in the time observing from stacked direction, surface electrode is to form in the overlapping mode in multiple positions with the internal electrode pattern of the most approaching interarea that is formed with surface electrode.
In addition, in cascade type LC filter of the present utility model, preferably the internal electrode pattern of the most approaching interarea that is formed with surface electrode is formed with multiple on same dielectric layer, in the time observing from stacked direction, surface electrode is with the overlapping mode of multiple internal electrode patterns and form.
In addition, in cascade type LC filter of the present utility model, one or more internal electrode patterns that are preferably the most approaching interarea that is formed with surface electrode form coil, in the time observing from stacked direction, surface electrode with internal electrode pattern in the overlapping mode of multiple parts of 1 internal electrode pattern and form.
In addition, in cascade type LC filter of the present utility model, being preferably surface electrode is the installing electrodes using in the installation of cascade type LC filter, an interarea of duplexer forms the installed surface of duplexer, surface electrode is formed on an interarea, is grounding electrode from the nearest internal electrode pattern of interarea relative with installed surface of duplexer.
According to cascade type LC filter of the present utility model, surface electrode and the relative dielectric constant that approaches the dielectric layer between the internal electrode pattern of interarea are most lower than the dielectric layer that forms capacitor.Therefore, the cascade type LC filter of the impact of the parasitic capacitance that is not vulnerable to occur between surface electrode can be provided.
Brief description of the drawings
Fig. 1 is the equivalent circuit diagram of the band pass filter of the 1st execution mode of the present utility model.
Fig. 2 is the stereogram that represents the band pass filter of the 1st execution mode of the present utility model.
Fig. 3 is the exploded perspective view that represents the band pass filter of the 1st execution mode of the present utility model.
Fig. 4 is the waveform result of the simulation of the band pass filter of the 1st execution mode of the present utility model.
Fig. 5 is the equivalent circuit diagram of the duplexer of the 2nd execution mode of the present utility model.
Fig. 6 is the stereogram that represents the duplexer of the 2nd execution mode of the present utility model.
Fig. 7 is the exploded perspective view that represents the duplexer of the 2nd execution mode of the present utility model.
Fig. 8 is the vertical view that schematically shows the surface electrode of Fig. 7 and pass, the position of coil electrode relation.
Fig. 9 is the analog waveform result of the duplexer of the 2nd execution mode of the present utility model.
Figure 10 is the vertical view that schematically shows the position relationship of coil and internal electrode.
Figure 11 is the exploded perspective view that represents the cascade type LC filter of the 3rd execution mode of the present utility model.
Figure 12 is the exploded perspective view that represents existing cascade type LC filter.
Reference numeral
1 cascade type LC filter (band pass filter, duplexer)
2,3,4,5,6,7 terminals
10 duplexers
11 dielectric layers
21,22,23 line electrodes
24,25,26 coil electrodes
27,28 coil electrodes
31,32,33 electrode for capacitors
34,35 electrode for capacitors
36,37 electrode for capacitors
41 surface electrodes
42 coupling electrodes
43 electrode for capacitors
44,45 extraction electrodes
46 grounding electrodes
47,48 grounding electrodes
51,52,53,54,55,56 terminal electrodes
61,62,63,64,65,66 through hole electrodes
67,68,69,70,71,72 through hole electrodes
101,102,103,104,105 dielectric layers
109 grounding electrodes
111 electrode for capacitors
116 line electrodes
131,141 through hole electrodes
Embodiment
(the 1st execution mode)
Fig. 1 is the equivalent circuit diagram of the cascade type LC filter of the 1st execution mode of the present utility model.Illustrate that in the present embodiment cascade type LC filter is the example of band pass filter.Terminal T1, T2 are input and output terminals.Between input and output terminal T1, T2, dispose 3 LC parallel resonator LC1, LC2, LC3.LC parallel resonator LC1 is made up of the capacitor C1 of connection parallel with one another and inductor L1.Similarly, LC parallel resonator LC2 is made up of capacitor C2 and the inductor L2 of connection parallel with one another.In addition, LC parallel resonator LC3 is made up of capacitor C3 and the inductor L3 of connection parallel with one another.In addition LC parallel resonator LC1 and LC2 mutual electromagnetic coupling, and LC parallel resonator LC2 and LC3 mutual electromagnetic coupling.
One end of LC parallel resonator LC1, LC2, LC3 respectively with grounding connection.In addition, between the other end of LC parallel resonator LC1 and the other end of LC parallel resonator LC2, be connected with capacitor C4.Similarly, between the other end of LC parallel resonator LC2 and the other end of LC parallel resonator LC3, be connected with capacitor C5.And, between input and output terminal T1 and T2, be connected with capacitor C6.This band pass filter has passes through the signal of special frequency band, and cuts off the function of the signal of frequency band in addition.
Fig. 2 is the stereogram that represents the band pass filter of present embodiment.Band pass filter 1 has duplexer 10, surface electrode 41.And duplexer 10 has 2 interareas vertical with stacked direction (direction of arrow in figure) and is connected multiple sides of 2 interareas.Terminal the 2,3,4,5,6, the 7th, forms in the mode of 2 interareas across duplexer 10 and side.In band pass filter 1 being installed to substrate etc., an interarea of duplexer 10 forms the installed surface of duplexer 10.
Surface electrode 41 is formed on the interarea of duplexer 10.In the present embodiment, surface electrode 41 is for example for identifying the identification mark of installation direction of band pass filter.In addition, surface electrode 41 is formed on the interarea contrary with the interarea of duplexer 10 of installed surface that forms duplexer 10.,, if observe from top when mounted, surface electrode 41 is visual.
In the present embodiment, terminal 5 is corresponding to the input and output terminal T1 of Fig. 1, terminal 3,6 earth terminals corresponding to Fig. 1, and terminal 7 is corresponding to the input and output terminal T2 of Fig. 1.In addition, terminal 2,4, is virtual (dummy) terminal not being conducted with the internal electrode of inside that is formed on duplexer.
Fig. 3 is the exploded perspective view that represents the band pass filter of present embodiment.Band pass filter 1 is to be laminated by the multiple dielectric layer 11a～11k that are formed with internal electrode pattern on surface.
Surface electrode 41a and terminal electrode 51a, 52a, 53a, 54a, 55a, 56a are formed on the surface of dielectric layer 11a.Line electrode 21b, 22b, 23b are formed on the surface of dielectric layer 11b.Line electrode 21c, 22c, 23c are formed on the surface of dielectric layer 11c.Line electrode 21d, 22d, 23d are formed on the surface of dielectric layer 11d.Extraction electrode 44e, 45e are formed on the surface of dielectric layer 11e.Electrode for capacitors 31f, 32f, 33f are formed on the surface of dielectric layer 11f.Coupling electrode 42g is formed on the surface of dielectric layer 11g.Electrode for capacitors 31h, 32h, 33h are formed on the surface of dielectric layer 11h.Electrode for capacitors 31i is formed on the surface of dielectric layer 11i.Electrode for capacitors 31j, 32j, 33j are formed on the surface of dielectric layer 11j.Grounding electrode 46k is formed on the surface of dielectric layer 11k.
Through hole electrode 61,63,65 connects dielectric layer 11b～11j on stacked direction.In addition, through hole electrode 62,64,66 connects dielectric layer 11b～11i on stacked direction.
Line electrode 21b, 21c, 21d one end is separately electrically connected with one end of through hole electrode 61 respectively.Line electrode 21b, 21c, the 21d other end is separately electrically connected with one end of through hole electrode 62 respectively.Line electrode 21b, 21c, 21d and through hole electrode 61,62 form inductor L1 (with reference to Fig. 1).In addition, the other end of through hole electrode 61 is electrically connected with grounding electrode 46k.The other end of through hole electrode 62 is electrically connected with electrode for capacitors 31j.Electrode for capacitors 31j and grounding electrode 46k across dielectric layer 11j relative to, form capacitor C1 (with reference to Fig. 1).Form LC parallel resonator LC1 by above-mentioned inductor L1 and capacitor C1.
One end of line electrode 22b, 22c, 22d is electrically connected with one end of through hole electrode 63.The other end of line electrode 22b, 22c, 22d is electrically connected with one end of through hole electrode 64.Line electrode 22b, 22c, 22d and through hole electrode 63,64 form inductor L2 (with reference to Fig. 1).In addition, the other end of through hole electrode 63 is electrically connected with grounding electrode 46k.The other end of through hole electrode 64 is electrically connected with electrode for capacitors 32j.Electrode for capacitors 32j and grounding electrode 46k across dielectric layer 11j relative to, form capacitor C2 (with reference to Fig. 1).Above-mentioned inductor L2 and capacitor C2 form LC parallel resonator LC2.
One end of line electrode 23b, 23c, 23d is electrically connected with one end of through hole electrode 65.The other end of line electrode 23b, 23c, 23d is electrically connected with one end of through hole electrode 66.Line electrode 23b, 23c, 23d and through hole electrode 65,66 form inductor L3 (with reference to Fig. 1).In addition, the other end of through hole electrode 65 is electrically connected with grounding electrode 46k.The other end of through hole electrode 66 is electrically connected with electrode for capacitors 33j.Electrode for capacitors 33j and grounding electrode 46k across dielectric layer 11j relative to, form capacitor C3 (with reference to Fig. 1).Above-mentioned inductor L3 and capacitor C3 form LC parallel resonator LC3.
Extraction electrode 44e is electrically connected with through hole electrode 62, and its one end is connected with input and output terminal T1 (with reference to Fig. 1).In addition, extraction electrode 45e is electrically connected with through hole electrode 66, and its one end is connected with input and output terminal T2 (with reference to Fig. 1).
Electrode for capacitors 31i is connected with through hole electrode 64.And electrode for capacitors 31h, the 31j being connected with through hole electrode 62 can be relative across dielectric layer 11h, 11i with electrode for capacitors 31i, thereby form capacitor C4 (with reference to Fig. 1).Similarly, electrode for capacitors 33h, the 33j being connected with through hole electrode 66 can be relative across dielectric layer 11h, 11i with electrode for capacitors 31i, thereby form capacitor C5 (with reference to Fig. 1).
Electrode for capacitors 31f, 31h are relative across dielectric layer 11f, 11g with coupling electrode 42g.Electrode for capacitors 32f, 32h are relative across dielectric layer 11f, 11g with coupling electrode 32g.Capacitor 33f, 33h are relative across dielectric layer 11f, 11g with coupling electrode 42g.Form thus capacitor C6 (with reference to Fig. 1).
In the present embodiment, the surperficial surface electrode 41a that is formed at dielectric layer 11a can expose from of duplexer 10 interarea, and performance makes the function of the clear and definite directivity mark of the installation direction of band pass filter.In the time observing from stacked direction, this surface electrode 41a can with approach most multiple internal electrode patterns of this interarea, be formed on surperficial line electrode 21b, the 22b overlaid of dielectric layer 11b.
Therefore, between surface electrode 41a and line electrode 21b, 22b, produce parasitic capacitance (CF of Fig. 1) across dielectric layer 11a, can produce harmful effect to the filter characteristic of band pass filter.Therefore, in the present embodiment, making the interarea from being formed with surface electrode 41a is the relative dielectric constant of the dielectric layer 11a 21b, 22b, 23b, lower than the relative dielectric constant of dielectric layer 11f, the 11g of formation capacitor, 11h, 11i, 11j to the internal electrode pattern that approaches most interarea.Therefore, can obtain the desired characteristic having of filter, and the value of the parasitic capacitance producing can be reduced to the size that can not affect filter characteristic between surface electrode 41a and line electrode 21b, 22b.In addition, in the present embodiment, make the relative dielectric constant of dielectric layer 11a lower than dielectric layer 11b～11k.As the example of the material of dielectric layer 11a, can exemplify out pottery or the resin of low relative dielectric constant.
Fig. 4 is the analog waveform result of the attenuation characteristic of the cascade type LC filter of present embodiment.Fig. 4 represents that it passes through characteristic, and Fig. 4 (A) is the characteristic that represents to comprise the frequency range in passband (passband) and upper and lower decay territory thereof, and Fig. 4 (B) represents to amplify this passband part.In Fig. 4, dotted line represent the relative dielectric constant of the outermost dielectric layer 11a (with reference to Fig. 3) of the duplexer 10 that is formed with surface electrode 41a be 50 and other the relative dielectric constant of dielectric layer be also the characteristic of passing through of band pass filter in 50 situation.In addition, solid line represents the characteristic of passing through of band pass filter in following situation:, the relative dielectric constant of outermost dielectric layer 11a is 8 and lower than the value 50 of the relative dielectric constant of other dielectric layer.
Learn from Fig. 4 (B), near the 2.4GHz of the lower frequency side in passband, the waveform of solid line is compared the waveform of dotted line, and its attenuation will low 0.1dB left and right.That is, known is lower relative dielectric constant by making dielectric layer 11a, thus the attenuation steeply inclined more of the low pass of passband (low-pass) side, thereby will show good characteristic as filter.
(the 2nd execution mode)
Fig. 5 is the equivalent circuit diagram of the duplexer of the 2nd execution mode of the present utility model.P1, P2, P3 are input and output terminals.Between terminals P 2 and terminals P 3, be connected with inductor LL1.In addition,, between terminals P 2 and ground connection, capacitor CL1 and inductor LL2 are connected in series.The low pass filter (low-pass filter) of inductor LL1, LL2 and capacitor CL1 formation duplexer partly.
Similarly, between terminals P 3 and terminals P 1, capacitor CH11, CH12 are connected in series.In addition,, between capacitor CH11 and the tie point and ground connection of capacitor CH12, capacitor CH2 and inductor LH are connected in series.The high pass filter (high-pass filter) of inductor LH and capacitor CH11, CH12, CH2 formation duplexer partly.
Fig. 6 is the stereogram that represents the duplexer of present embodiment.Terminal 5 is corresponding to the P2 of Fig. 5, and terminal 7 is corresponding to the P1 of Fig. 5, and terminal 3 is corresponding to the P3 of Fig. 5, and terminal 2,4 is corresponding to ground connection.In addition, terminal 6 is virtual terminals.
Fig. 7 is the exploded perspective view that represents the duplexer of present embodiment.Duplexer is to be laminated by the multiple dielectric layer 11a～11o that are formed with internal electrode pattern on surface.
Surface electrode 41a and terminal electrode 51a, 52a, 53a, 54a, 55a, 56a are formed on the surface of dielectric layer 11a.Coil electrode 24b, 25b are formed on the surface of dielectric layer 11b.Coil electrode 24c, 25c are formed on the surface of dielectric layer 11c.Coil electrode 24d, 25d are formed on the surface of dielectric layer 11d.Coil electrode 24e is formed on the surface of dielectric layer 11e.Electrode for capacitors 34f, 35f are formed on the surface of dielectric layer 11f.Electrode for capacitors 34g, 35g are formed on the surface of dielectric layer 11g.Electrode for capacitors 34h, 35h are formed on the surface of dielectric layer 11h.Electrode for capacitors 35i is formed on the surface of dielectric layer 11i.Electrode for capacitors 35j is formed on the surface of dielectric layer 11j.Electrode for capacitors 35k is formed on the surface of dielectric layer 11k.Coil electrode 26l is formed on the surface of dielectric layer 11l.Coil electrode 26m is formed on the surface of dielectric layer 11m.Coil electrode 26n is formed on the surface of dielectric layer 11n.Grounding electrode 46o is formed on the surface of dielectric layer 11o.
Through hole electrode 67 connects dielectric layer 11b～11d on stacked direction.Through hole electrode 68 connects dielectric layer 11b, 11c on stacked direction.Through hole electrode 69 connects dielectric layer 11l, 11m on stacked direction.Through hole electrode 70 connects dielectric layer 11g～11k on stacked direction.Through hole electrode 71 connects dielectric layer 11g～11j on stacked direction.Through hole electrode 72 connects dielectric layer 11d～11g on stacked direction.
Will be described below the corresponding relation of Fig. 5～Fig. 7.One end of coil electrode 24b is connected with terminal 3 (with reference to the P3 of Fig. 6, Fig. 5).In addition, coil electrode 24b, 24c, 24d, 24e interconnect by through hole electrode 67.Coil electrode 24b, 24c, 24d, 24e and through hole electrode 67 form coil LL1.One end of coil electrode 24e is connected with terminal 5 (with reference to the P2 of Fig. 6, Fig. 5).
One end of electrode for capacitors 34f, 34h is connected with terminal 5 (with reference to the P2 of Fig. 6, Fig. 5).Electrode for capacitors 34f, 34h are relative across dielectric layer 11f, 11g with electrode for capacitors 34g, thereby form capacitor CL1.One end of electrode for capacitors 34g is connected by through hole electrode 70 with coil electrode 26l.
Coil electrode 26l, 26m, 26n interconnect by through hole electrode 69.Coil electrode 26l, 26m, 26n and through hole electrode 69 form coil LL2.One end of coil electrode 26n is connected with terminal 2 (with reference to the ground connection of Fig. 6, Fig. 5).
One end of coil electrode 25b is connected with terminal 6 (with reference to the ground connection of Fig. 6, Fig. 5).In addition, coil electrode 25b, 25c, 25d are connected by through hole electrode 68.Coil electrode 25b, 25c, 25d and through hole electrode 68 form coil LH.Coil electrode 25d is connected by through hole electrode 72 with electrode for capacitors 35h.
Electrode for capacitors 35h and electrode for capacitors 35g, 35i, across dielectric layer 11g, 11h relatively to, form capacitor CH2.Electrode for capacitors 35g, 35i, 35k, connect by through hole electrode 71.
Electrode for capacitors 35i, 35k are relative across dielectric layer 11i, 11j with electrode for capacitors 35j, thereby form capacitor CH12.One end of electrode for capacitors 35j is connected with terminal 7 (with reference to the P1 of Fig. 6, Fig. 5).
Electrode for capacitors 35f is relative across dielectric layer 11f with electrode for capacitors 35g, thereby forms capacitor CH11.One end of electrode for capacitors 35f is connected with terminal 3 (with reference to the P3 of Fig. 6, Fig. 5).
In the present embodiment, the internal electrode pattern of the most approaching interarea that is formed with surface electrode 41a is that coil electrode 24b, 25b form respectively coil.
Fig. 8 is the vertical view that schematically shows the surface electrode 41a of Fig. 7 and pass, the position of coil electrode 24b relation.In the time observing from stacked direction, surface electrode 41a is with the overlapping mode of multiple parts of coil electrode 24b and form.In the present embodiment, coil electrode 24b is spiral (helical) shape, and surface electrode 41a forms with 2 positions shown in the oblique line part at Fig. 8 and the overlapping mode of coil electrode 24b.In this case, between surface electrode 41a and coil electrode 24b, produce parasitic capacitance across dielectric layer 11a, thereby the characteristic of cascade type LC filter reduces.Therefore, make the relative dielectric constant of dielectric layer 11a lower than dielectric layer 11f, the 11g, 11h, 11i, 11j, the 11k that form capacitor, thereby can reduce by suppression characteristic.
Fig. 9 is the analog waveform that passes through characteristic that forms the high pass filter of the duplexer of present embodiment.Fig. 9 (A) is that this is wide band by characteristic, and Fig. 9 (B) is near enlarged drawing cut-off frequency.Dotted line be the relative dielectric constant of outermost dielectric layer 11a (with reference to Fig. 7) be 50 and other the relative dielectric constant of dielectric layer be also the characteristic of passing through of duplexer in 50 situation.In addition, solid line is the characteristic of passing through that represents duplexer in following situation:, the relative dielectric constant of outermost dielectric layer 11a is 8 and lower than other the relative dielectric constant 50 of dielectric layer.
For the parasitic capacitance producing between coil electrode 24b and surface electrode 41a, in high pass filter part, be to cause as being connected in the capacitor between terminals P 1,3 of terminals P and earth terminal.Thus, the frequency that is positioned at the attenuation pole of the high-frequency side of high pass filter reduces, and therefore in the waveform of dotted line, attenuation characteristic reduces.
On the other hand, the solid line waveform at the relative dielectric constant of outermost dielectric layer 11a lower than the relative dielectric constant of other dielectric layer, can suppress the reduction of the frequency of the attenuation pole that the generation of parasitic capacitance causes.Therefore,, in the scope of wider frequency band, maintained good attenuation characteristic.
In addition, in present embodiment, illustrated be positioned at surface electrode under coil be the example of helical coil, but other coil also can be brought into play effect of the present utility model.Figure 10 is the vertical view that schematically shows pass, the position relation of coil and internal electrode, is the execution mode that has changed coil kind.Figure 10 (A) is the example of spiral (spiral) coil, and Figure 10 (B) is the example of inflection (meander) coil.While observation from stacked direction, have coil electrode 24 in the bottom of surface electrode 41, because the potential difference between coil electrode 24 and surface electrode 41 causes producing parasitic capacitance between coil electrode 24 and surface electrode 41.This parasitic capacitance is the main cause of the characteristic degradation in the high-frequency region of duplexer.Therefore, by make interarea from being formed with surface electrode 41 to the internal electrode pattern that approaches most interarea be coil electrode 24 to the relative dielectric constant of dielectric layer 11 reduce, thereby can suppress the impact of parasitic capacitance.
In addition, present embodiment, illustrated about the mode of the coil electrode of 1 coil with across in duplexer and be formed with surface electrode, but surface electrode also can across between the coil electrode of multiple coils, capacitor electrode interpolar or the mode of coil electrode and capacitor electrode interpolar and form.In addition, be not only applicable to duplexer (diplexer), be applicable to single fiber three-phase device (triplexer) yet.
(the 3rd execution mode)
Figure 11 is the exploded perspective view that represents the cascade type LC filter of the 3rd execution mode of the present utility model.The cascade type LC filter of present embodiment is to form by being laminated with the duplexer of dielectric layer 11a～11l.Be formed with surface electrode 41a, the 41b of the problem that becomes the parasitic capacitance between the grounding electrode of duplexer inside and other terminal electrode 51a, 52a, 53a, 54a, 55a, 56a on the surface of dielectric layer 11a.Be formed with grounding electrode 46b on the surface of dielectric layer 11b.Be formed with coil electrode 27d, 28d on the surface of dielectric layer 11d.Be formed with coil electrode 27e, 28e on the surface of dielectric layer 11e.Be formed with grounding electrode 47g, 48g on the surface of dielectric layer 11g.Be formed with electrode for capacitors 36h, 37h on the surface of dielectric layer 11h.Be formed with coupling electrode 42i on the surface of dielectric layer 11i.Be formed with electrode for capacitors 36j, 37j on the surface of dielectric layer 11j.Be formed with grounding electrode 46k on the surface of dielectric layer 11k.
Come to be connected with coil electrode 27e, 28e respectively by the through hole electrode that connects dielectric layer 11d in one end of coil electrode 27d, 28d.Coil electrode 27d, 27e, coil electrode 28d, 28e form respectively inductor.The other end of coil electrode 27d, 28d is drawn to a side and another side of duplexer respectively.
Electrode for capacitors 36h, 36j draw to a side of duplexer respectively, interconnect by the side electrode that is formed at this side.Electrode for capacitors 36h is relative with grounding electrode 47g across dielectric layer 11g, thereby forms electric capacity.Electrode for capacitors 36j is across dielectric layer 11j and relative with grounding electrode 46k, thereby forms electric capacity.Similarly, electrode for capacitors 37h, 37j draw to another side of duplexer respectively, interconnect by the side electrode that is formed at this side.Electrode for capacitors 37h is across dielectric layer 11g and relative with grounding electrode 48g, thereby forms electric capacity.Electrode for capacitors 37j is across dielectric layer 11j and relative with grounding electrode 46k, thereby forms electric capacity.
Coupling electrode 42i is across dielectric layer 11h and relative with electrode for capacitors 36h, 37h, thereby forms coupling capacitance, and coupling electrode 42i is across dielectric layer 11i and relative with electrode for capacitors 36j, 37j, thereby forms coupling capacitance.
Utilize above-mentioned electric capacity and inductor to form the stack filter of present embodiment.
In addition, surface electrode 41a, by being formed on the side electrode of a side of duplexer, is connected with electrode for capacitors 36h, 36j with coil electrode 27d.Surface electrode 41b, by being formed on the opposing party's the side electrode of side of duplexer, is connected with electrode for capacitors 37h, 37j with coil electrode 28d.Surface electrode 41a, 41b are equivalent to the input and output terminal of the stacked LC filter of present embodiment.
In the present embodiment, surface electrode 41a, 41b, terminal electrode 51a～56a are the installing electrodes using in the installation of cascade type LC filter.In the time that cascade type LC filter is installed on to substrate, the grafting material of installing electrodes by scolding tin etc. and engaging with the terminal pad of substrate.Surface electrode 41a is formed on an interarea of duplexer of the installed surface that forms duplexer.And the internal electrode pattern of the most approaching interarea relative with installed surface becomes grounding electrode 46b.
And, in the present embodiment, for the interarea from being formed with surface electrode 41a, 41b, terminal electrode 51a～56a, to the relative dielectric constant that approaches most the dielectric layer 11a the grounding electrode 46b of interarea, it is lower than forming dielectric layer 11g, 11h of capacitor, the relative dielectric constant of 11i, 11j.In this case, can be suppressed at grounding electrode 46b and become the parasitic capacitance producing between surface electrode 41a, the 41b of input and output terminal, can make the characteristic of stacked LC filter stable.
In addition, present embodiment is not limited to above-mentioned execution mode, can do various changes in the scope that does not depart from main idea.
Claims (8)
1. a cascade type LC filter, is characterized in that, has:
Duplexer, this duplexer is to be laminated by the multiple dielectric layers that are formed with internal electrode pattern on surface, and forms coil and capacitor by described dielectric layer and described internal electrode pattern, and has two interareas vertical with stacked direction; And
Surface electrode, this surface electrode is formed on the interarea of described duplexer,
For the described interarea from being formed with described surface electrode, to the relative dielectric constant that approaches most the dielectric layer the internal electrode pattern of described interarea, it is lower than the relative dielectric constant of dielectric layer that forms described capacitor.
2. cascade type LC filter as claimed in claim 1, is characterized in that,
Described surface electrode is the identification mark for identifying,
An interarea of described duplexer forms the installed surface of described duplexer, and described surface electrode is formed on another interarea of described duplexer.
3. cascade type LC filter as claimed in claim 1, is characterized in that,
In the time observing from stacked direction, described surface electrode is to form in the overlapping mode in multiple positions with the internal electrode pattern of the most approaching interarea that is formed with described surface electrode.
4. cascade type LC filter as claimed in claim 2, is characterized in that,
In the time observing from stacked direction, described surface electrode is to form in the overlapping mode in multiple positions with the internal electrode pattern of the most approaching interarea that is formed with described surface electrode.
5. the cascade type LC filter as described in any one of claim 1 to 4, is characterized in that,
The internal electrode pattern of the most approaching interarea that is formed with described surface electrode is formed with on same dielectric layer multiple, in the time observing from stacked direction, described surface electrode is with the overlapping mode of multiple internal electrode patterns and form.
6. the cascade type LC filter as described in any one of claim 1 to 4, is characterized in that,
One or more internal electrode patterns of the most approaching interarea that is formed with described surface electrode form coil,
In the time observing from stacked direction, described surface electrode with described internal electrode pattern in the overlapping mode of multiple parts of an internal electrode pattern and form.
7. cascade type LC filter as claimed in claim 5, is characterized in that,
One or more internal electrode patterns of the most approaching interarea that is formed with described surface electrode form coil,
In the time observing from stacked direction, described surface electrode with described internal electrode pattern in the overlapping mode of multiple parts of an internal electrode pattern and form.
8. cascade type LC filter as claimed in claim 1, is characterized in that,
Described surface electrode is the installing electrodes using in the installation of described cascade type LC filter,
An interarea of described duplexer forms the installed surface of described duplexer, and described surface electrode is formed on a described interarea,
The interarea nearest internal electrode pattern relative with installed surface from described duplexer is grounding electrode.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011245803 | 2011-11-09 | ||
| JP2011-245803 | 2011-11-09 | ||
| PCT/JP2012/076756 WO2013069419A1 (en) | 2011-11-09 | 2012-10-17 | Stacked lc filter |
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| Publication Number | Publication Date |
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| CN203734631U true CN203734631U (en) | 2014-07-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201290000776.8U Expired - Lifetime CN203734631U (en) | 2011-11-09 | 2012-10-17 | Stacked-type LC filter |
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| Country | Link |
|---|---|
| CN (1) | CN203734631U (en) |
| TW (1) | TWI500262B (en) |
| WO (1) | WO2013069419A1 (en) |
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| CN114502904A (en) * | 2020-02-20 | 2022-05-13 | 日本碍子株式会社 | Dielectric drying method and dielectric drying device for ceramic molded body, and method for manufacturing ceramic structure |
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| JP5907124B2 (en) * | 2013-07-24 | 2016-04-20 | 株式会社村田製作所 | High frequency components and filter components |
| JP2016540467A (en) * | 2014-04-03 | 2016-12-22 | 深▲せん▼振華富電子有限公司 | Multilayer chip type ceramic radio frequency low pass filter and method of manufacturing the same |
| TWI630792B (en) * | 2016-08-17 | 2018-07-21 | 村田製作所股份有限公司 | Multilayer LC filter |
| TWI643454B (en) * | 2016-10-05 | 2018-12-01 | 日商村田製作所股份有限公司 | Multilayer LC filter |
| TWI648949B (en) * | 2016-11-18 | 2019-01-21 | 日商村田製作所股份有限公司 | LC filter |
| JP6791107B2 (en) | 2017-12-08 | 2020-11-25 | 株式会社村田製作所 | Stacked band pass filter |
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| JP3103296B2 (en) * | 1995-06-30 | 2000-10-30 | ティーディーケイ株式会社 | Dielectric porcelain, method of manufacturing the same, and electronic component using the same |
| JP2004312065A (en) * | 2003-04-01 | 2004-11-04 | Soshin Electric Co Ltd | Passive component |
| JP3900104B2 (en) * | 2003-04-10 | 2007-04-04 | 松下電器産業株式会社 | Antistatic parts |
| JP4442154B2 (en) * | 2003-08-13 | 2010-03-31 | 株式会社村田製作所 | Multilayer array parts |
| WO2005062464A1 (en) * | 2003-12-19 | 2005-07-07 | Murata Manufacturing Co., Ltd. | Surface-mounted passive electronic components, and structure and method for mounting them |
| US20080218083A1 (en) * | 2005-09-13 | 2008-09-11 | Koninklijke Philips Electronics, N.V. | Lamp Assembly Comprising a Reflector and a Method for Manufacturing the Lamp Assembly |
| JP5007499B2 (en) * | 2005-10-21 | 2012-08-22 | 株式会社村田製作所 | Noise filter array |
| JP2008147349A (en) * | 2006-12-08 | 2008-06-26 | Murata Mfg Co Ltd | Electronic component |
| WO2010100997A1 (en) * | 2009-03-02 | 2010-09-10 | 株式会社村田製作所 | Electronic component and electronic device |
| JP4983881B2 (en) * | 2009-09-28 | 2012-07-25 | 株式会社村田製作所 | Multilayer bandpass filter |
| JP2011114628A (en) * | 2009-11-27 | 2011-06-09 | Panasonic Corp | Common mode noise filter |
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| CN114502904A (en) * | 2020-02-20 | 2022-05-13 | 日本碍子株式会社 | Dielectric drying method and dielectric drying device for ceramic molded body, and method for manufacturing ceramic structure |
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| TW201330494A (en) | 2013-07-16 |
| TWI500262B (en) | 2015-09-11 |
| WO2013069419A1 (en) | 2013-05-16 |
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