CN203573977U - IC chip stacking packaging part with high packaging density and good high-frequency performance - Google Patents
IC chip stacking packaging part with high packaging density and good high-frequency performance Download PDFInfo
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- CN203573977U CN203573977U CN201320660340.8U CN201320660340U CN203573977U CN 203573977 U CN203573977 U CN 203573977U CN 201320660340 U CN201320660340 U CN 201320660340U CN 203573977 U CN203573977 U CN 203573977U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
The utility model provides an IC chip stacking packaging part with high packaging density and good high-frequency performance. Even-number layers of IC chips are stacked on a multi-loop QFN lead frame. IC chips without projected point are arranged on the odd-number layers. Reversely arranged IC chips with projected points are arranged on the even-number layers. The IC chips without projected point are connected with inner pins. Even-number layers of IC chips are stacked on an AAQFN lead frame, wherein IC chips with projected points are arranged on the odd-number layers, and reversely arranged IC chips without projected points are arranged on the even-number layers. The IC chips without projected points are connected with the inner pins. The adjacent IC chips are adhibited through high-temperature UV film. The IC chip stacking packaging part with high packaging density and good high-frequency performance is realized through steps of: wafer thinning scribing, core arranging, pressure welding, plastic packaging, pin separating, chemical plating, printing, product separating, checking, testing and packaging. The packaging part can replace CPS produced from substrate, thereby realizing flexible application of IC chips in CSP packaging of the lead frame, improving production efficiency and reducing production cost.
Description
Technical field
The utility model belongs to electronic information Element of automatic control manufacturing technology field, relates to a kind of many IC chip stacked packaging piece, is specifically related to the IC chip stacked packaging piece that the large high frequency performance of a kind of packaging density is good.
Background technology
Along with electronic market to less, gentlier, the thinner expansion of various multi-functional mobile phone demands and the growth of the electronic device applications of PAD rank, impel electronics industry integrated antenna package to the development of miniaturization, multifunctional direction, stacked package has become and has met less, lighter, the multi-purpose a kind of important technological means of product.It makes in single package body can stacking multiple IC chips, realize the multiplication of the capacity of the confined space; It impels bonding line obviously to shorten chip direct interconnection, and signal transmission interference faster and that be subject to is less; And with the stack of this packaging part series products chip, internal memory is larger, multiple this packaging part of difference functional chips are stacked, and can make single package realize greater functionality, have the advantages such as low in energy consumption, speed is fast.Along with the raising of the technological levels such as attenuate, scribing, upper core, bonding, plastic packaging, stacked package technology can meet the many laminations of different this packaging part clients, many pins, high density, high reliability and encapsulate the requirement of many structure diversifications.But current number of pins is few and the QFN of high bank lamination and other packing forms can not be satisfied with the requirement of the low radian bonding wire of many I/O, restriction product packaging density, affects the limitation problem of high frequency performance.
Utility model content
The purpose of this utility model is to provide the IC chip stacked packaging piece of a kind of multi-turn QFN, and number of pins is more, and low bank lamination, improves the packaging density of product.
For achieving the above object, the technical scheme that the utility model adopts is: the IC chip stacked packaging piece that the large high frequency performance of a kind of packaging density is good, comprise lead frame and plastic-sealed body, when lead frame adopts multi-turn QFN lead frame, stacking on lead frame have an at least two-layer IC chip, and the total number of plies of IC chip is even number, in the IC of odd-level chip for not being with salient point IC chip, in the IC of even level chip, it is band salient point IC chip, band salient point IC flip-chip, ground floor is not with salient point IC chip to be connected with the first interior pin by first key zygonema, all the other are not with salient point IC chip to be connected with the second interior pin by bonding line,
When lead frame adopts AAQFN lead frame, stacking on lead frame have an at least two-layer IC chip, and the total number of plies of IC chip is even number, in the IC of odd-level chip, it is band salient point IC chip, in the IC of even level chip for not being with salient point IC chip, band salient point IC flip-chip, the salient point on ground floor band salient point IC chip is connected with the first interior pin, and all salient point IC chips of not being with are connected with the second interior pin by bonding line;
The described size with salient point IC chip is less than the adjacent not size with salient point IC chip; Bonding by high temperature UV film between adjacent two IC chips.
The utility model manufacture method can be according to client's needs, autonomous Design exploitation high density narrow pitch lead frame on bare copper frame plate, and core and lower filling in applicable upside-down mounting, plastic packaging; Framework thinning back side, repeatedly passivation and etching, growing metal layer, make UBM layer and plant the manufacturing process of ball, the AAQFN stacked package product of manufacturing, substitute the CPS of substrate production, realize IC chip flexible Application in the CSP of lead frame encapsulation, the CPS that compares substrate production has improved the rate of coming into force and has saved production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of 2 layers of IC chip stacked packaging piece in the utility model.
Fig. 2 is the structural representation of 4 layers of IC chip stacked packaging piece in the utility model.
Fig. 3 is the structural representation of 6 layers of IC chip stacked packaging piece in the utility model.
Fig. 4 is the more than 6 layers structural representation of IC chip stacked packaging piece in the utility model.
Fig. 5 is the structural representation that adopts 2 layers of IC chip stacked packaging piece of AAQFN lead frame in the utility model.
Fig. 6 is the structural representation that adopts 4 layers of IC chip stacked packaging piece of AAQFN lead frame in the utility model.
Fig. 7 is the structural representation that adopts 6 layers of IC chip stacked packaging piece of AAQFN lead frame in the utility model.
Fig. 8 is the structural representation that adopts the more than 6 layers IC chip stacked packaging piece of AAQFN lead frame in the utility model.
Fig. 9 fills schematic diagram under the plastic packaging adopting in the utility model.
In figure, 1. lead frame, 2. an IC chip, 3. the first bonding die glue, 4. the first interior pin, 5. the second interior pin, 6. plastic-sealed body, 7. the 2nd IC chip, 8. first key zygonema, 9. the second bonding die glue, 10. the 3rd IC chip, 11. the 4th IC chips, 12. second bonding lines, 13. the 3rd bonding die glue, 14. the 5th IC chips, 15. the 6th IC chips, 16. the 3rd bonding lines, 17. the 7th IC chips, 18. the 8th IC chips, 19. the 9th IC chips, 20. the tenth IC chips, 21. the 11 IC chips, 22. the 12 IC chips, 23. times inserts.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is elaborated.
The utility model packaging part is divided into the IC chip stacked packaging piece of multi-turn QFN and the IC chip stacked packaging piece of AAQFN.Illustrate respectively below:
One, the IC chip stacked packaging piece of multi-turn QFN
As shown in Figure 1, wherein 2 layers of IC chip stacked packaging piece, comprise lead frame 1, and lead frame 1 both sides, edge are provided with the first interior pin 4 and the second interior pin 5 successively away from the direction of lead frame 1; On lead frame 1, be pasted with an IC chip 3, the one IC chip 3 is pasted on lead frame 1 by the first bonding die glue 3, on the one IC chip 3, be pasted with the 2nd IC chip 7, the 2nd IC chip 7 is the IC chip with salient point, this IC chip with salient point is inverted, the salient point of the IC chip with salient point and an IC chip 3 are bonding, and the 2nd IC chip 7 is pasted on an IC chip 3 by high temperature UV film, lower inserts 23 after filling between the chip bump on the 2nd IC chip 7; The one IC chip 3 is connected with the first interior pin 4 by first key zygonema 8, is packaged with plastic-sealed body 6 on lead frame 1; Lead frame 1, an IC chip 3, the 2nd IC chip 7, the first interior pin 4, the second interior pin 5, first key zygonema 7 and all adhesive films are all packaged in plastic-sealed body 6.
As shown in Figure 2, wherein 4 layers of IC chip stacked packaging piece, shown in its structure and Fig. 1, the structure of 2 layers of IC chip stacked packaging piece is basic identical, 4 layers of IC chip stacked packaging piece are exactly on the basis of 2 layers of IC chip stacked packaging piece, to have increased two-layer IC chip, on the 2nd IC chip 7, be bonded with the 3rd IC chip 10, the 3rd IC chip 10 is pasted on the 2nd IC chip 7 by the second bonding die glue 9, and the second bonding die glue 9 is high temperature UV film; On the 3rd IC chip 10, be pasted with the 4th IC chip 11, the 4th IC chip 11 is the IC chip with salient point, this IC chip is inverted, and the salient point of the IC chip with salient point and the 3rd IC chip 10 are pasted, each with being all filled with lower inserts 23 between the chip bump on salient point IC chip; The 3rd IC chip 10 is connected with the second interior pin 5 by the second bonding line 12.The second bonding die glue 9, the 3rd IC chip 10, the 4th IC chip 11 and the second bonding line 12 are also all packaged in plastic-sealed body 6.
As Fig. 3, wherein 6 layers of IC chip stacked packaging piece, its structure is basic identical with the structure of 4 layers of IC chip stacked packaging piece as shown in Figure 2, 6 layers of IC chip stacked packaging piece are exactly on the basis of 4 layers of IC chip stacked packaging piece, to have increased two-layer IC chip, that is: on the 4th IC chip 11, be bonded with the 5th IC chip 14, the 5th IC chip 14 is pasted on the 4th IC chip 11 by the 3rd bonding die glue 13, the 3rd bonding die glue 13 adopts high temperature UV film, on the 5th IC chip 14, be pasted with the 6th IC chip 15, the 6th IC chip 15 adopts salient point IC chip, the 6th IC chip 15 is inverted, the salient point of the 6th IC chip 15 and the 5th IC chip 14 are pasted, each with being all filled with lower inserts 23 between the chip bump on salient point IC chip, the 5th IC chip 14 is connected with the second interior pin 5 by the 3rd bonding line 16.The 5th IC chip 14, the 6th IC chip 15, the 3rd bonding die glue 13 and the 3rd bonding line 16 are also all packaged in plastic-sealed body 6.
Exceed six layers of packaging part that IC is chip-stacked, as shown in Figure 4.Exactly take 6 layers of IC chip stacked packaging piece as basis, the IC chip of stacking respective numbers on the IC chip of 6 layers of IC chip stacked packaging piece the superiors as required, the chip-stacked number of plies of IC is even number, and the stacking IC chip with salient point be not with the setting of salient point IC street, when stacking, adopt high temperature UV film to paste adjacent two layers IC chip, each with being all filled with lower inserts 23 between the chip bump on salient point IC chip; The stacking salient point IC chip of not being with is connected with the second interior pin 5 by bonding line.All IC chips, all bonding lines and all high temperature UV films are all packaged in plastic-sealed body 6.
The first bonding die glue 3 adopts conducting resinl or conductive adhesive film; Remaining bonding die glue all adopts high temperature UV film.Size with salient point IC chip is much smaller than the size with salient point IC chip not.
Two, the IC chip stacked packaging piece of AAQFN
2 layers of IC chip stacked packaging piece wherein, as shown in Figure 5, comprise AAQFN lead frame, this AAQFN lead frame is provided with and ranked first interior pin 4 more, the both sides that ranked first interior pin 4 are respectively equipped with one and ranked second interior pin 5 more, ranked first on interior pin 4 more and are pasted with the 7th IC chip 17, the seven IC chips 17 for band salient point IC chip, on the 7th IC chip 17, the row of chip bump is identical with the row of the first interior pin 4 on AAQFN lead frame, and it is mutually bonding that row's salient point and ranked first interior pin 4; On the 7th IC chip 17, by high temperature UV film, be pasted with between the chip bump on the 8th IC chip 18, the two IC chips 17 and be filled with lower inserts 23; The 8th IC chip 18 is connected with the second interior pin 5 by first key zygonema 8.AAQFN lead frame, the first all interior pins 4, all the second interior pin 5, the 7th IC chip 17, the 8th IC chip 18 and first key zygonemas 9 are all packaged in plastic-sealed body 6.
4 layers of IC chip stacked packaging piece wherein, as shown in Figure 6, these 4 layers of IC chip stacked packaging pieces are take 2 layers of IC chip stacked packaging piece shown in Fig. 5 as basis, stacking two-layer IC chip on the 8th IC chip 18.That is: on the 8th IC chip 18, be pasted with the 9th IC chip 19, the 9th IC chip 19 is band salient point IC chip, salient point on the 9th IC chip 19 is mutually bonding with the 8th IC chip 18 by high temperature UV film, on the 9th IC chip 19, be pasted with the tenth IC chip 20, the tenth IC chip 20 is pasted on the 9th IC chip 19 by high temperature UV film, each with being all filled with lower inserts 23 between the chip bump on salient point IC chip; Each with being all filled with lower inserts 23 between the chip bump on salient point IC chip; The tenth IC chip 20 is connected with the second interior pin 5 by the second bonding line 12.The 9th IC chip 19, the tenth IC chip 20 and the second bonding line 12 are also packaged in plastic-sealed body 6.
6 layers of IC chip stacked packaging piece wherein, as shown in Figure 7, these 6 layers of IC chip stacked packaging pieces are take 4 layers of IC chip stacked packaging piece shown in Fig. 6 as basis, stacking two-layer IC chip on the tenth IC chip 20.That is: on the tenth IC chip 20, be pasted with the 11 IC chip 21, the 11 IC chip 21 is band salient point IC chip, salient point on the 11 IC chip 21 is mutually bonding with the tenth IC chip 20 by high temperature UV film, on the 11 IC chip 21, be pasted with the 12 IC chip 22, the 12 IC chip 22 is pasted on the 11 IC chip 21 by high temperature UV film, each with being all filled with lower inserts 23 between the chip bump on salient point IC chip; The 12 IC chip 22 is connected with the second interior pin 5 by the 3rd bonding line 16.The 11 IC chip the 21, the 12 IC chip 22 and the second bonding line 16 are also packaged in plastic-sealed body 6.
Wherein exceed six layers of packaging part that IC is chip-stacked, as shown in Figure 8.Exactly take 6 layers of IC chip stacked packaging piece shown in Fig. 7 as basis, the IC chip of stacking respective numbers on the IC chip of 6 layers of IC chip stacked packaging piece the superiors as required, the chip-stacked number of plies of IC is even number, and stacking band salient point IC chip be not with the setting of salient point IC street, when stacking, adopt high temperature UV film to paste adjacent two layers IC chip, each with being all filled with lower inserts 23 between the chip bump on salient point IC chip; The stacking salient point IC chip of not being with is connected with the second interior pin 5 by bonding line.All IC chips, all bonding lines and all high temperature UV films are all packaged in plastic-sealed body 6.
In this packaging part, the size with salient point IC chip of flip chip bonding is much smaller than the size with salient point IC chip not, and the size of the high temperature UV film between adjacent two layers IC chip is not with basic identical with the IC chip size of salient point IC chip.High temperature UV film can be sealed lower floor's bonding wire after at high temperature softening, and lower floor's bonding wire is played to protection and supporting role, prevents from breasting the tape, and improves test yield.All IC chips are connected with interior pin by gold (copper) line bonding, the power supply of forming circuit and signalling channel.
The utility model packaging part adopts the method for core combination stacked encapsulation in upper core pressure welding, upside-down mounting, in package thickness allowed band, can increase arbitrarily the stacking number of plies, improves packaging density and increases circuit function and storage density.Adopt upside-down mounting bonding die, both can reduce every layer of average thickness, can improve again circuit frequency of utilization.Improve packaging density, shortened signal transmission distance, increase internal memory, make product function many, high frequency performance is good.And, adopt the mode that in this upper core, pressure welding, upside-down mounting, core combination stacked encapsulates, also can be used for other form lead frames and baseplate material encapsulation.
The utility model packaging part is the requirement that can not be satisfied with the low radian bonding wire of many I/O for the QFN of current low pin count and high bank lamination and other packing forms, restriction product packaging density, and the limitation problem that affects high frequency performance is developed.Adopt core in core on high temperature UV membranous type, pressure welding and upside-down mounting, or the production technology that in upside-down mounting, on core, high temperature UV membranous type, core and pressure welding are combined, production multiple-level stack encapsulating products, had both improved stacked package density, had improved again high frequency performance.
The manufacture method of the utility model packaging part:
Step 1: reduction scribing
Adopt the anti-chip bump of thick glued membrane scratch (testing by DOE), (thickness >=150 μ m) to select thick glued membrane, Full-automatic film, while cutting film according to wafer gulde edge shape, corresponding blade running orbit parameter be set and cut film speed, guaranteeing that the running orbit of film sitting blade changes with glued membrane gulde edge; The lower cutter speed of cutting membrane knife when contact crystal round fringes is 10～30mm/sec, and while cutting film, the angle between cutting membrane knife and wafer plane is 75 °～90 °; To the wafer with salient point and not the wafer with salient point carry out attenuate and scribing, attenuate adopt corase grind+fine grinding+corrosion+polishing, wafer thickness is controlled at 150 μ m, wafer rear roughness≤0.4 μ m; During the wafer attenuate with salient point, do not adopt corase grind+fine grinding+corrosion+glossing, wafer final thickness is controlled in 100 μ m, the surface roughness≤0.3 μ m after attenuate.
Band salient point wafer rear after attenuate and be not with salient point wafer rear to paste high temperature UV film, then adopts the anti-fragment scribing process of double-pole staged to carry out scribing.
Step 2: upper core
For the IC chip stacked packaging piece of multi-turn QFN: get multi-turn QFN lead frame, the high temperature UV film of use with high-temperature baking and the equipment with core on high temperature UV film, core on the IC chip with salient point not, on multi-turn QFN lead frame, is toasted to 1～2h at the temperature of 100 ℃～140 ℃; With spun gold or copper cash from this not the IC chip with salient point to the flat arc routing of the first interior pin, form first key zygonema; Then use upside-down mounting chip feeder (model: 2S8912DA, advanced person Pacific Ocean Hong Kong Co., Ltd manufactures), at this IC chip of adhesive band salient point on the IC chip with salient point not, make salient point on this IC chip with salient point and IC die bonding with salient point, and between the chip bump with bump chip IC fill under filler 23, in this upside-down mounting, in core process, adopt core and lower fill process in upside-down mounting; If need the IC chip of stacking more multi-layered number, stack gradually as stated above the IC chip that requires the number of plies, and the number of plies of stacking IC chip is even number, odd-level is the IC chip of not being with salient point, even level is the IC chip with salient point of upside-down mounting, from the number of plies, be positioned at the 3rd layer not starting up with the IC chip of salient point, all with spun gold or copper cash in height arc routing mode from all not IC chips with salient point to the second interior pin routing;
For the IC chip stacked packaging piece of AAQFN: use upside-down mounting chip feeder by core on the IC chip with salient point to AAQFN lead frame, make salient point on this IC chip with salient point with AAQFN lead frame on the first interior pin mutually bonding, and between the chip bump with salient point IC chip and chip bump fill under filler 23, in this upside-down mounting, in core process, adopt core and lower fill process in upside-down mounting; The high temperature UV film of use with high-temperature baking and have the equipment of core on high temperature UV film on multi-turn QFN lead frame, toasts 1～2h by core on the IC chip with salient point not at the temperature of 100 ℃～140 ℃; With spun gold or copper cash from this not the IC chip with salient point to the flat arc routing of the first interior pin, form first key zygonema; If need the IC chip of stacking more multi-layered number, by upper core after the above-mentioned IC chip of first going up core band salient point, with the IC chip method of salient point, do not stack gradually the IC chip of the requirement number of plies, and the number of plies of stacking IC chip is even number, odd-level is the IC chip with salient point of upside-down mounting, even level is the IC chip of not being with salient point, from the number of plies, be positioned at the 4th layer not starting up with the IC chip of salient point, all with spun gold or copper cash in flat arc routing mode from all not IC chips with salient point to the second interior pin routing; Core and lower fill process in upside-down mounting: on upside-down mounting chip feeder, first will be with the upset of salient point IC chip, and be stained with after scolder, auto-alignment is placed into UBM(metalization under bump corresponding on the lead frame of core in upside-down mounting, under salient point, metallize) position, as shown in Figure 9; On whole piece framework, after complete chip, income is transmitted box automatically, and in flip-chip, the semi-finished product lead frame after core transmits box and delivers to Reflow Soldering operation by the gross.Passing through DOE (Design of Experiment, EXPERIMENTAL DESIGN) test under definite thermal reflow profile, by UBM corresponding on tin salient point, scolder and lead frame on chip by Reflow Soldering hot melt, UBM on chip and lead frame is firmly welded together, directly substituted traditional upper core and bond technology.By DOE (Design of Experiment, EXPERIMENTAL DESIGN) test and choose suitable lower inserts (less filler), under vacuum suction, lower inserts can be filled the space between chip bump and chip bump with salient point IC chip fully completely, do not have cavity, prevent that soldered ball is shifted at high temperature.Lower filling process, referring to Fig. 9, adopts vacuum suction method, and left end breach is lower filler import, and right-hand member breach is lower filler outlet and exhaust passage, carries out lower filling in mold cavity.After baking, high temperature UV film is softening, can be by fixing to lower floor's gold thread or copper cash encirclement, and punching silk while avoiding plastic packaging.
Step 3: plastic packaging and rear solidifying
Adopt low stress (α
1≤ 1), the environmental protection plastic packaging material that meets the VEEE of European Union, ROHS association of low moisture absorption (hydroscopicity≤0.2%) and the multistage injection molding prototype software control packaging technology (software registration card number 0276826) of our company's utility model, realize without absciss layer, without empty plastic packaging; After plastic packaging, carry out rear solidifying.
Step 4: separate pin
The etching that adopts our company to develop combines with grinding and removes method (patent application < < tetra-limit flat leadless package parts and the production method > > thereof that the lead frame back side is greater than frame thickness 1/2nd thickness copper layers, application number 201210098828.6, publication No. CV102629599A, date of publication 2012.08.08) or laser cutting pin connect the method for muscle, the pin of realizing multi-turn QFN encapsulating products separates.
Step 5: chemical plating
If adopt laser cutting to separate pin, only need chemical plating one deck pure tin;
If the method cutting and separating pin that adopts etching to combine with grinding, first plates layer of copper, copper and copper are combined, and be combined, and then plate pure tin between copper facing and copper facing on plated copper layer;
Because step is above removed the company's muscle between pin, between pin, be separated from each other, therefore can not adopt electro-plating method to zinc-plated on pin bottom surface, can only adopt chemical deposition zinc-plated.
Step 6: adopt the technique of existing multi-turn QFN packaging part to print, products of separated, check, test, packing, make the IC chip stacked packaging piece that the large high frequency performance of packaging density is good.
The utility model stacking encapsulation method also can be used in other packing forms of lead frame or baseplate material.
Although illustrated and described in conjunction with the preferred embodiments the utility model, it will be understood by those skilled in the art that under the prerequisite of the spirit and scope of the present utility model that limit without prejudice to claims and can modify and convert.
Claims (3)
1. the IC chip stacked packaging piece that the large high frequency performance of packaging density is good, comprise lead frame and plastic-sealed body, it is characterized in that, when lead frame adopts multi-turn QFN lead frame, stacking on lead frame have an at least two-layer IC chip, and the total number of plies of IC chip is even number, in the IC of odd-level chip for not being with salient point IC chip, in the IC of even level chip, it is band salient point IC chip, band salient point IC flip-chip, between chip bump with salient point IC chip, be filled with lower inserts, ground floor is not with salient point IC chip to be connected with the first interior pin by first key zygonema, all the other are not with salient point IC chip to be connected with the second interior pin by bonding line,
When lead frame adopts AAQFN lead frame, stacking on lead frame have an at least two-layer IC chip, and the total number of plies of IC chip is even number, in the IC of odd-level chip, it is band salient point IC chip, in the IC of even level chip, for not being with salient point IC chip, band salient point IC flip-chip, is filled with lower inserts between the chip bump with salient point IC chip, salient point on ground floor band salient point IC chip is connected with the first interior pin, and all salient point IC chips of not being with are connected with the second interior pin by bonding line.
2. the good IC chip stacked packaging piece of the large high frequency performance of packaging density according to claim 1, is characterized in that, the described size with salient point IC chip is less than the adjacent not size with salient point IC chip.
3. the good IC chip stacked packaging piece of the large high frequency performance of packaging density according to claim 1, is characterized in that, bonding by high temperature UV film between adjacent two IC chips.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320660340.8U CN203573977U (en) | 2013-10-24 | 2013-10-24 | IC chip stacking packaging part with high packaging density and good high-frequency performance |
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| CN201320660340.8U CN203573977U (en) | 2013-10-24 | 2013-10-24 | IC chip stacking packaging part with high packaging density and good high-frequency performance |
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| CN203573977U true CN203573977U (en) | 2014-04-30 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994005A (en) * | 2017-12-27 | 2018-05-04 | 天水华天科技股份有限公司 | A kind of high reliability array locking-type lead frame and its application in an enclosure |
| CN110323198A (en) * | 2019-07-26 | 2019-10-11 | 广东气派科技有限公司 | Contactless upper lower chip packaging structure and its packaging method |
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2013
- 2013-10-24 CN CN201320660340.8U patent/CN203573977U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994005A (en) * | 2017-12-27 | 2018-05-04 | 天水华天科技股份有限公司 | A kind of high reliability array locking-type lead frame and its application in an enclosure |
| CN107994005B (en) * | 2017-12-27 | 2024-07-05 | 天水华天科技股份有限公司 | High-reliability array locking type lead frame and application of lead frame in packaging piece |
| CN110323198A (en) * | 2019-07-26 | 2019-10-11 | 广东气派科技有限公司 | Contactless upper lower chip packaging structure and its packaging method |
| CN110323198B (en) * | 2019-07-26 | 2024-04-26 | 广东气派科技有限公司 | Non-contact type upper and lower chip packaging structure and packaging method thereof |
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