CN102263077A - Double flat carrier-free pin-free IC chip packaging part - Google Patents
Double flat carrier-free pin-free IC chip packaging part Download PDFInfo
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- CN102263077A CN102263077A CN201110157792XA CN201110157792A CN102263077A CN 102263077 A CN102263077 A CN 102263077A CN 201110157792X A CN201110157792X A CN 201110157792XA CN 201110157792 A CN201110157792 A CN 201110157792A CN 102263077 A CN102263077 A CN 102263077A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention provides a double flat carrier-free pin-free IC chip packaging part which comprises a lead wire framework and an interior pin provided on the lead wire framework. The interior pin is provided with a first IC chip. The first IC chip connects with the interior pin through a bonding line, and the first IC chip bonds with the interior pin through a DAF membrane. According to the invention, the chip is directly bonded on the pin of the lead wire framework, thus the chip and the framework are in good combination, membrane thickness is uniform and deviation is very small; the bonding line directly connects with the interior pin in the lead wire framework from the chip, or connects with a chip from another chip, thus a bonding line length is substantially shortened, material is saved, and the framework can employ flip IC chip packaging.
Description
Technical field
The invention belongs to integrated circuit encapsulation manufacturing technology field, relate to a kind of IC chip-packaging structure, be specifically related to the IC chip package that a kind of two flat carrier-free does not have pin.
Background technology
The small shape encapsulated integrated circuit of DFN series grew up in recent years, used a kind of novel small shape encapsulation of giving birth to for the development need that satisfies ultrathin electronic products such as mobile phone, MP3, MP4.Have no pin, mount characteristics such as occupied area is little, setting height(from bottom) is low, and go between short and small, the plastic-sealed body size is little, packaging body is thin, can make CPU volume-diminished 30%～50%.So this microminiature encapsulation can provide remarkable electrical property, simultaneously, provides outstanding heat dispersion by the leadframe pad that exposes.But existing common DFN encapsulation only is used for common product, does not have high reliability request, and the lead frame of use does not have special anti-lamination defect designing requirement, and the encapsulating material of use also is general material.Simultaneously, in manufacture process, do not take anti-defective (layering) technological measure, cause common DFN encapsulation to have the following disadvantages:
1) adhesion of integrated circuit (IC) chip and carrier is bad, when be subjected to that external environment changes influence the time, can cause the inner lamination defect that produces of product, cause taking off of performance, even lost efficacy;
2) adhesion of the carrier back side and plastic packaging material is bad, when the influence that is subjected to external environment, can cause product to produce defective (layering); Or expose on the carrier (Ji Dao) thicker flash is arranged, bring difficulty for the follow-up flash that goes, increased the probability that produces lamination defect;
3) first placement of foot of DFN encapsulation is not easily distinguishable, and package fabrication process and client's use have been brought unnecessary trouble.
Summary of the invention
In order to overcome the shortcoming that exists in the above-mentioned prior art, the purpose of this invention is to provide the IC chip package that a kind of two flat carrier-free does not have pin, can make in integrated circuit (IC) chip and the lead frame between the pin in conjunction with firmly, be not subjected to the influence of external environment.
For achieving the above object, the technical solution adopted in the present invention is:
A kind of two flat carrier-free does not have the IC chip package of pin, comprise lead frame and go up the interior pin 1 that is provided with, interior pin 1 is provided with an IC chip, and an IC chip is connected with interior pin 1 by first bonding line, and an IC chip is mutually bonding with interior pin 1 by a DAF film.
Be bonded with the 2nd IC chip by the 2nd DAF film on the described IC chip, the 2nd IC chip is connected with interior pin 1 by second bonding line, and the 2nd IC chip also is connected with an IC chip by the 3rd bonding line.
IC chip package of the present invention directly is pasted on chip on the lead frame pin by the DAF film, and it is good especially to make that chip combines with framework, and film thickness is even, and deviation is also very little; Bonding line is directly got in the lead frame on the pin from chip, perhaps gets on the chip from chip, thereby has shortened bonding line length greatly, save material, and this framework can adopt upside-down mounting IC Chip Packaging.
Description of drawings
Fig. 1 is a single-chip package vertical view of the present invention.
Fig. 2 is single-chip package profile under the ram frame of the present invention.
Fig. 3 is single-chip package profile under the etched frame of the present invention.
Fig. 4 is multi-chip stacking encapsulation vertical view of the present invention.
Fig. 5 is multi-chip stacking encapsulation profile under the ram frame of the present invention.
Fig. 6 is multi-chip stacking encapsulation profile under the etched frame of the present invention.
Fig. 7 is a single-chip flip-chip packaged vertical view of the present invention.
Fig. 8 is the ram frame of the present invention flip-chip encapsulation cutaway view that places an order.
Fig. 9 is the etched frame of the present invention flip-chip encapsulation cutaway view that places an order.
Figure 10 is a kind of flip-chip packaged vertical view of multi-chip stacking of the present invention.
Figure 11 is the another kind of flip-chip packaged vertical view of multi-chip stacking of the present invention.
Figure 12 is a kind of flip-chip packaged cutaway view of multi-chip stacking under the etched frame of the present invention.
Figure 13 is the another kind of flip-chip packaged cutaway view of multi-chip stacking under the etched frame of the present invention.
Figure 14 is a kind of flip-chip packaged cutaway view of multi-chip stacking under the ram frame of the present invention.
Figure 15 is the another kind of flip-chip packaged cutaway view of multi-chip stacking under the ram frame of the present invention.
Embodiment
The present invention is described in detail below in conjunction with accompanying drawing.
Packaging part of the present invention comprises single-chip package, single-chip flip-chip packaged, multi-chip stacking encapsulation and multi-chip stacking flip-chip packaged.
As Fig. 1, Fig. 2 and shown in Figure 3, the structure of IC chip package single-chip package of the present invention, comprise lead frame and go up the interior pin 1 that is provided with, interior pin 1 is bonded with an IC chip 3 by a DAF film 2, the one IC chip 3 is connected with interior pin 1 by first bonding line 4, and the surface of interior pin 1 is sealed with plastic-sealed body 5; The one DAF film 2, an IC chip 3 and first bonding line 4 all are packaged in the plastic-sealed body 5.
The structure of packaging part multi-chip stacking encapsulation of the present invention, as Fig. 4, Fig. 5 and shown in Figure 6, comprise lead frame and go up the interior pin 1 that is provided with, interior pin 1 surface is bonded with on an IC chip 3, the one IC chips 3 by a DAF film 2 and is bonded with the 2nd IC chip 6 by the 2nd DAF film 7; The one IC chip 3 is connected with interior pin 1 by first bonding line 4, and an IC chip 3 is connected with the 2nd IC chip 6 by second bonding line 9, and the 2nd IC chip 6 is connected with interior pin 1 by the 3rd bonding line 8; Be sealed with plastic-sealed body 5 on the interior pin 1.The one DAF film 2, an IC chip 3, the 2nd DAF film 7, the 2nd IC chip 6, first bonding line 4, second bonding line 9 and the 3rd bonding line 8 all are packaged in the plastic-sealed body 5.
Plastic-sealed body 5 surrounds in the multi-chip stacking encapsulation the 2nd IC chip 6, an IC chip 3, the 3rd bonding line 8, second bonding line 9, first bonding line 4, a DAF film 2, the 2nd DAF film 7 and interior pin 1 have constituted circuit integral body, and 5 pairs the one IC chips of plastic-sealed body 3, the 2nd IC chip 6, first bonding line 4 and second bonding line 9 have played the effect of support and protection.The one IC chip 3, the 2nd IC chip 6, first bonding line 4, second bonding line 9 and interior pin 1 have constituted the power supply and the protection passage of circuit.The multi-chip stacking packing forms can be formed in a plurality of chipsets in the plastic-sealed body, and integrated level height, product size are very little, can satisfy the requirement of integrated circuit encapsulation high-performance, vectorette, thin profile.
Packaging part of the present invention comprises frame inner pin, chip, DAF film, bonding line, plastic-sealed body, and lead frame is connected with chip by the DAF film.The last core process of tradition integrated circuit encapsulation, adopt the bonding die sheet adhesive, the glue amount of overflowing is difficult to control, and being easy to generate defectives such as layering and bonding die be in uneven thickness, the present invention adopts DAF film bonding die, directly is pasted on framework on DAF chip, chip combines with framework 100%, and the thickness of glued membrane is even, and deviation is at ± 25 μ m, and the yield of last core is high.
This packaging part has the advantages that carrier-free does not have pin, adopts the DAF film that chip directly is pasted on the framework surface, directly bonding line is got on the pin from chip during routing, and is very convenient; Its pin is arranged very dense, the width of whole plastic-sealed body can be controlled between 1.2mm～2.2mm, can greatly reduce product size, can also under the situation that possesses enough pins gap, carry out flip-chip packaged, the single-chip flip-chip packaged is with reference to Fig. 7, Fig. 8 and Fig. 9, and multicore sheet flip-chip packaged is with reference to Figure 10, Figure 11, Figure 12, Figure 13, Figure 14 and Figure 15.
The size of IC chip can reduce as far as possible in the carrier-free encapsulation, the IC chip can directly be attached on the lead frame, bonding line can be got in the lead frame on the pin from the IC chip, also can directly get on another chip from chip, thereby shorten the length of bonding line greatly, save material, and can reduce package dimension.
A kind of two flat carrier-free does not have the method for packing of the IC chip package of pin, and the technological process of production is as follows:
1) single-chip package
Wafer attenuate → scribing → last core (bonding die) → pressure welding → plastic packaging → back curing → plating → printing → product separation → visual inspection → test tape package → warehouse-in.
2) multi-chip stacking encapsulation
Wafer attenuate → scribing → last core (bonding die) → pressure welding → plastic packaging → back curing → plating → printing → product separation → visual inspection → test tape package → warehouse-in.
Adopt in the wafer attenuate operation and prevent chip warpage technology.During scribing, the wafer below 8 o'clock and 8 o'clock adopts DISC 3350 scribing machines or two scribing machine to carry out scribing, and wafer adopted the scribing of PG300RM/TCN scribing machine in 8 o'clock to 12 o'clock, and application is prevented fragment, prevented crackle scribing process software controlling technique.Select the environment-friendly type plastic packaging of low moisture absorption (hydroscopicity≤0.25%), low stress (coefficient of expansion α 1≤1) for use.Adopt the anti-warpage technology of ultrathin encapsulation, solve a difficult problem of dashing silk, warpage and absciss layer in the encapsulation process.Before the electroplating work procedure, remove earlier flash, adopt heat to boil softening and high pressure water impact combines goes flash technology, plastic part after elder generation will afterwards solidify is put into the softening liquid bath of being furnished with chemical materials such as S700 series and is soaked 25min～40min, then this plastic part being delivered to water under high pressure goes on the flash machine, by the pressure and the scouring force of water under high pressure, the flash of maceration on the plastic part is destroyed, reach the flash effect; Electroplate at the fully automatic electric plate wire again, electroplate back baking 2 hours.Adopt blade cutting machine, unit product is separated from framework, in the cutting and separating process, consider anti-colloid technology.
The chip feeder that possesses glue film and bonding die glued membrane bonding die is used in the multi-chip stacking encapsulation, adopts glue film (DAF film), notes control spill-out and glue film size (preferably being slightly less than chip).Core all will toast for twice on the glue film, adopts anti-layering baking process.Multi-chip stacking encapsulation is owing to existing chip and chip on chip and chip, chip and pin, the same chip bonding pad, have chip and an interior pin routing again, and chip and chip chamber bonding wire lack, and the bonding wire that chip arrives between interior pin is longer.Employing lamination routing and reverse routing technology, the multi-functional bonding machine that service precision is higher satisfies height arc, short-term routing and reverse routing function.Multi-chip stacking encapsulation considers that upper strata chip and lower floor's chip chamber bonding wire are shorter, plastic packaging has the potential risk of open circuit, bonding wire between upper strata chip welding spot and interior pin is longer, it is big or have short circuit hidden danger to dash curved rate, need to adopt multistage injection moulding erosion control silk, anti-absciss layer technology, satisfy the processing quality requirement.
Claims (2)
1. two flat carrier-frees do not have the IC chip package of pin, comprise lead frame and go up the interior pin (1) that is provided with, interior pin (1) is provided with an IC chip, the one IC chip is connected with interior pin (1) by first bonding line, it is characterized in that an IC chip is mutually bonding with interior pin (1) by a DAF film.
2. a kind of two flat carrier-frees according to claim 1 do not have the IC chip package of pin, it is characterized in that, be bonded with the 2nd IC chip by the 2nd DAF film on the described IC chip, the 2nd IC chip is connected with interior pin (1) by second bonding line, and the 2nd IC chip also is connected with an IC chip by the 3rd bonding line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110157792XA CN102263077A (en) | 2011-06-13 | 2011-06-13 | Double flat carrier-free pin-free IC chip packaging part |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110157792XA CN102263077A (en) | 2011-06-13 | 2011-06-13 | Double flat carrier-free pin-free IC chip packaging part |
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| CN102263077A true CN102263077A (en) | 2011-11-30 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543937A (en) * | 2011-12-30 | 2012-07-04 | 北京工业大学 | Flip chip on-chip package and manufacturing method thereof |
| CN102543907A (en) * | 2011-12-31 | 2012-07-04 | 北京工业大学 | Package and manufacture method for thermal enhanced quad flat no-lead flip chip |
| CN106876282A (en) * | 2016-12-20 | 2017-06-20 | 杰群电子科技（东莞）有限公司 | A kind of heat sink of semiconductor devices except gluing method and except adhesive dispenser |
| CN112830448A (en) * | 2021-01-19 | 2021-05-25 | 潍坊歌尔微电子有限公司 | Microphone packaging process and microphone packaging structure |
| WO2022179229A1 (en) * | 2021-12-02 | 2022-09-01 | 深圳麦克韦尔科技有限公司 | Heating element module and preparation method therefor, packaging module and electronic atomization device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1773700A (en) * | 2004-11-08 | 2006-05-17 | 日月光半导体制造股份有限公司 | Packing structure of multichip |
| CN201417765Y (en) * | 2009-04-01 | 2010-03-03 | 苏州固锝电子股份有限公司 | Base island free semi-conductor chip package structure |
| CN201508834U (en) * | 2009-10-17 | 2010-06-16 | 天水华天科技股份有限公司 | Double flat pin-free encapsulating part |
| CN102004940A (en) * | 2010-11-30 | 2011-04-06 | 天水华天科技股份有限公司 | High-density SIM (Subscriber Identity Module) card packaging element and production method thereof |
| CN102074559A (en) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | SiP (Session Initiation Protocol) system integrated-level IC (Integrated Circuit) chip packaging part and manufacturing method thereof |
-
2011
- 2011-06-13 CN CN201110157792XA patent/CN102263077A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1773700A (en) * | 2004-11-08 | 2006-05-17 | 日月光半导体制造股份有限公司 | Packing structure of multichip |
| CN201417765Y (en) * | 2009-04-01 | 2010-03-03 | 苏州固锝电子股份有限公司 | Base island free semi-conductor chip package structure |
| CN201508834U (en) * | 2009-10-17 | 2010-06-16 | 天水华天科技股份有限公司 | Double flat pin-free encapsulating part |
| CN102074559A (en) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | SiP (Session Initiation Protocol) system integrated-level IC (Integrated Circuit) chip packaging part and manufacturing method thereof |
| CN102004940A (en) * | 2010-11-30 | 2011-04-06 | 天水华天科技股份有限公司 | High-density SIM (Subscriber Identity Module) card packaging element and production method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543937A (en) * | 2011-12-30 | 2012-07-04 | 北京工业大学 | Flip chip on-chip package and manufacturing method thereof |
| CN102543907A (en) * | 2011-12-31 | 2012-07-04 | 北京工业大学 | Package and manufacture method for thermal enhanced quad flat no-lead flip chip |
| CN106876282A (en) * | 2016-12-20 | 2017-06-20 | 杰群电子科技（东莞）有限公司 | A kind of heat sink of semiconductor devices except gluing method and except adhesive dispenser |
| CN106876282B (en) * | 2016-12-20 | 2019-08-02 | 杰群电子科技（东莞）有限公司 | A kind of heat sink of semiconductor devices except gluing method and remove adhesive dispenser |
| CN112830448A (en) * | 2021-01-19 | 2021-05-25 | 潍坊歌尔微电子有限公司 | Microphone packaging process and microphone packaging structure |
| CN112830448B (en) * | 2021-01-19 | 2023-12-26 | 潍坊歌尔微电子有限公司 | Microphone packaging technology and microphone packaging structure |
| WO2022179229A1 (en) * | 2021-12-02 | 2022-09-01 | 深圳麦克韦尔科技有限公司 | Heating element module and preparation method therefor, packaging module and electronic atomization device |
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