CN108736885A - The clock phase-splitting method of phase-locked loop clock edging trigger - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The clock phase-splitting method of phase-locked loop clock edging trigger, belongs to time interval measurement field, and the present invention is to solve the problems, such as that existing clock phase-splitting method resolution ratio is relatively low, system operation frequency is high, performance is relatively low.Detailed process of the present invention is：Clock signal 100MHz is input to the input terminal of phaselocked loop；By clock signal frequency multiplication to 315MHz, high level section is subjected to eight phase shifts；Using the edge of the clock signal after frequency multiplication of phase locked loop phase shift as trigger signal；Measured signal is subjected to clock synchronization process；Temporal constraint is carried out respectively to clock signal and every transmission paths of measured signal；The position that measured signal level saltus step occurs in triggering moment is extracted；High level is exported when rising edge occur in measured signal rising edge detection function or measured signal failing edge detection function, otherwise exports low level；Obtain the relative position of measured signal rising edge or failing edge within a clock cycle.The present invention is used for time interval measurement.
Description
Technical field
The present invention relates to a kind of time interval measurement methods, belong to time interval measurement field.
Background technology
Time is one of base unit of physics.Our, there are two types of meanings usually said times：What a kind of meaning referred to
It is the moment, and another meaning refers to time interval.Moment refer to the time continuously to pass certain in a flash, it refers to certain
When one event occurs；And time interval refer to interval between two moments how long, it refers to a certain event
Duration.
Basic physical parameter of the accurate time as scientific research, scientific experiment and engineering technology aspects is all
Dynamic system and when program process measurement and quantitative study basis coordinates when providing essential.The accurate time not only exists
It Nuclear Physics research, particle physics research, geodynamic study, the theory of relativity research, pulsar cycle studies and artificial defends
There is an important role in the basic research fields such as star dynamics geodetic, and the communication of such as aerospace, deep space, satellite launch and
Also have in the application studies such as monitoring, geological mapping, navigational communications, power transmission and Scientific Measurement, national defence and the development of the national economy
Universal application, or even people different social sectors have been deep into, almost without less than.
With the increasingly raising of people's living standard, high-resolution time interval measurement technology is more and more applied
In various civil fields.The science and technology in China, civil field key skill will be greatly promoted to the research of time interval measurement method
The development of art.And traditional time interval measurement be rely on analogue measurement, but with the development of science and technology with high-precision demand and
The various limitations of analog measurement method, this measurement method far can not meet the needs of time interval measurement, so such as
What using digital measurement time interval becomes more important, and present digital measurement is mainly based on FPGA and ASIC, but ASIC
Because the defects of its design cycle is long, correcting investment is big, flexibility is poor, restricts its application range.And FPGA is because of operation speed
Spending the advantages such as fast, programmable, the development cycle is short, flexibility is strong becomes the main platform of people's realization Digital Logic, thus grinds
Study carefully the high speed and precision time interval measurement technology based on FPGA to have important practical significance.
Time-to-digital conversion circuit is the basic means measured the time, it is converted to the analog signal for carrying temporal information
Digital signal digitizes, to realize the measurement of temporal information.On the other hand, absolute temporal information is often not too many
Meaning, but opposite temporal information is just significant, so many occasions are all the measurements of time interval information.
In many applications, the measurement of some physical quantitys can be converted to the measurement of time quantum, such as flow, thickness, close
The physical quantitys such as degree, temperature, frequency and phase shift.
Such as pulse type laser ranging, principle is similar to radar range finding, general first to be sent out by laser diode alignment target
Laser pulse is penetrated, laser is scattered to all directions after target reflects, and some scattered light returns to sensing receiver, by optical system
It is imaged onto on avalanche photodide after reception.Avalanche photodide is a kind of optical sensing of the inside with enlarging function
Device, therefore it can detect extremely faint optical signal.Record and handle from light pulse be issued to return be received undergone it is past
The time is returned, the half of two-way time is multiplied by with the light velocity (300,000 thousand meter per second), is exactly the distance to be measured.If light with
Speed c is propagated in air, is t the time required to A, B point-to-point transmission round trip, then A, B distance between two points D can use following formula table
Show:
D=ct/2 (1)
Very widely used today hand-held and Portable distance meter, operating distance are hundreds of meters to tens of kms, measure essence
Degree is five meters or so.The high precision distance detector to satellite ranging that China develops, measurement accuracy can reach several centimetres.Because of the light velocity
Too fast, transmission time laser sensor must extremely accurately measure transmission time, to make resolution ratio reach, then transmission time
The electronic circuit of distance measuring sensor must be able to tell very short time interval below.
Or be the thickness for needing to control sheet metal and pipeline wall etc. in some applications, it at this moment just needs to measure thick
Degree.The speed of ultrasonic wave and ultrasonic wave in respective media using ultrasonic wave on determinand surface and backside reflection back,
Corresponding thickness information can be calculated, here it is crucial that time interval measurement between reflected ultrasonic wave.
Thus research high speed and precision time interval measurement technology has very important realistic meaning.
Early stage time measurement technology develops, the electronics technologies such as semiconductor integrated circuit are relatively backward, this period,
Analogue measurement is the main stream approach of time interval measurement.Such as time-reversal mirror method, time voltage transformation approach etc., these methods be
In the time interval of required measurement, by current integration, the time quantum not directly measured is converted into measurable voltage
Or the quantity of electric charge, it is converted into digital quantity using A/D conversion circuits.
Time measurement demand constantly improves the development for having pushed time measurement technology.And at this time analogue measurement the shortcomings that
Also it is exposed increasingly, it is such as very sensitive, easy by external disturbance interference, the conversion that design is complicated, needs are long to temperature
Time etc..Especially in high-energy physics experiment, using analog circuit measuring system, it is difficult to meet the requirements, but skill is digitized
Art is increasingly becoming the hair of detector electronic system because of advantages such as its flexibility, stability, high speed, parallel processing, low costs
Open up direction.Then, Digital Measuring Technique starts the favor and welcome by researchers.
With the development of microelectric technique and technique, digital integrated electronic circuit is integrated electric from electron tube, transistor, middle and small scale
Road, super large-scale integration gradually develop to the application-specific integrated circuit of today.The realization rate of time-to-digital converter technology
It completes from discrete device to FPGA and the transformation of ASIC.Undoubtedly, the appearance of ASIC (application-specific integrated circuit) reduces product
Production cost improves the reliability of system, reduces the physical size of design, has pushed the digitlization process of society.But
The ASIC limitation of the scope of application and the powerful advantages of FPGA itself caused by its defect so that FPGA becomes the time
The main application platform of number conversion.
In numerous time figure measuring techniques, the time-to-digital converter technical characteristic based on FPGA is mainly reflected in
On hardware configuration and smaller logic gate delay special FPGA.For example, time delay line method, delay lock loop (DLL) skill
Art etc. is all using the delay of device itself come time of measuring interval.Its basic thought is that one kind is found in device substantially
This element is cascaded up to form delay chain structure by delay unit by certain mode, and allows the time to be measured by delay chain, real
Existing temporal interpolation.Indicate this time interval eventually by the quantity of basic delay unit, to realize from the time to
The conversion of number.
Invention content
The invention aims to solve, existing clock phase-splitting method resolution ratio is relatively low, system operation frequency is high, performance is relatively low
The problem of, provide a kind of clock phase-splitting method of phase-locked loop clock edging trigger.
The clock phase-splitting method of phase-locked loop clock edging trigger of the present invention, detailed process are：
Step 1, the input terminal that clock signal 100MHz is input to phaselocked loop；
Step 2, by clock signal 100MHz frequencys multiplication to 315MHz, the high level section of input clock is subjected to eight phase shifts,
Phase shift angle CLK [0]~CLK [7] is respectively set as 0 °, 22.5 °, 45 °, 66.5 °, 90 °, 112.5 °, 135 °, 157.5 °；
Step 3, using the edge of eight tunnel clock signals of frequency multiplication of phase locked loop phase shift Hou as 16 trigger signals；
Measured signal is carried out clock synchronization process by step 4；
Step 5 carries out temporal constraint respectively to clock signal and every transmission paths of measured signal；
Step 6 judges that in measured signal level Count [0]~Count [15] of 16 triggering moments be 0 or 1,
The position for 0 → 1 saltus step and 1 → 0 saltus step occur in Count [0]~Count [15] is extracted；
Step 7 records measured signal rising edge detection function with event_up_reg [n] or event_down_reg [n]
Rising edge/failing edge of event_up [n] or measured signal failing edge detection function event_down [n], when in measured signal
When there is rising edge along detection function event_up [n] or measured signal failing edge detection function event_down [n] in liter
Event_up_reg [n] or event_down_reg [n] exports high level, otherwise event_up_reg [n] or event_down_
Reg [n] exports low level；
Step 8 obtains the relative position of measured signal rising edge or failing edge in a clock cycle 315MHz, completes
Clock phase-splitting.
Advantages of the present invention：The clock phase-splitting method of phase-locked loop clock edging trigger proposed by the present invention can complete high property
Energy, high-resolution time interval measurement improve time measurement resolution compared with prior art, reduce the operation frequency of system
Rate.First with " thick " the survey part at interval of simple binary counter deadline, " thin " survey part uses clock phase-splitting
The high level part of clock (half of clock cycle) is only carried out eight phase shifts by method, and original resolution ratio is improved 16 times, is differentiated
Rate can be higher than 165ps, and equivalent measurement frequency using the present invention is that (input clock 100MHz, frequency is 6080MHz after frequency multiplication
315MHz), resolution ratio can be higher than 165ps, and traditional clock phase-splitting method is that the entire clock cycle is carried out average phase shift, this
Time measurement resolution can be improved under the premise of PLL tap finites by inventing the method proposed, reduced system operation frequency, reached
The measurement effect of higher performance.
Description of the drawings
Fig. 1 is pulse counting method schematic diagram；
Fig. 2 is interpolation horology schematic diagram；
Fig. 3 is part of data acquisition overall construction drawing；
Fig. 4 is frequency multiplication of phase locked loop phase shift schematic diagram；
Fig. 5 is data transfer path schematic diagram of the clock edge as trigger signal；
Fig. 6 is clock phase shift interpolation overall output schematic diagram；
Fig. 7 is " thin " the actual measurement output waveform figure for surveying part.
Specific implementation mode
Specific implementation mode one：The clock phase-splitting method of phase-locked loop clock edging trigger described in present embodiment, detailed process
For：
Step 1, the input terminal that clock signal 100MHz is input to phaselocked loop；
Step 2, by clock signal 100MHz frequencys multiplication to 315MHz, the high level section of input clock is subjected to eight phase shifts,
Phase shift angle CLK [0]~CLK [7] is respectively set as 0 °, 22.5 °, 45 °, 66.5 °, 90 °, 112.5 °, 135 °, 157.5 °；
Step 3, using the edge of eight tunnel clock signals of frequency multiplication of phase locked loop phase shift Hou as 16 trigger signals；
Measured signal is carried out clock synchronization process by step 4；
Step 5 carries out temporal constraint respectively to clock signal and every transmission paths of measured signal；
Step 6 judges that in measured signal level Count [0]~Count [15] of 16 triggering moments be 0 or 1,
The position for 0 → 1 saltus step and 1 → 0 saltus step occur in Count [0]~Count [15] is extracted；
Step 7 records measured signal rising edge detection function with event_up_reg [n] or event_down_reg [n]
Rising edge/failing edge of event_up [n] or measured signal failing edge detection function event_down [n], when in measured signal
When there is rising edge along detection function event_up [n] or measured signal failing edge detection function event_down [n] in liter
Event_up_reg [n] or event_down_reg [n] exports high level, otherwise event_up_reg [n] or event_down_
Reg [n] exports low level；
Step 8 obtains the relative position of measured signal rising edge or failing edge in a clock cycle 315MHz, completes
Clock phase-splitting.
In present embodiment, using the edge of the clock signal after frequency multiplication phase shift as trigger signal, can theoretically it incite somebody to action
Frequency after frequency multiplication carries out 16 times of subdivision again, to reach higher.As shown in figure 4, PLL is Phase Locked Loop, lock
Xiang Huan.
Specific implementation mode two：Present embodiment is described further embodiment one, eight road clocks described in step 3
The edge of signal includes the rising edge and failing edge of eight tunnel clock signals.
Specific implementation mode three：Present embodiment is described further embodiment one, by Count [0] described in step 5
Occurring the method that the position of 0 → 1 saltus step and 1 → 0 saltus step extracts in~Count [15] is：
Count [n] and Count [n+1] are calculated：
Appearance event_up [n]=(it is the position of 0 → 1 saltus step when~Count [n]) &Count [n+1]；
Appearance event_down [n]=(it is the position of 1 → 0 saltus step when~Count [n+1]) &Count [n]；
Wherein, n=0,1 ..., 15.
The present invention proposes the precise time-time-interval measurement method based on FPGA, by time interval measurement be divided into it is " thick " survey and
" thin " survey two parts, " thick " survey refers to carrying out preliminary surveying with counter, and the realization of " thin " survey mainly relies on clock phase-splitting method
Temporal interpolation is carried out, to obtaining higher temporal resolution.
Most basic method is pulse counting method in traditional time interval measurement technology.Pulse in pulse counting method is
Refer to reference clock signal CLK_IN, reference clock signal is time reference when pulse counting method is surveyed, therefore also known as time-base signal.It surveys
The event section of amount is made of initial signal (start signals) and termination signal (stop signals) two parts.Pulse counting method
Measuring principle is the comparison based on same dimension physical quantity.It is gone to fill tested time interval with time-base signal, by time-base signal
Step-by-step counting quantify tested time interval.Concrete operating principle as shown in Figure 1, start signals in T1Moment, which opens, to be counted
Device, stop count signals are in T2Moment stops counter, and start signals are along logical with time interval △ T of the stop signals between
Oversampling clock is that the counter of clk measures counting.
The time-to-digital converter that this method is realized, structure and logical comparison are simple.Its resolution ratio determines by the clock cycle,
The dynamic range of measurement is determined that the precision of measurement is determined by the stability of clock by the digit of counter.
Since the resolution ratio of pulse counting method is very low, in order to improve time measurement resolution, using temporal interpolation method.In time
It inserts on the basis of be the base in low resolution, technology when obtaining a kind of high-resolution survey.
Temporally interpolated Measurement Resolution is smaller than time base period, as shown in Fig. 2, start signals are in T1Moment, which opens, to be counted
Device, stop count signals are in T2Moment stops counter, and start signals are along logical with time interval △ T of the stop signals between
Oversampling clock is that the counter of clk measures counting, wherein TclkFor the period of reference clock signal CLK_IN, n is counter number
Value.△T1It is tested time interval between event signal rising edge and time-base signal rising edge, △ T2It is event signal failing edge
With the time interval between time-base signal rising edge, △ T1With △ T2It is temporally interpolated measurement object.It, can by temporal interpolation
With by △ T1With △ T2These tiny time intervals for being less than time base period further quantify.
The middle and lower parts Fig. 2 are △ T1With △ T2Enlarged diagram, arrow represents the scale that further quantifies.Due to Shi Jixin
Number period is known fixed value, can reach same interpolation results to the measurement of two kinds of different measurement objects.The present invention uses
Temporal interpolation method be clock phase-splitting method.
Clock phase-splitting technology refers to that multiple phases of clock cycle are all used to reach higher time resolution,
It is widely used in high-speed digital system design.Under certain measuring environments, after meeting certain measurement accuracy, it is contemplated that system
The factors such as structure, resource consumption, measurement period realize that the TDC based on FPGA is a kind of choosing well using clock phase-splitting technology
Select scheme.
Fig. 3 is part of data acquisition overall construction drawing, and key component is the intermediate TDC methods based on FPGA.In this method
In, the rising edge of input signal is time signal to be measured, and the thick time measures using synchronous parallel counter method structure, and resolution ratio is
System clock CLK_sys periods, and the thick time measuring unit in multiple channels.Fine measurement unit includes being based on multi-phase clock
Temporal interpolation time sampling unit, data buffer unit and coding unit.
The model for the chip that the present invention uses is the EP4SGX230KF40C2 of Stratix IV series, and inside is utilized
Integrated group phaselocked loop (PLL) realizes multi-phase clock circuit, thus obtains higher time measurement resolution.Stratix IV devices
In special global clock network (GCLK), local clock network (RCLK) and peripheral clock network (PCLK) constitute with layer
The clock architecture of secondary structure, this structure provides up to 236 single clock domains (16GCLK+88RCLK+132PCLK), and
Support up to 71 single GCLK, RCLK and PCLK clock sources (16GCLK+22RCLK+33PCLK) in each device quadrant.
Table 1 lists the available clock sources in StratixIV devices.
Clock sources in 1 Stratix IV devices of table
StratixIV devices provide up to 16 GCLK, these clocks can drive the function mould of entire device inside
Block (for example, adaptive logic module (ALM), Digital Signal Processing (DSP) module, TriMatrix memory modules and
PLL), the clock sources of low offset are provided.StratixIV device I/O units (IOE) can be by driving GCLK with internal logic
Come create internal generation global clock and it is other it is high be fanned out to control signal, such as：It either synchronously or asynchronously resets and the enabled letter of clock
Number.
Measured signal selection is transmitted via global clock line, it is made to reach each collection point as close possible to simultaneously, so as to
The realization of clock phase-splitting interpolation.
As shown in figure 5, being data transfer path of the clock edge as trigger signal, while utilizing TimeQuest
Timing Analyzer analyze the delay time of each measuring route, using TimeQuest Timing Analyzer to special
Transmission path carry out temporal constraint so that the delay time of adjacent data transfer path is as identical as possible.
" thin " survey part is divided into the rising edge of measured signal and failing edge two parts carry out temporal constraint respectively, according to preceding
The measurement result in face chooses suitable delay time respectively to each path progress temporal constraint.
Logical locking is carried out in Chip Planner with the module that LogicLock completes temporal constraint, to the greatest extent may be used
Energy ground enables later programmed to inherit the path delay that front has constrained.
After the realization for completing " thin " survey part, it is also necessary to be partially integrated into " thick " survey part and " thin " survey together, tool is such as
Shown in Fig. 6.
It loads the program into DE4 development boards (model of chip is the EP4SGX230KF40C2 of Stratix IV series),
Measured signal (square wave, frequency 120MHz) is generated by function generator Agilent 33220A, is carried out using Signal Tap
" thin " the actual measurement output waveform for surveying part of observation, detects its attainable resolution ratio, as shown in Figure 7.
Experimental data surveys part, and 5 groups of different time intervals has been taken to measure, 20 data of every group of survey, 5 groups of times
Interval is preset as 100ns, 200ns, 500ns, 1000ns, 1500ns respectively.
It is about 165ps to obtain its resolution ratio according to experimental measurements.The small error amount that time interval is preset as 100ns is
211ps (measurement result relative to oscillograph)；The minimum error values that time interval is preset as 200ns are 274ps (relative to showing
The measurement result of wave device)；The minimum error values that time interval is preset as 500ns are 310ps (the measurement knots relative to oscillograph
Fruit)；The minimum error values that time interval is preset as 1000ns are 257ps (measurement result relative to oscillograph)；Time interval
The minimum error values for being preset as 1500ns are 312ps (measurement result relative to oscillograph).
The clock of 100MHz inputs, and frequency is 6080MHz when the equivalent survey reached, effectively raises time measurement resolution.
Claims (3)
1. the clock phase-splitting method of phase-locked loop clock edging trigger, which is characterized in that detailed process is：
Step 1, the input terminal that clock signal 100MHz is input to phaselocked loop；
Step 2, by clock signal 100MHz frequencys multiplication to 315MHz, the high level section of input clock is subjected to eight phase shifts, phase shift
Angle CLK [0]~CLK [7] is respectively set as 0 °, 22.5 °, 45 °, 66.5 °, 90 °, 112.5 °, 135 °, 157.5 °；
Step 3, using the edge of eight tunnel clock signals of frequency multiplication of phase locked loop phase shift Hou as 16 trigger signals；
Measured signal is carried out clock synchronization process by step 4；
Step 5 carries out temporal constraint respectively to clock signal and every transmission paths of measured signal；
Step 6 judges that in measured signal level Count [0]~Count [15] of 16 triggering moments be 0 or 1, will
Occur 0 → 1 saltus step in Count [0]~Count [15] and the position of 1 → 0 saltus step extracts；
Step 7 records measured signal rising edge detection function with event_up_reg [n] or event_down_reg [n]
Rising edge/failing edge of event_up [n] or measured signal failing edge detection function event_down [n], when in measured signal
When there is rising edge along detection function event_up [n] or measured signal failing edge detection function event_down [n] in liter
Event_up_reg [n] or event_down_reg [n] exports high level, otherwise event_up_reg [n] or event_down_
Reg [n] exports low level；
Step 8 obtains the relative position of measured signal rising edge or failing edge in a clock cycle 315MHz, completes clock
Split-phase.
2. the clock phase-splitting method of phase-locked loop clock edging trigger according to claim 1, which is characterized in that described in step 3
The edge of eight tunnel clock signals includes the rising edge and failing edge of eight tunnel clock signals.
3. the clock phase-splitting method of phase-locked loop clock edging trigger according to claim 1, which is characterized in that will described in step 5
Occurring the method that the position of 0 → 1 saltus step and 1 → 0 saltus step extracts in Count [0]~Count [15] is：
Count [n] and Count [n+1] are calculated：
Appearance event_up [n]=(it is the position of 0 → 1 saltus step when~Count [n]) &Count [n+1]；
Appearance event_down [n]=(it is the position of 1 → 0 saltus step when~Count [n+1]) &Count [n]；
Wherein, n=0,1 ..., 15.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109857014A (en) * | 2019-01-24 | 2019-06-07 | 武汉精能电子技术有限公司 | A kind of pwm signal generation method based on FPGA |
| CN112019287A (en) * | 2019-05-30 | 2020-12-01 | 深圳市合讯电子有限公司 | Method for improving clock phase measurement precision |
| CN113711057A (en) * | 2019-02-12 | 2021-11-26 | 特克特朗尼克公司 | System and method for synchronizing a plurality of test and measurement instruments |
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