CN105187053A

CN105187053A - Metastable state eliminating circuit used for TDC

Info

Publication number: CN105187053A
Application number: CN201510562858.1A
Authority: CN
Inventors: 甄少伟; 刘俐宏; 尤帅; 艾国润; 罗萍; 贺雅娟; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2015-09-07
Filing date: 2015-09-07
Publication date: 2015-12-23
Anticipated expiration: 2035-09-07
Also published as: CN105187053B

Abstract

The invention belongs to the technical field of electronic circuits, and specifically relates to a metastable state eliminating circuit used for a TDC. The main structure of the metastable state eliminating circuit is composed of a first rising edge D trigger, a second rising edge D trigger, a third rising edge D trigger, a first falling edge D trigger and a second falling edge D trigger, wherein a D input end of the first rising edge D trigger and a D input end of the first falling edge D trigger are connected with external input signals; a Q output end of the second rising edge D trigger is connected with a clock signal input end of the third rising edge D trigger; and a Q output end of the second falling edge D trigger is connected with a D input end of the third rising edge D trigger. The metastable state eliminating circuit has the beneficial effects of being capable of effectively eliminating timing error caused by metastable state while ensuring that the result after time digital quantification and the traditional TDC have the same measuring range and resolution, and greatly improves reliability of TDC precision.

Description

A kind of metastable state for TDC eliminates circuit

Technical field

The invention belongs to electronic circuit technology field, relate to a kind of metastable state for TDC specifically and eliminate circuit.

Background technology

Time interval measurement technology has a large amount of application in a lot of field.It not only, in Atomic Physics, laser ranging, positioning timing etc., also has a wide range of applications in time interval measurement technology, automatic checkout equipment field; In addition, in national defense industry, time interval measurement is as a kind of important discriminating and detection means, very strict to the requirement of precision, even reaches picosecond magnitude.Therefore, high-precision TDC circuit has important effect.

Typical digital time converter adopts DLL sum counter two-layer configuration to quantize the time.Its basic thought to measure between start signal rising edge and stop signal rising edge during this period of time by clock count, and the range of TDC determines primarily of rolling counters forward scope, and resolution depends on DLL.The typical TDC circuit diagram based on this thought is as a Fig. 1, and its sequential chart is as Fig. 2, and thick value counter realizes nT _clktiming; Latch coding module and realize Δ T _startwith Δ T _stoptwo-part timing; Data processing module 8 outputs obtained of being sampled by DLL are carried out encoding and calculate the difference ε=Δ T of two clocking portions _stop-Δ T _start, then give thick value counting module a carry signal c according to difference.Data processing module exports with thick value counter module two parts timing and becomes Δ T change-over time, is the time interval between start and the stop signal rising edge that will measure.Δ T=nT can be obtained by Fig. 2 _clk-Δ T _start+ Δ T _stop, wherein T _clkfor the clock cycle, Δ T _startwith Δ T _stopfor the time measurement error started and terminate, n is the count value of Δ T inside counting device.Between clocking to numeral transformed error be ε=Δ T _stop-Δ T _start, Δ T=nT can be obtained _clk+ ε.

Fig. 3 is the circuit diagram of DLL, and ideally, clock is divided into 8 phase places by DLL, and to each output phase sample when start signal arrives, its sequential chart is as Fig. 4.In fact because the reasons such as duty ratio distortion, signal jitter, delay distortion have deviation, may there is metastable state in particular sample position in start.As shown in Figure 1, Δ T _startcalculating only relevant with the rising edge of d [7:0], so the position of d [7:0] signal rising edge when considering that start signal arrives.1. 4. be 2. a pair sampling location, be 3. that another is to sampling location.

Due to sampling time d type flip flop exist set up and the retention time, 1. 2. position time, start to d [7:0] sampling, due to the state that d [7] is in upset, likely there is metastable state, cause sampled result mistake.Thus Δ T _startlikely from T _clkto the saltus step of 0ns; Or contrary, likely from 0ns to T _clksaltus step, cause the counting of TDC to occur very large deviation.

Start, when 3. 4. sample to d [7:0] in position, because d [2] is in the state of upset, although also may generating metastable, can sample correct value, so Δ T at d [1] and d [3] place _startonly have the error of a phase place, negligible.

Summary of the invention

To be solved by this invention, be exactly for the problems referred to above, propose a kind of metastable state for TDC and eliminate circuit.

For achieving the above object, the present invention adopts following technical scheme:

Metastable state for TDC eliminates a circuit, and this circuit is made up of the first rising edge d type flip flop, the second rising edge d type flip flop, the 3rd rising edge d type flip flop, the first trailing edge d type flip flop and the second trailing edge d type flip flop;

The D of described first rising edge d type flip flop inputs termination external input signal, and its clock signal input terminal connects external timing signal, and its Q exports the D output of termination second rising edge d type flip flop; The clock signal input terminal of the second rising edge d type flip flop connects external timing signal, and its Q exports the clock signal input terminal of termination the 3rd rising edge d type flip flop; The D of the first trailing edge trigger inputs termination external input signal t, and its clock signal input terminal connects external timing signal, and its Q exports the D input of termination second trailing edge d type flip flop; The clock signal input terminal of the second trailing edge d type flip flop connects external timing signal, and its Q exports the D input of termination the 3rd rising edge d type flip flop; Described first rising edge d type flip flop, the second rising edge d type flip flop, the first trailing edge d type flip flop are connected identical external timing signal with the second trailing edge d type flip flop; The Q output of the 3rd rising edge flip-flops is the output that metastable state eliminates circuit.

Beneficial effect of the present invention is, while the result after ensureing time figure quantification has identical range and resolution with traditional TDC, effectively can eliminate the timing error that metastable state produces, greatly improve the reliability of TDC precision.

Accompanying drawing explanation

Fig. 1 typical case TDC circuit structure;

Fig. 2 is typical time period digital translation principle sequential chart;

Fig. 3 is DLL function structure chart;

Fig. 4 is that metastable position view may appear in start particular sample;

Fig. 5 is the logical construction schematic diagram that metastable state of the present invention eliminates circuit;

Fig. 6 is the application drawing that metastable state of the present invention eliminates circuit;

The sequential chart of Fig. 7 to be circuit of the present invention in sampling location be 1. position in Fig. 4;

The sequential chart of Fig. 8 to be circuit of the present invention in sampling location be 2. position in Fig. 4;

Fig. 9 is containing the counter portion sequential chart of the TDC of structure of the present invention;

Figure 10 is traditional TDC linearity schematic diagram;

Figure 11 is the TDC linearity schematic diagram adopting circuit structure of the present invention.

Embodiment

Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:

The present invention is the timing error that when eliminating traditional TDC employing DLL sum counter quantization time interval, metastable state situation produces, and with the addition of metastable state and eliminates logical circuit.The TDC eliminated after metastable state is the same with typical TDC precision, unique difference is, when start Fig. 4 1. 2. position sampling time, typical TDC probably can not correctly sample, making quantized result have the deviation of a clock cycle compared with correct result, is very serious deviation.And the quantized result increasing the circuit DLL after can not correctly sampling after metastable state elimination logic has the deviation of a clock cycle, also counter signal start_clk can be given simultaneously, counting n is made also to produce deviation 1, as shown in Figure 9, wherein start_clk is the signal that start produces after edge synchronization; Stop_clk is the signal that stop produces after edge synchronization; Start_stop is the signal that start_clk and stop_clk produces after enable module, as the enable signal of counter; Clk_dealy is the signal of clk through postponing; Gated_clk_delay is that start_stop and clk_dealy inputs and signal behind the door, as the count signal of counter through two.Due to, the n that the sampling of start metastable state produces and Δ T _starttwo parts quantization error counteracts, thus achieves start and to sample metastable elimination.

Structure of the present invention as shown in Figure 5, wherein start_clk is the signal that start produces after rising edge synch, the start_nclk signal that to be start produce after trailing edge is synchronous, Q_nclk be clock falling edge to start sampled output signal, exporting s_out is circuit judges result.

As shown in Figure 5, this circuit is made up of the first rising edge d type flip flop, the second rising edge d type flip flop, the 3rd rising edge d type flip flop, the first trailing edge d type flip flop and the second trailing edge d type flip flop structure of the present invention; The D of described first rising edge d type flip flop inputs termination external input signal, and its clock signal input terminal connects external timing signal, and its Q exports the D output of termination second rising edge d type flip flop; The clock signal input terminal of the second rising edge d type flip flop connects external timing signal, and its Q exports the clock signal input terminal of termination the 3rd rising edge d type flip flop; The D of the first trailing edge trigger inputs termination external input signal t, and its clock signal input terminal connects external timing signal, and its Q exports the D input of termination second trailing edge d type flip flop; The clock signal input terminal of the second trailing edge d type flip flop connects external timing signal, and its Q exports the D input of termination the 3rd rising edge d type flip flop; Described first rising edge d type flip flop, the second rising edge d type flip flop, the first trailing edge d type flip flop are connected identical external timing signal with the second trailing edge d type flip flop; The Q output of the 3rd rising edge flip-flops is the output that metastable state eliminates circuit.

The operation principle of this example is:

1. or 2. as shown in Figure 4, during in sampling location, there will not be the situation of d [x:x-1]=01 (x=6 ~ 1).1. or 2. then in Fig. 6, sampling location judge module is distinguished external input signal start (or stop) thus and whether is occurred that sampling location in the diagram.1. or 2. when judging sampling location, encoder adopts metastable state to eliminate the result coding of the output signal s_out of circuit, namely works as s_out=0, Δ T _startassignment is T _clk; S_out=1, Δ T _startassignment is 0ns.Otherwise encoder normal encoding, does not affect by s_out.

When 1. start samples d [7:0] in Fig. 4 position, metastable state eliminates its sequential chart of logic as Fig. 7, if external input signal start and external timing signal clk signal interval do not meet d type flip flop settling time, namely can not sample, the timing error of start_clk signal, if it is start_clk_wrong, now rolling counters forward result can reduce a T as shown in Figure 9 _clk.Start_clk_wrong sampling start_nclk obtains signal s_out_wrong=1, this seasonal Δ T _startfor 0ns, more correctly during sampling s_out=0, Δ T _startreduce T _clk.In conjunction with Δ T=nT _clk-Δ T _start+ Δ T _stopΔ T can be found _startthe error produced is by nT _clkbe eliminated after place's adjustment.

When 2. start samples d [7:0] in Fig. 4 position, metastable state eliminates its sequential chart of logic as Fig. 8, if start and clk signal interval does not meet d type flip flop settling time, namely can not sample, the timing error of start_clk signal, if it is start_clk_wrong, now rolling counters forward result can increase a T as shown in Figure 9 _clk.Start_clk_wrong sampling start_nclk obtains signal s_out_wrong=1, this seasonal Δ T _startfor T _clk, more correctly during sampling s_out=0, Δ T _startadd T _clk.In conjunction with Δ T=nT _clk-Δ T _start+ Δ T _stopΔ T can be found _startthe error produced is by nT _clkbe eliminated after place's adjustment.

In like manner: Δ T _stopthe error produced also can be eliminated, thus eliminates due to the metastable timing error occurring causing.

As shown in Figure 10 and Figure 11, compare typical TDC, the TDC linearity that the band that the present invention proposes can eliminate metastable state circuit is better, greatly improves the reliability of time quantization result.

Claims

1. the metastable state for TDC eliminates a circuit, and this circuit is made up of the first rising edge d type flip flop, the second rising edge d type flip flop, the 3rd rising edge d type flip flop, the first trailing edge d type flip flop and the second trailing edge d type flip flop;