CN203301440U - Single-double-conversion duty cycle-adjustable circuit - Google Patents
Single-double-conversion duty cycle-adjustable circuit Download PDFInfo
- Publication number
- CN203301440U CN203301440U CN2013203522729U CN201320352272U CN203301440U CN 203301440 U CN203301440 U CN 203301440U CN 2013203522729 U CN2013203522729 U CN 2013203522729U CN 201320352272 U CN201320352272 U CN 201320352272U CN 203301440 U CN203301440 U CN 203301440U
- Authority
- CN
- China
- Prior art keywords
- differential pair
- pair tube
- resistance
- drain electrode
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
The utility model relates to a single-double-conversion duty cycle-adjustable circuit. The single-double-conversion duty cycle-adjustable circuit comprises first differential transistor pair M1, second differential transistor pair M2 and a proportion inversing transistor M3; the grid of the first differential transistor pair M1 is connected with input signals; the drain of the first differential transistor pair M1 is connected with the grid of the second differential transistor pair M2 through a blocking capacitor; the drain of the second differential transistor pair M2 and the drain of the first differential transistor pair M1 are differential output ends; the source of the first differential transistor pair M1 and the source of the second differential transistor pair M2 are connected with a current source; the grid of the proportion inversing transistor M3 is connected with power source voltage; the drain of the proportion inversing transistor M3 is connected with the grid of the second differential transistor pair M2; and the source of the proportion inversing transistor M3 is connected with the middle point of a voltage-dividing circuit composed of an R1 and an R2. The single-double-conversion duty cycle-adjustable circuit of the utility model can realize differential output and simple adjustment structure of duty cycle simultaneously through a single-double-conversion circuit, and can adjust the duty cycle of output waveform to be 50% through setting the values of the R1 and R2.
Description
Technical field
The utility model relates to a kind of difference channel, particularly relates to and singly turns two duty ratio conditioned circuits.
Background technology
In communication system, in order to improve the noise resistivity, the radio-frequency (RF) front-end circuit of receiver generally can adopt differential configuration, and single-ended signal transfers differential signal to by the single-ended transfer difference device.As described in number of patent application 2012100461973, the single-ended double end converter that turns, it comprises the first transistor, transistor seconds and voltage transformation unit, this voltage transformation unit comprises the first inductance element, the second inductance element and the 3rd inductance element, the first inductance element and the 3rd inductance element carry out the first coupling according to the first mutual coupling parameter, and the second inductance element and the 3rd inductance element carry out the second coupling according to the second mutual coupling parameter.
Yet, in the radio-frequency front-end application, adopt the pre-divider of TSPC structure, if as frequency division by odd integers, the signal dutyfactor that pre-divider produces is not 50%, and is Single-end output.After simple single-ended transfer difference device, can not revise duty ratio.When the input signal duty ratio of frequency mixer is not 50%, can produce local oscillator leakage, the problems such as noise increase.
The utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, and it is the two duty ratio conditioned circuits of singly turning of 50% differential signal that a kind of duty ratio simple in structure, exportable is provided.
The purpose of this utility model is achieved through the following technical solutions: singly turn two duty ratio conditioned circuits, it comprises the first differential pair tube M1, the second differential pair tube M2 and an inverse ratio pipe M3, the grid of the first differential pair tube M1 connects input signal, the drain electrode of the first differential pair tube M1 connects the grid of the second differential pair tube M2 by capacitance, the drain electrode of the drain electrode of the second differential pair tube M2 and the first difference M1 is difference output end, and the source electrode of the source electrode of the first differential pair tube M1 and the second differential pair tube M2 all is connected current source; The grid of inverse ratio pipe M3 connects supply voltage, and the drain electrode of inverse ratio pipe M3 is connected with the grid of the second differential pair tube M2, and the source electrode of inverse ratio pipe M3 is connected with the mid point of the bleeder circuit that is comprised of R1, R2.
Further, between the drain electrode of the drain electrode of described the first differential pair tube M1 and the second differential pair tube M2 and supply voltage, also be provided with filter capacitor C2, filter capacitor C2 is connected with the drain electrode of the first differential pair tube M1 by resistance R 5, and filter capacitor C2 also is connected with the drain electrode of the second differential pair tube M2 by resistance R 4.Resistance R 4 is identical with the resistance of resistance R 5, and resistance R 4 and resistance R 5 are be used to adjusting the amplitude of oscillation of output voltage.
Further, between the drain electrode of the drain electrode of described the first differential pair tube M1 and the second differential pair tube M2 and supply voltage, also be provided with resistance R 3, resistance R 3 is be used to adjusting the common-mode point of output voltage, resistance R 3 is connected with the drain electrode of the first differential pair tube M1 by resistance R 5, and resistance R 3 also is connected with the drain electrode of the second differential pair tube M2 by resistance R 4.
Further, described inverse ratio pipe M3 is NMOS inverse ratio pipe.
The beneficial effects of the utility model are:
(1) by singly turning double circuit, just can realize simultaneously the adjusting of duty ratio, without the extra duty ratio adjusting circuit that increases, simple in structure;
(2), by the meticulous value that divider resistance R1 and divider resistance R2 are set, change the common mode electrical level of the first differential pair tube and the second differential pair tube, and then the duty ratio of adjustment output waveform is 50%.
The accompanying drawing explanation
Fig. 1 is circuit theory diagrams of the present utility model;
Fig. 2 is the input waveform of the utility model the first differential pair tube and the second differential pair tube;
In figure, V
X1And V
X2For the input of the second differential pair tube under different situations, V
InInput signal for circuit.
Embodiment
Below in conjunction with accompanying drawing, the technical solution of the utility model is described in further detail, but protection range of the present utility model is not limited to the following stated.
As shown in Figure 1, singly turn two duty ratio conditioned circuits, it comprises the first differential pair tube M1, the second differential pair tube M2 and an inverse ratio pipe M3, the grid of the first differential pair tube M1 connects input signal Vin, the drain electrode of the first differential pair tube M1 connects the grid of the second differential pair tube M2 by capacitance C1, the drain electrode of the drain electrode of the second differential pair tube M2 and the first differential pair tube M1 is difference output end, and the source electrode of the source electrode of the first differential pair tube M1 and the second differential pair tube M2 all is connected current source.The grid of inverse ratio pipe M3 connects supply voltage VDD, and the drain electrode of inverse ratio pipe M3 is connected with the grid of the second differential pair tube M2, and the source electrode of inverse ratio pipe M3 is connected with the mid point of the bleeder circuit that is comprised of R1, R2.
Further, between the drain electrode of the drain electrode of described the first differential pair tube M1 and the second differential pair tube M2 and supply voltage, also be provided with filter capacitor C2, filter capacitor C2 is connected with the drain electrode of the first differential pair tube M1 by resistance R 5, and filter capacitor C2 also is connected with the drain electrode of the second differential pair tube M2 by resistance R 4.Resistance R 4 is identical with the resistance of resistance R 5, and resistance R 4 and resistance R 5 are be used to adjusting the amplitude of oscillation of output voltage.
Further, between the drain electrode of the drain electrode of described the first differential pair tube M1 and the second differential pair tube M2 and supply voltage, also be provided with resistance R 3, resistance R 3 is be used to adjusting the common-mode point of output voltage, resistance R 3 is connected with the drain electrode of the first differential pair tube M1 by resistance R 5, and resistance R 3 also is connected with the drain electrode of the second differential pair tube M2 by resistance R 4.
Further, described inverse ratio pipe M3 is NMOS inverse ratio pipe.
Operation principle of the present utility model is as follows: the single-ended input signal V of M1
In, by capacitance C1, make M1 drain electrode output signal feed back to the grid of M2, completing circuit singly turn difunctional.The size of adjusting capacitor C 1 can be controlled the amplitude of feedback voltage, so that the output difference sub-signal amplitude of oscillation is identical.By the ratio of divider resistance R1 and divider resistance R2 is set, change the dividing potential drop size on divider resistance R2, determine the common mode electrical level of two differential pair tube inputs.M3 is NMOS inverse ratio pipe, serves as the role of large resistance, plays the effect that cuts off feedback signal.By resistance R 3 and regulating resistor R4& are set; R5 can adjust maximum level and the amplitude of oscillation of output voltage, and C2 is filter capacitor.
M1 and M2 input waveform is as shown in Figure 2: the output of completely putting signal and be the TSPC frequency divider is the input signal V of circuit
In.Two amplitudes are than small-signal V
X1And V
X2Input for M2 under different situations.Due to various ghost effects being arranged in actual domain, cause the output waveform of TSPC frequency divider that certain rising and falling time is arranged, at different common mode electrical level places, the duty ratio of waveform can make a big difference, utilize this point, can by the meticulous R1 of setting of post-simulation and R2, change the common mode electrical level of M1 and M2, make the output waveform duty ratio be adjusted into 50%.For example, in the duty ratio of common mode electrical level VCM1 place differential signal, be just 50%, and the duty ratio of common mode electrical level VCM2 place output difference sub-signal just can not meet the application needs.
Claims (4)
1. singly turn two duty ratio conditioned circuits, it is characterized in that: it comprises the first differential pair tube M1, the second differential pair tube M2 and an inverse ratio pipe M3, the grid of the first differential pair tube M1 connects input signal, the drain electrode of the first differential pair tube M1 connects the grid of the second differential pair tube M2 by capacitance, the drain electrode of the drain electrode of the second differential pair tube M2 and the first differential pair tube M1 is difference output end, and the source electrode of the source electrode of the first differential pair tube M1 and the second differential pair tube M2 all is connected current source; The grid of inverse ratio pipe M3 connects supply voltage, and the drain electrode of inverse ratio pipe M3 is connected with the grid of the second differential pair tube M2, and the source electrode of inverse ratio pipe M3 is connected with the mid point of the bleeder circuit that is comprised of R1, R2.
2. according to claim 1ly singly turn two duty ratio conditioned circuits, it is characterized in that: between the drain electrode of the drain electrode of described the first differential pair tube M1 and the second differential pair tube M2 and supply voltage, also be provided with filter capacitor C2, filter capacitor C2 is connected with the drain electrode of the first differential pair tube M1 by resistance R 5, filter capacitor C2 also is connected with the drain electrode of the second differential pair tube M2 by resistance R 4, resistance R 4 is identical with the resistance of resistance R 5, and resistance R 4 and resistance R 5 are be used to adjusting the amplitude of oscillation of output voltage.
3. according to claim 1ly singly turn two duty ratio conditioned circuits, it is characterized in that: between the drain electrode of the drain electrode of described the first differential pair tube M1 and the second differential pair tube M2 and supply voltage, also be provided with resistance R 3, resistance R 3 is be used to adjusting the common-mode point of output voltage, resistance R 3 is connected with the drain electrode of the first differential pair tube M1 by resistance R 5, and resistance R 3 also is connected with the drain electrode of the second differential pair tube M2 by resistance R 4.
4. according to claim 1ly singly turn two duty ratio conditioned circuits, it is characterized in that: described inverse ratio pipe M3 is NMOS inverse ratio pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203522729U CN203301440U (en) | 2013-06-19 | 2013-06-19 | Single-double-conversion duty cycle-adjustable circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203522729U CN203301440U (en) | 2013-06-19 | 2013-06-19 | Single-double-conversion duty cycle-adjustable circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203301440U true CN203301440U (en) | 2013-11-20 |
Family
ID=49577420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013203522729U Expired - Fee Related CN203301440U (en) | 2013-06-19 | 2013-06-19 | Single-double-conversion duty cycle-adjustable circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203301440U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104635826A (en) * | 2014-12-12 | 2015-05-20 | 长沙景嘉微电子股份有限公司 | Simple linear power supply circuit |
-
2013
- 2013-06-19 CN CN2013203522729U patent/CN203301440U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104635826A (en) * | 2014-12-12 | 2015-05-20 | 长沙景嘉微电子股份有限公司 | Simple linear power supply circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103095217A (en) | Low phase noise voltage-controlled oscillator | |
| CN102323848A (en) | Band-gap reference circuit capable of eliminating offset influence by chopping technology | |
| CN106257835B (en) | A kind of 25% duty cycle clock signal generation circuit | |
| CN104158496A (en) | Passive frequency mixer at duty ratio of 25% with positive feedback transimpedance amplification stage as load | |
| CN201869094U (en) | Voltage-stabilizing circuit based on MOS tube | |
| CN104953981A (en) | Gain enhancement type N-channel active band-pass filter adopting differential clock | |
| CN203301440U (en) | Single-double-conversion duty cycle-adjustable circuit | |
| CN204013481U (en) | Realize the circuit structure that low-voltage crystal oscillator drives | |
| CN103248226A (en) | Switching power supply controller of average current lagging mode | |
| CN104348431A (en) | Common-mode feedback differential amplification circuit, method and integrated circuit | |
| CN203660873U (en) | Circuit for eliminating low-frequency oscillation of output ripples of high-voltage power supply | |
| CN204539097U (en) | A kind of noise reduction filtering circuit for pi type filter and a kind of pi type filter | |
| CN104242875B (en) | Single turn of double dutycycle conditioned circuit | |
| CN204156738U (en) | A kind of power supply and control circuit thereof | |
| CN104218892A (en) | Multiple-frequency crystal oscillation circuit | |
| CN104133518A (en) | Anti-interference current mirror image circuit | |
| CN204669326U (en) | Differential clocks gain-boost N channel active band-pass filter | |
| CN203423670U (en) | Variable-gain analog adder | |
| CN102164103B (en) | Programmable differential continuous-time pre-emphasis driver | |
| CN205490422U (en) | Be fit for harmonious voltage controlled oscillator in broadband | |
| CN204216879U (en) | A kind of cmos vco | |
| CN204993303U (en) | VCO circuit of high performance of making an uproar mutually | |
| CN204103896U (en) | A kind of ring oscillator | |
| CN104426540A (en) | VCO device generating balanced duty ratio signals | |
| CN204681318U (en) | A kind of voltage transitions is the mutual conductance amplifying circuit of electric current |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: CHENGDU ZHENXIN TECHNOLOGY CO., LTD. Free format text: FORMER NAME: CHENGDU ARTEC ELECTRONICS CORP. |
|
| CP03 | Change of name, title or address |
Address after: No. 1 high tech Zone Gaopeng road in Chengdu city of Sichuan Province in 610000 Patentee after: CHENGDU CORPRO TECHNOLOGY CO., LTD. Address before: No. 1 high tech Zone Gaopeng road in Chengdu city of Sichuan Province in 610041 Patentee before: Chengdu ARTEC Electronics Corp. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131120 Termination date: 20190619 |