CN203135824U - A power on reset circuit containing a global enabling pulse control automatic reset function - Google Patents
A power on reset circuit containing a global enabling pulse control automatic reset function Download PDFInfo
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- CN203135824U CN203135824U CN 201320040221 CN201320040221U CN203135824U CN 203135824 U CN203135824 U CN 203135824U CN 201320040221 CN201320040221 CN 201320040221 CN 201320040221 U CN201320040221 U CN 201320040221U CN 203135824 U CN203135824 U CN 203135824U
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Abstract
The utility model discloses a power on reset circuit containing a global enabling pulse control automatic reset function. The power on reset circuit comprises a voltage dividing module, a level detecting module, a quick response module, a time delay module, a reset pulse signal generating module, and a wave shaping module. The input end of the voltage dividing module is connected with an external enable pulse signal, while the output end of the voltage dividing module is connected with the input end of the level detecting module and the output end of the quick response module. The output end of the level detecting module is connected with the input end of the quick response module and the input end of the time delay module. The output end of the time delay module is connected with the input end of the reset pulse signal generating module. The output end of the reset pulse signal generating module is connected with the input end of the wave shaping module. The voltage on the output end of the wave shaping module is used as the output signal of the power on reset circuit. The power on reset circuit is capable of generating a reset pulse in a power on process of a power supply or under the control of a global reset pulse signal in order to reset a digital circuit and to be automatically started.
Description
Technical field
The utility model relates to a kind of electrify restoration circuit, relates in particular to a kind of electrify restoration circuit that has overall enabling pulse control auto-reset function, belongs to analog to digital composite signal integrated circuits design field.
Background technology
Along with the increase of level of integrated system and application demand, increasing digital module and analog module are embedded in the same chip, and the application of digital hybrid circuit also more and more widely.In extensive digital-to-analogue mixed signal design of integrated circuit; owing to have electronic circuit unit such as a large amount of registers, trigger in the chip; the state of these electronic circuit unit is uncertain when power supply begins to be added on the chip, and this can cause the entire chip misoperation or also will reconfigure register by sending instruction before operate as normal.Therefore, if can when chip power, after supply voltage reaches a certain value, provide the value that a reset signal refreshes register automatically, then can avoid system's misoperation or need the special time to dispose the situation of initial condition, electrify restoration circuit is exactly the element circuit of finishing this function specially.
When using the digital-to-analogue hybrid chip; the operation irregularity situation such as overflow when output valve occurring, perhaps the digital-to-analogue hybrid chip need be carried out initialization and proofreaied and correct, when perhaps having the park mode function; need carry out power down or reset processing to entire chip, restart this chip afterwards again.In this process, also need again some registers in the digital module to be reinitialized.But this moment, we wish to carry out resetting of digital module again after the analog module circuit all reaches stable quiescent point, and whole digital-to-analogue hybrid chip just can operate as normal resetting after like this, otherwise the situation that also may cause initialization to fail.
At present, generally be that electrify restoration circuit and whole chip reset circuit are designed respectively, when whole chip reset, need design circuit to satisfy certain time sequence, again the digital module register is resetted after making analog module reach stable operating point earlier, such shortcoming is the complexity that can increase circuit, causes the waste of chip area and power consumption.
Summary of the invention
The purpose of this utility model is to overcome and address the above problem, a kind of electrify restoration circuit that has overall enabling pulse control auto-reset function is provided, under the prerequisite of saving chip area and power consumption, make reset in the digital-to-analog composite signal integrated circuits more accurate.
For realizing above purpose, the technical solution of the utility model is as follows: a kind of electrify restoration circuit that has overall enabling pulse control auto-reset function, comprise division module, level detection module, quick respond module, time delay module, reseting pulse signal generation module and waveform-shaping module, the outside enabling pulse signal of the input termination of division module; The output of division module is connected with the input of level detection module, the output of quick respond module; The output of level detection module is connected with the input of quick respond module, the input of time delay module; The output of time delay module is connected with the input of reseting pulse signal generation module; The output of reseting pulse signal generation module is connected with the input of waveform-shaping module; The voltage of the output of waveform-shaping module is as the output signal of electrify restoration circuit, wherein: division module is for generation of the component of voltage relevant with supply voltage, it is controlled by external input signal, when external input signal was not worked division module, the final output level of division module output was lower than the upset level of testing circuit module; The level detection module is for detection of the output level of division module, according to the size of the output level of division module, at the different voltage signal of output output of level detection module; Quick respond module, be used for detect the division module output level greater than a certain fixed value after, make the output level fast rise of division module; Time delay module is used for adjusting the time interval between power up and the reseting pulse signal generation; The reseting pulse signal generation module for generation of the reset level pulse signal, resets after at certain time intervals and finishes, and reset pulse finishes;
Waveform-shaping module, the output voltage that the reseting pulse signal generation module is produced amplifies and shaping, and will amplify with shaping after voltage signal as the output signal of electrify restoration circuit.
Preferably:
Described voltage module circuit contains the P type metal-oxide-semiconductor M1 as switching tube, under the control of systematic reset signal division module is enabled control; P type metal-oxide-semiconductor M2, M3, M4, the M5 of 4 diode connections form bleeder circuit, and the voltage with mains voltage variations is provided; First resistance R 1 and first capacitor C 1 are formed filter circuit, and the final voltage output of division module is provided.The source electrode of P type metal-oxide-semiconductor M1 is connected with power supply; The grid of P type metal-oxide-semiconductor M1 is connected with systematic reset signal CTR; The source electrode of the drain electrode of P type metal-oxide-semiconductor M1 and P type metal-oxide-semiconductor M2 interconnects; The grid of P type metal-oxide-semiconductor M2, the source electrode of the drain electrode of P type metal-oxide-semiconductor M2 and P type metal-oxide-semiconductor M3 interconnects; The grid of P type metal-oxide-semiconductor M3, the source electrode of the drain electrode of P type metal-oxide-semiconductor M3, P type metal-oxide-semiconductor M4 and an end of first resistance R 1 interconnect; The grid of P type metal-oxide-semiconductor M4, the source electrode of the drain electrode of P type metal-oxide-semiconductor M4 and P type metal-oxide-semiconductor M5 interconnects; The grid of P type metal-oxide-semiconductor M5, the drain electrode of P type metal-oxide-semiconductor M5 with interconnect; One end of the other end of first resistance R 1, first capacitor C 1 and the output of division module interconnect; The other end of first capacitor C 1 is connected with ground.
Described level detection modular circuit contains P type metal-oxide-semiconductor M6, N-type metal-oxide-semiconductor M7, constitutes level sensitive circuit, by adjusting the suitable upset level of device size design of P type metal-oxide-semiconductor M6 and N-type metal-oxide-semiconductor M7; The first inverter INV1 is used to provide the opposite levels of signal, and the input and output signal of the first inverter INV1 is controlled the transmission gate in the quick respond module circuit simultaneously.The grid of the output of the input of level detection modular circuit, division module circuit, P type metal-oxide-semiconductor M6, the grid of N-type metal-oxide-semiconductor M7 interconnect with the output of quick respond module; The source electrode of P type metal-oxide-semiconductor M6 is connected with power supply; The drain electrode of P type metal-oxide-semiconductor M6, the drain electrode of N-type metal-oxide-semiconductor M7, the grid of P type metal-oxide-semiconductor M8 and the input of the first inverter INV1 interconnect; The source electrode of N-type metal-oxide-semiconductor M7 is connected with ground; The output of the output of the first inverter INV1 and level detection modular circuit interconnects.
Described quick respond module circuit contains as the P type metal-oxide-semiconductor M8 of switching tube with as the N-type metal-oxide-semiconductor M9 of switching tube, constitutes a transmission gate; Second capacitor C 2 is used for giving when the transmission gate conducting output of division module circuit that electric charge is provided, and accelerates the rising of the output end voltage of division module circuit.The drain electrode of P type metal-oxide-semiconductor M6, the drain electrode of N-type metal-oxide-semiconductor M7, the grid of P type metal-oxide-semiconductor M8 and the input of the first inverter INV1 interconnect; The grid of the output of the first inverter INV1, the input of time delay module and N-type metal-oxide-semiconductor M9 interconnects; One end of the source electrode of P type metal-oxide-semiconductor M8, the drain electrode of N-type metal-oxide-semiconductor M9 and second capacitor C 2 interconnects; The other end of second capacitor C 2 is connected with power supply; The drain electrode of the input of the output of division module circuit, level detection modular circuit, P type metal-oxide-semiconductor M8, the source electrode of N-type metal-oxide-semiconductor M9 interconnect with the output of quick respond module circuit.
Described time delay module circuit contains the second inverter INV2, the 3rd inverter INV3, is used for the anti-phase output of voltage; P type metal-oxide-semiconductor M10, N-type metal-oxide-semiconductor M11, P type metal-oxide-semiconductor M12, N-type metal-oxide-semiconductor M13, the 3rd capacitor C 3 and the 4th capacitor C 4 are for generation of the signal lag that is input to output.The input of the output of the input of time delay module circuit, level detection modular circuit and the second inverter INV2 interconnects; The grid of the output of the second inverter INV2, P type metal-oxide-semiconductor M10 and the grid of N-type metal-oxide-semiconductor M11 interconnect; The source electrode of P type metal-oxide-semiconductor M10 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M11 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M10, the drain electrode of N-type metal-oxide-semiconductor M11, the 3rd capacitor C 3, the grid of P type metal-oxide-semiconductor M12 and the grid of N-type metal-oxide-semiconductor M13 interconnect; The other end of the 3rd capacitor C 3 is connected with ground; The source electrode of P type metal-oxide-semiconductor M12 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M13 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M12, the drain electrode of N-type metal-oxide-semiconductor M13, an end of the 4th capacitor C 4 and the input of the 3rd inverter INV3 interconnect; The input of the output of the output of the 3rd inverter INV3, time delay module circuit and reseting pulse signal generation module circuit interconnects.
Described reseting pulse signal generation module circuit contains P type metal-oxide-semiconductor M14, N-type metal-oxide-semiconductor M15, P type metal-oxide-semiconductor M16, N-type metal-oxide-semiconductor M17, the 5th capacitor C 5 and the 6th capacitor C 6, for generation of the signal lag that is input to output; The 4th inverter INV4 is used for the anti-phase output of voltage; First liang of input nand gate NAND2 by the difference of input signal, produces reset pulse output.The input of the grid of the input of time delay module circuit output end, reseting pulse signal generation module circuit, P type metal-oxide-semiconductor M14, the grid of N-type metal-oxide-semiconductor M15 and first liang of input nand gate NAND2 interconnects; The source electrode of P type metal-oxide-semiconductor M14 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M15 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M14, the drain electrode of N-type metal-oxide-semiconductor M15, the 5th capacitor C 5, the grid of P type metal-oxide-semiconductor M16 and the grid of N-type metal-oxide-semiconductor M17 interconnect; The other end of the 5th capacitor C 5 is connected with ground; The source electrode of P type metal-oxide-semiconductor M16 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M17 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M16, the drain electrode of N-type metal-oxide-semiconductor M17, an end of the 6th capacitor C 6 and the input of the 4th inverter INV4 interconnect; The other end of the 6th capacitor C 6 is connected with ground; Another input of first liang of input nand gate NAND2 and the output of the 4th inverter INV4 interconnect; The input of the output of first liang of input nand gate NAND2 and waveform-shaping module circuit interconnects.
Described waveform-shaping module circuit contains the 5th inverter INV5 and hex inverter INV6, and input signal is amplified and shaping, and the electrification reset output signal is provided.The input of the output of reseting pulse signal generation module circuit, the input of waveform-shaping module circuit and the 5th inverter INV5 interconnects; The output of the 5th inverter INV5 and the input of hex inverter INV6 interconnect; The output RST of the output of hex inverter INV6 and electrify restoration circuit interconnects.
The concrete connected mode of above-mentioned whole electrify restoration circuit is as follows: the grid of P type metal-oxide-semiconductor M1 is connected with systematic reset signal CTR; The source electrode of the drain electrode of P type metal-oxide-semiconductor M1 and P type metal-oxide-semiconductor M2 interconnects; The grid of P type metal-oxide-semiconductor M2, the source electrode of the drain electrode of P type metal-oxide-semiconductor M2 and P type metal-oxide-semiconductor M3 interconnects; The grid of P type metal-oxide-semiconductor M3, the source electrode of the drain electrode of P type metal-oxide-semiconductor M3, P type metal-oxide-semiconductor M4 and an end of first resistance R 1 interconnect; The grid of P type metal-oxide-semiconductor M4, the source electrode of the drain electrode of P type metal-oxide-semiconductor M4 and P type metal-oxide-semiconductor M5 interconnects; The grid of P type metal-oxide-semiconductor M5, the drain electrode of P type metal-oxide-semiconductor M5 with interconnect; The drain electrode of the grid of one end of the other end of resistance R 1, first capacitor C 1, P type metal-oxide-semiconductor M6, the grid of N-type metal-oxide-semiconductor M7, P type metal-oxide-semiconductor M8 and the source electrode of N-type metal-oxide-semiconductor M9 interconnect; The other end of first capacitor C 1 is connected with ground; The source electrode of P type metal-oxide-semiconductor M6 is connected with power supply; The drain electrode of P type metal-oxide-semiconductor M6, the drain electrode of N-type metal-oxide-semiconductor M7, the grid of P type metal-oxide-semiconductor M8 and the input of the first inverter INV1 interconnect; The source electrode of N-type metal-oxide-semiconductor M7 is connected with ground; The grid of the input of the output of the first inverter INV1, the second inverter INV2 and N-type metal-oxide-semiconductor M9 interconnects; One end of the source electrode of P type metal-oxide-semiconductor M8, the drain electrode of N-type metal-oxide-semiconductor M9 and second capacitor C 2 interconnects; The other end of second capacitor C 2 is connected with power supply; The grid of the output of the second inverter INV2, P type metal-oxide-semiconductor M10 and the grid of N-type metal-oxide-semiconductor M11 interconnect; The source electrode of P type metal-oxide-semiconductor M10 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M11 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M10, the drain electrode of N-type metal-oxide-semiconductor M11, the 3rd capacitor C 3, the grid of P type metal-oxide-semiconductor M12 and the grid of N-type metal-oxide-semiconductor M13 interconnect; The other end of the 3rd capacitor C 3 is connected with ground; The source electrode of P type metal-oxide-semiconductor M12 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M13 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M12, the drain electrode of N-type metal-oxide-semiconductor M13, an end of the 4th capacitor C 4 and the input of the 3rd inverter INV3 interconnect; The input of the grid of the output of the 3rd inverter INV3, P type metal-oxide-semiconductor M14, the grid of N-type metal-oxide-semiconductor M15 and first liang of input nand gate NAND2 interconnects; The source electrode of P type metal-oxide-semiconductor M14 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M15 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M14, the drain electrode of N-type metal-oxide-semiconductor M15, the 5th capacitor C 5, the grid of P type metal-oxide-semiconductor M16 and the grid of N-type metal-oxide-semiconductor M17 interconnect; The other end of the 5th capacitor C 5 is connected with ground; The source electrode of P type metal-oxide-semiconductor M16 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M17 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M16, the drain electrode of N-type metal-oxide-semiconductor M17, an end of the 6th capacitor C 6 and the input of the 4th inverter INV4 interconnect; The other end of the 6th capacitor C 6 is connected with ground; Another input of first liang of input nand gate NAND2 and the output of the 4th inverter INV4 interconnect; The input of first liang of input nand gate NAND2 output and the 5th inverter INV5 interconnects; The output of the 5th inverter INV5 and the input of hex inverter INV6 interconnect; The output RST of the output of hex inverter INV6 and electrify restoration circuit interconnects.
Compared with prior art, the utlity model has following advantage and remarkable result:
Electrify restoration circuit in the utility model both can be realized the electrification reset function, also can be when the digital-to-analogue hybrid chip be carried out Global reset, and produce and allow the pulse signal of digital module circuit reset.Than alternate manner, saved total area and the power consumption of circuit;
Quick respond module circuit in the utility model can just reach the threshold voltage of the upset that resets at circuit, begins to produce the moment quickening electric capacity charging of reset signal, makes reset signal more precipitous;
Can regulate the resetting time of the electrify restoration circuit in the utility model by the metal-oxide-semiconductor in the reseting pulse signal generation module circuit and the value of electric capacity.
Description of drawings
Fig. 1 is the basic framework figure of electrify restoration circuit in the present embodiment;
Fig. 2 is the circuit structure diagram of electrify restoration circuit in the present embodiment.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing embodiment of the present utility model is described in further detail.
A kind of electrify restoration circuit that has overall enabling pulse control auto-reset function in the present embodiment, its basic framework figure as shown in Figure 1, comprise division module 1, level detection module 2, quick respond module 3, time delay module 4, reseting pulse signal generation module 5 and waveform-shaping module 6, the outside enabling pulse signal of the input termination of division module 1; The output of division module 1 is connected with the input of level detection module 2, the output of quick respond module 3; The output of level detection module 2 is connected with the input of quick respond module 3, the input of time delay module 4; The output of time delay module 4 is connected with the input of reseting pulse signal generation module 5; The output of reseting pulse signal generation module 5 is connected with the input of waveform-shaping module 6; The voltage of the output of waveform-shaping module 6 is as the output signal of electrify restoration circuit, wherein: division module 1 is for generation of the component of voltage relevant with supply voltage, it is controlled by external input signal, when external input signal was not worked division module 1, the final output level of division module 1 output was lower than the upset level of testing circuit module; Level detection module 2 is for detection of the output level of division module 1, according to the size of the output level of division module 1, at the different voltage signal of output output of level detection module 2; Quick respond module 3, be used for detect division module 1 output level greater than a certain fixed value after, make the output level fast rise of division module 1; Time delay module 4 is used for adjusting the time interval between power up and the reseting pulse signal generation; Reseting pulse signal generation module 5 for generation of the reset level pulse signal, resets after at certain time intervals and finishes, and reset pulse finishes; Waveform-shaping module 6, the output voltage that reseting pulse signal generation module 5 is produced amplifies and shaping, and will amplify with shaping after voltage signal as the output signal of electrify restoration circuit.Particular circuit configurations figure among the embodiment such as Fig. 2.Voltage module 1 is by P type metal-oxide-semiconductor M1,4 P type metal-oxide-semiconductor M2, M3, M4, M5 that diode connects, and resistance R 1 and capacitor C 1 constitute; Level detection module 2 is by P type metal-oxide-semiconductor M6, and N-type metal-oxide-semiconductor M7 and the first inverter INV1 constitute; Fast respond module 3 is by P type metal-oxide-semiconductor M8, N-type metal-oxide-semiconductor M9, and capacitor C 2 constitutes; Time delay module 4 is by the second inverter INV2, the 3rd inverter INV3, and P type metal-oxide-semiconductor M10, N-type metal-oxide-semiconductor M11, P type metal-oxide-semiconductor M12, N-type metal-oxide-semiconductor M13, capacitor C 3 and capacitor C 4 constitute; Reseting pulse signal generation module 5 is by P type metal-oxide-semiconductor M14, N-type metal-oxide-semiconductor M15, and P type metal-oxide-semiconductor M16, N-type metal-oxide-semiconductor M17, capacitor C 5, capacitor C 6, the four inverter INV4, first liang of input nand gate NAND2 constitutes.Waveform-shaping module 6 is by the 5th inverter INV5, and hex inverter INV6 constitutes.
On the whole, this circuit structure connects in the following manner: the grid of P type metal-oxide-semiconductor M1 is connected with systematic reset signal CTR; The source electrode of the drain electrode of P type metal-oxide-semiconductor M1 and P type metal-oxide-semiconductor M2 interconnects; The grid of P type metal-oxide-semiconductor M2, the source electrode of the drain electrode of P type metal-oxide-semiconductor M2 and P type metal-oxide-semiconductor M3 interconnects; The grid of P type metal-oxide-semiconductor M3, the source electrode of the drain electrode of P type metal-oxide-semiconductor M3, P type metal-oxide-semiconductor M4 and an end of first resistance R 1 interconnect; The grid of P type metal-oxide-semiconductor M4, the source electrode of the drain electrode of P type metal-oxide-semiconductor M4 and P type metal-oxide-semiconductor M5 interconnects; The grid of P type metal-oxide-semiconductor M5, the drain electrode of P type metal-oxide-semiconductor M5 with interconnect; The drain electrode of the grid of one end of the other end of resistance R 1, first capacitor C 1, P type metal-oxide-semiconductor M6, the grid of N-type metal-oxide-semiconductor M7, P type metal-oxide-semiconductor M8, source electrode and the terminal A of N-type metal-oxide-semiconductor M9 interconnect; The other end of first capacitor C 1 is connected with ground; The source electrode of P type metal-oxide-semiconductor M6 is connected with power supply; The grid of the drain electrode of P type metal-oxide-semiconductor M6, the drain electrode of N-type metal-oxide-semiconductor M7, P type metal-oxide-semiconductor M8, input and the end points CP of the first inverter INV1 interconnect; The source electrode of N-type metal-oxide-semiconductor M7 is connected with ground; Grid and the end points CN of the input of the output of the first inverter INV1, the second inverter INV2, N-type metal-oxide-semiconductor M9 interconnect; One end and the terminal B of the source electrode of P type metal-oxide-semiconductor M8, the drain electrode of N-type metal-oxide-semiconductor M9, second capacitor C 2 interconnect; The other end of second capacitor C 2 is connected with power supply; The grid of the output of the second inverter INV2, P type metal-oxide-semiconductor M10 and the grid of N-type metal-oxide-semiconductor M11 interconnect; The source electrode of P type metal-oxide-semiconductor M10 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M11 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M10, the drain electrode of N-type metal-oxide-semiconductor M11, the 3rd capacitor C 3, the grid of P type metal-oxide-semiconductor M12 and the grid of N-type metal-oxide-semiconductor M13 interconnect; The other end of the 3rd capacitor C 3 is connected with ground; The source electrode of P type metal-oxide-semiconductor M12 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M13 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M12, the drain electrode of N-type metal-oxide-semiconductor M13, an end of the 4th capacitor C 4 and the input of the 3rd inverter INV3 interconnect; Input and the end points C of the grid of the output of the 3rd inverter INV3, P type metal-oxide-semiconductor M14, the grid of N-type metal-oxide-semiconductor M15, first liang of input nand gate NAND2 interconnect; The source electrode of P type metal-oxide-semiconductor M14 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M15 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M14, the drain electrode of N-type metal-oxide-semiconductor M15, the 5th capacitor C 5, the grid of P type metal-oxide-semiconductor M16 and the grid of N-type metal-oxide-semiconductor M17 interconnect; The other end of the 5th capacitor C 5 is connected with ground; The source electrode of P type metal-oxide-semiconductor M16 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M17 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M16, the drain electrode of N-type metal-oxide-semiconductor M17, an end of the 6th capacitor C 6 and the input of the 4th inverter INV4 interconnect; The other end of the 6th capacitor C 6 is connected with ground; Another input of first liang of input nand gate NAND2, the output of the 4th inverter INV4 and end points D interconnect; Input and the end points E of first liang of input nand gate NAND2 output, the 5th inverter INV5 interconnect; The output of the 5th inverter INV5 and the input of hex inverter INV6 interconnect; The output RST of the output of hex inverter INV6 and electrify restoration circuit interconnects.
In the present embodiment, when chip power power up and high impulse global reset signal of CTR signal generation, all can produce a reset pulse.Make a concrete analysis of as follows:
When CTR connects low level all the time, P type metal-oxide-semiconductor M1 conducting all the time.In the power up, the power vd D increase of starting from scratch, the voltage of terminal A is corresponding increase also, but the increase amplitude is about power vd D half.
When power vd D increases to a certain value (such as threshold voltage VTHP), but the voltage of terminal A is when also surpassing threshold voltage VTHN, P type metal-oxide-semiconductor M6 conducting, and N-type metal-oxide-semiconductor M7 closes, so the voltage of end points CP voltage follow power vd D and changing.Accordingly, the voltage of end points CN, end points C is low level voltage, the change in voltage of the voltage follow power vd D of end points D, end points E.So P type metal-oxide-semiconductor M8 and N-type metal-oxide-semiconductor M9 turn-off, the voltage of terminal B is followed the change in voltage of power vd D always.
After terminal A voltage was greater than threshold voltage VTHN, the voltage of end points CP was low level by the voltage upset of power vd D, and the voltage of end points CN is the voltage of power vd D by the low level upset.So, P type metal-oxide-semiconductor M8 and all conductings of N-type metal-oxide-semiconductor M9, electric charge on the terminal B and the electric charge on the terminal A are redistributed, because the voltage on the terminal B is the voltage of power vd D before conducting, and the voltage on the terminal A is bigger than the value of capacitor C 1 if the value of C2 is held in power taking less than the voltage of power vd D, so, the voltage of redistributing on the aft terminal A can so just reach the purpose of accelerating the electrification reset response greater than original value.
Because the voltage of end points CN is the voltage of power vd D by the low level upset, the voltage of end points C is being the voltage of power vd D by the low level upset also after the delay of t1 after a while, because having, the circuit that P type metal-oxide-semiconductor M14, N-type metal-oxide-semiconductor M15, P type metal-oxide-semiconductor M16, N-type metal-oxide-semiconductor M17, capacitor C 5 and capacitor C 6 constitute produces the signal lag function that is input to output, this moment, the voltage of end points D still be the voltage of power vd D, was low level so the output voltage of first liang of input nand gate NAND2 is overturn by the voltage of power vd D.But after end points C voltage was voltage a period of time t2 of power vd D by the low level upset, end points D was low level by the voltage upset of power vd D, and the output voltage of first liang of input nand gate NAND2 is the voltage of power vd D by the low level upset.So in the power up of power vd D, the voltage of end points E can produce one and be turned to low level by the power supply vdd voltage, is turned to the pulse of power supply vdd voltage again from low level, its pulse duration is about time t2.Because the 5th inverter INV5 and hex inverter INV6 are the shapings that is input to output, so the output end voltage of hex inverter INV6 that is to say that the voltage of the output signal RST of electrify restoration circuit can produce a low level reseting pulse signal.
When the power supply vdd voltage was in the normal working voltage scope all the time, if the CTR signal is a high level pulse signal, just reset circuit also can produce the reset signal of a low level pulse after the trailing edge of CTR signal.Make a concrete analysis of as follows:
When the power supply vdd voltage is in the normal working voltage scope all the time, and other circuit is when work in the chip, voltage should be low level on the CTR signal, at this moment, the voltage of end points CP, end points D is low level in the electrify restoration circuit, and the output RST voltage of signals of end points CN, end points C, end points E, terminal A, electrify restoration circuit is the power supply vdd voltage.At this moment, P type metal-oxide-semiconductor M8 and all conductings of N-type metal-oxide-semiconductor M9, terminal A equates substantially with the voltage of terminal B, and greater than threshold voltage VTHN.
Voltage on the CTR signal is the power supply vdd voltage by the low level upset, P type metal-oxide-semiconductor M1 closes, and does not have electric current in the branch road that P type metal-oxide-semiconductor M1, M2, M3, M4, M5 constitute, so, each node voltage in the branch road all can descend, so the also corresponding decline of the voltage of terminal A.When the voltage of terminal A drops to less than VTHN, the voltage of end points CP is the voltage of power vd D by the low level upset, and the voltage of end points CN is low level by the voltage upset of power vd D.So P type metal-oxide-semiconductor M8 and N-type metal-oxide-semiconductor M9 turn-off.After a period of time in, the voltage that the voltage of terminal B is no longer followed terminal A descends together, but remains a certain fixed value VB.The voltage of end points C is turned to low level by the power supply vdd voltage, and the voltage of end points D is turned to the power supply vdd voltage by low level.The voltage of the output signal RST of end points E, electrify restoration circuit remains unchanged, and still is the power supply vdd voltage.
If the time long enough of CTR signal high level, the voltage of terminal A can drop to the threshold voltage sum near P type metal-oxide-semiconductor M4 and M5.
Voltage on the CTR signal is low level by the upset of power supply vdd voltage, P type metal-oxide-semiconductor M1 conducting all the time, and the branch road that P type metal-oxide-semiconductor M1, M2, M3, M4, M5 constitute can charge to terminal A, and the voltage of terminal A can rise,
After terminal A voltage was greater than threshold voltage VTHN, the voltage of end points CP was low level by the voltage upset of power vd D, and the voltage of end points CN is the voltage of power vd D by the low level upset.P type metal-oxide-semiconductor M8 and all conductings of N-type metal-oxide-semiconductor M9, electric charge on the terminal B and the electric charge on the terminal A are redistributed, because the voltage on the terminal B is when voltage is the power supply vdd voltage on the CTR signal, remain on a higher level, voltage on ratio terminal A this moment is big, and is bigger than the value of capacitor C 1 if the value of C2 is held in power taking, so, the voltage of redistributing on the aft terminal A can so just reach the purpose that acceleration resets and responds greater than original value.
Because the voltage of end points CN is the voltage of power vd D by the low level upset, the voltage of end points C is being the voltage of power vd D by the low level upset also after the delay of t1 after a while, because having, the circuit that P type metal-oxide-semiconductor M14, N-type metal-oxide-semiconductor M15, P type metal-oxide-semiconductor M16, N-type metal-oxide-semiconductor M17, capacitor C 5 and capacitor C 6 constitute produces the signal lag function that is input to output, this moment, the voltage of end points D still be the voltage of power vd D, was low level so the output voltage of first liang of input nand gate NAND2 is overturn by the voltage of power vd D.But after end points C voltage was voltage a period of time t2 of power vd D by the low level upset, end points D was low level by the voltage upset of power vd D, and the output voltage of first liang of input nand gate NAND2 is the voltage of power vd D by the low level upset.So in the power up of power vd D, the voltage of end points E can produce one and be turned to low level by the power supply vdd voltage, is turned to the pulse of power supply vdd voltage again from low level, its pulse duration is about time t2.Because the 5th inverter INV5 and hex inverter INV6 are the shapings that is input to output, so the output end voltage of hex inverter INV6 that is to say that the voltage of the output signal RST of electrify restoration circuit can produce a low level reseting pulse signal.
The content that is not described in detail in this specification belongs to this area professional and technical personnel's known prior art.
Above embodiment only is a kind of preferred embodiment of the present utility model, but is not the whole of all circuit set-up modes of the present utility model, all in the utility model spirit essential scope with the interior equivalents of being done, all will be in the utility model protection range.
Claims (7)
1. one kind has the electrify restoration circuit that overall enabling pulse is controlled auto-reset function, it is characterized in that: described circuit comprises division module (1), level detection module (2), quick respond module (3), time delay module (4), reseting pulse signal generation module (5) and waveform-shaping module (6), the outside enabling pulse signal of the input termination of division module (1); The output of division module (1) is connected with the output of the input of level detection module (2), quick respond module (3); The output of level detection module (2) is connected with the input of quick respond module (3), the input of time delay module (4); The output of time delay module (4) is connected with the input of reseting pulse signal generation module (5); The output of reseting pulse signal generation module (5) is connected with the input of waveform-shaping module (6); The voltage of the output of waveform-shaping module (6) is as the output signal of electrify restoration circuit, wherein:
Division module (1) is for generation of the component of voltage relevant with supply voltage, it is controlled by external input signal, when external input signal makes division module (1) when not working, the final output level of division module (1) output is lower than the upset level of testing circuit module;
Level detection module (2) is for detection of the output level of division module (1), according to the size of the output level of division module (1), at the different voltage signal of output output of level detection module (2);
Quick respond module (3), be used for detect division module (1) output level greater than a certain fixed value after, make the output level fast rise of division module (1);
Time delay module (4) is used for adjusting the time interval between power up and the reseting pulse signal generation;
Reseting pulse signal generation module (5) for generation of the reset level pulse signal, resets after at certain time intervals and finishes, and reset pulse finishes;
Waveform-shaping module (6), the output voltage that reseting pulse signal generation module (5) is produced amplifies and shaping, and will amplify with shaping after voltage signal as the output signal of electrify restoration circuit.
2. a kind of electrify restoration circuit that has overall enabling pulse control auto-reset function according to claim 1, it is characterized in that: described voltage module (1) contains the P type metal-oxide-semiconductor M1 as switching tube, under the control of systematic reset signal division module is enabled control; P type metal-oxide-semiconductor M2, M3, M4, the M5 of 4 diode connections form bleeder circuit, and the voltage with mains voltage variations is provided; First resistance R 1 and first capacitor C 1 are formed filter circuit, and the final voltage output of division module is provided;
Division module (1) circuit connects in the following manner:
The source electrode of P type metal-oxide-semiconductor M1 is connected with power supply; The grid of P type metal-oxide-semiconductor M1 is connected with systematic reset signal CTR; The source electrode of the drain electrode of P type metal-oxide-semiconductor M1 and P type metal-oxide-semiconductor M2 interconnects; The grid of P type metal-oxide-semiconductor M2, the source electrode of the drain electrode of P type metal-oxide-semiconductor M2 and P type metal-oxide-semiconductor M3 interconnects; The grid of P type metal-oxide-semiconductor M3, the source electrode of the drain electrode of P type metal-oxide-semiconductor M3, P type metal-oxide-semiconductor M4 and an end of first resistance R 1 interconnect; The grid of P type metal-oxide-semiconductor M4, the source electrode of the drain electrode of P type metal-oxide-semiconductor M4 and P type metal-oxide-semiconductor M5 interconnects; The grid of P type metal-oxide-semiconductor M5, the drain electrode of P type metal-oxide-semiconductor M5 with interconnect; The output of one end of the other end of first resistance R 1, first capacitor C 1 and division module (1) interconnects; The other end of first capacitor C 1 is connected with ground.
3. a kind of electrify restoration circuit that has overall enabling pulse control auto-reset function according to claim 1, it is characterized in that: described level detection module (2) circuit contains P type metal-oxide-semiconductor M6, N-type metal-oxide-semiconductor M7, constitute level sensitive circuit, by adjusting the suitable upset level of device size design of P type metal-oxide-semiconductor M6 and N-type metal-oxide-semiconductor M7; The first inverter INV1 is used to provide the opposite levels of signal, and the input and output signal of the first inverter INV1 is controlled the transmission gate in the quick respond module circuit simultaneously;
Level detection module (2) circuit connects in the following manner:
The grid of the output of the input of level detection module (2) circuit, division module (1) circuit, P type metal-oxide-semiconductor M6, the grid of N-type metal-oxide-semiconductor M7 interconnect with the output of quick respond module (3); The source electrode of P type metal-oxide-semiconductor M6 is connected with power supply; The drain electrode of P type metal-oxide-semiconductor M6, the drain electrode of N-type metal-oxide-semiconductor M7, the grid of P type metal-oxide-semiconductor M8 and the input of the first inverter INV1 interconnect; The source electrode of N-type metal-oxide-semiconductor M7 is connected with ground; The output of the output of the first inverter INV1 and level detection module (2) circuit interconnects.
4. a kind of electrify restoration circuit that has overall enabling pulse control auto-reset function according to claim 1, it is characterized in that: described quick respond module (3) circuit contains as the P type metal-oxide-semiconductor M8 of switching tube with as the N-type metal-oxide-semiconductor M9 of switching tube, constitutes a transmission gate; Second capacitor C 2 is used for giving when the transmission gate conducting output of division module circuit that electric charge is provided, and accelerates the rising of the output end voltage of division module circuit;
Respond module (3) circuit connects in the following manner fast:
The drain electrode of P type metal-oxide-semiconductor M6, the drain electrode of N-type metal-oxide-semiconductor M7, the grid of P type metal-oxide-semiconductor M8 and the input of the first inverter INV1 interconnect; The grid of the input of the output of the first inverter INV1, time delay module (4) and N-type metal-oxide-semiconductor M9 interconnects; One end of the source electrode of P type metal-oxide-semiconductor M8, the drain electrode of N-type metal-oxide-semiconductor M9 and second capacitor C 2 interconnects; The other end of second capacitor C 2 is connected with power supply; The drain electrode of the input of the output of division module (1) circuit, level detection module (2) circuit, P type metal-oxide-semiconductor M8, the source electrode of N-type metal-oxide-semiconductor M9 interconnect with the output of quick respond module (3) circuit.
5. a kind of electrify restoration circuit that has overall enabling pulse control auto-reset function according to claim 1, it is characterized in that: described time delay module (4) circuit contains the second inverter INV2, the 3rd inverter INV3, is used for the anti-phase output of voltage; P type metal-oxide-semiconductor M10, N-type metal-oxide-semiconductor M11, P type metal-oxide-semiconductor M12, N-type metal-oxide-semiconductor M13, the 3rd capacitor C 3 and the 4th capacitor C 4 are for generation of the signal lag that is input to output;
Time delay module (4) circuit connects in the following manner:
The output of the input of time delay module (4) circuit, level detection module (2) circuit and the input of the second inverter INV2 interconnect; The grid of the output of the second inverter INV2, P type metal-oxide-semiconductor M10 and the grid of N-type metal-oxide-semiconductor M11 interconnect; The source electrode of P type metal-oxide-semiconductor M10 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M11 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M10, the drain electrode of N-type metal-oxide-semiconductor M11, the 3rd capacitor C 3, the grid of P type metal-oxide-semiconductor M12 and the grid of N-type metal-oxide-semiconductor M13 interconnect; The other end of the 3rd capacitor C 3 is connected with ground; The source electrode of P type metal-oxide-semiconductor M12 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M13 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M12, the drain electrode of N-type metal-oxide-semiconductor M13, an end of the 4th capacitor C 4 and the input of the 3rd inverter INV3 interconnect; The input of the output of the output of the 3rd inverter INV3, time delay module (4) circuit and reseting pulse signal generation module (5) circuit interconnects.
6. a kind of electrify restoration circuit that has overall enabling pulse control auto-reset function according to claim 1, it is characterized in that: described reseting pulse signal generation module (5) circuit contains P type metal-oxide-semiconductor M14, N-type metal-oxide-semiconductor M15, P type metal-oxide-semiconductor M16, N-type metal-oxide-semiconductor M17, the 5th capacitor C 5 and the 6th capacitor C 6, for generation of the signal lag that is input to output; The 4th inverter INV4 is used for the anti-phase output of voltage; First liang of input nand gate NAND2 by the difference of input signal, produces reset pulse output;
Reseting pulse signal generation module (5) circuit connects in the following manner:
The input of the grid of the input of time delay module (4) circuit output end, reseting pulse signal generation module (5) circuit, P type metal-oxide-semiconductor M14, the grid of N-type metal-oxide-semiconductor M15 and first liang of input nand gate NAND2 interconnects; The source electrode of P type metal-oxide-semiconductor M14 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M15 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M14, the drain electrode of N-type metal-oxide-semiconductor M15, the 5th capacitor C 5, the grid of P type metal-oxide-semiconductor M16 and the grid of N-type metal-oxide-semiconductor M17 interconnect; The other end of the 5th capacitor C 5 is connected with ground; The source electrode of P type metal-oxide-semiconductor M16 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M17 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M16, the drain electrode of N-type metal-oxide-semiconductor M17, an end of the 6th capacitor C 6 and the input of the 4th inverter INV4 interconnect; The other end of the 6th capacitor C 6 is connected with ground; Another input of first liang of input nand gate NAND2 and the output of the 4th inverter INV4 interconnect; The input of the output of first liang of input nand gate NAND2 and waveform-shaping module circuit interconnects.
7. a kind of electrify restoration circuit that has overall enabling pulse control auto-reset function according to claim 1, it is characterized in that: described waveform-shaping module (6) circuit contains the 5th inverter INV5 and hex inverter INV6, input signal is amplified and shaping, the electrification reset output signal is provided
Waveform-shaping module (6) circuit connects in the following manner:
The input of the output of reseting pulse signal generation module (5) circuit, waveform-shaping module (6) circuit and the input of the 5th inverter INV5 interconnect; The output of the 5th inverter INV5 and the input of hex inverter INV6 interconnect; The output RST of the output of hex inverter INV6 and electrify restoration circuit interconnects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320040221 CN203135824U (en) | 2013-01-25 | 2013-01-25 | A power on reset circuit containing a global enabling pulse control automatic reset function |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320040221 CN203135824U (en) | 2013-01-25 | 2013-01-25 | A power on reset circuit containing a global enabling pulse control automatic reset function |
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| CN203135824U true CN203135824U (en) | 2013-08-14 |
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| CN 201320040221 Withdrawn - After Issue CN203135824U (en) | 2013-01-25 | 2013-01-25 | A power on reset circuit containing a global enabling pulse control automatic reset function |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066972A (en) * | 2013-01-25 | 2013-04-24 | 湘潭芯力特电子科技有限公司 | Power-on reset circuit with global enabling pulse control automatic reset function |
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- 2013-01-25 CN CN 201320040221 patent/CN203135824U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066972A (en) * | 2013-01-25 | 2013-04-24 | 湘潭芯力特电子科技有限公司 | Power-on reset circuit with global enabling pulse control automatic reset function |
| CN103066972B (en) * | 2013-01-25 | 2015-04-15 | 湘潭芯力特电子科技有限公司 | Power-on reset circuit with global enabling pulse control automatic reset function |
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