CN103633974A - Power-on reset circuit with fixed resistance-capacitance time delay characteristic - Google Patents
Power-on reset circuit with fixed resistance-capacitance time delay characteristic Download PDFInfo
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Abstract
The invention provides a power-on reset circuit of an integrated circuit chip. The power-on reset circuit is characterized in that in power-on procedures of a power source, a starting circuit starts to work at first, so that current reference required by a resistance-capacitance circuit and a voltage comparator can be generated by a bias circuit; initial voltages at two ends of a capacitor are low, output of the voltage comparator is high, and high-level reset signals are outputted; the voltages are increased gradually along with charging procedures, the output of the comparator is turned over when the voltages exceed a voltage value determined by divided voltages of resistors, low-level signals are outputted, and reset procedures are completed. The power-on reset circuit has the advantages that durations of the reset signals are determined mainly by parameters of the resistors and the capacitor, reference comparison voltages generated by an extra circuit can be omitted, and accordingly the stable reset signals can be outputted.
Description
Technical field
The present invention relates to a kind of chip power-on reset circuit, be specifically related to a kind of fixedly electrify restoration circuit of capacitance-resistance time delay characteristic that has.
Background technology
Integrated circuit (IC) system structure becomes increasingly complex at present, and integrated level is more and more higher.Along with the expansion of integrated circuit scale, the digital circuit that it is inner and analog module need to be when powering on, the initial work of completing circuit.For guaranteeing the correctness of each digital logic module state of IC interior, carry the incipient stage at chip power, carry out the reset work of all circuit.Electrify restoration circuit (power on reset, be called for short POR), need exactly in the process of power supply electrifying, produce an effective high level or low level reset signal, make internal circuit enter definite logic state, to when follow-up sequential conversion, enter smoothly predetermined logic state.In Design of Digital Circuit, reset signal generally adopts Low level effective, need to, with certain delay and certain low level pulse width, require this circuit to have low in energy consumption, the performance of good stability simultaneously.
A kind of implementation of simple the most common electrify restoration circuit as shown in Figure 1, utilizes the charge-discharge principle of RC to realize.Wherein the characteristic of metal-oxide-semiconductor is equivalent to a resistance with a constant impedance.In the time of chip power, supply voltage raises gradually, and electric capacity both end voltage be because can not suddenly change, thereby still keeps electronegative potential.Now, reset signal is output as high level.Along with power supply power supply charges to capacitor C by resistance, electric capacity both end voltage slowly raises, and when it surpasses the turnover voltage of reverser, the output switching activity of reset signal is high level, and keeps high level state always.This electrify restoration circuit is simple in structure, but it can only provide rising edge from low to high, can not judge the height of supply voltage, therefore, when supply voltage is too low, can cause the unstable of system reset.
Another kind of electrify restoration circuit sees in the scientific paper of the people such as W.C.Yen " the A precision CMOS power-on reset circuit with power noise immunity for low-voltage technology " by name of 2004, as shown in Figure 2.Its principle is whether to detect the difference of supply voltage VDD and b point voltage Vb higher than bandgap voltage reference, due to Vb ground connection, can be considered Vb=0, whether detects supply voltage VDD higher than bandgap voltage reference.But this circuit can not accurately be set the time width of reset signal.Chinese utility model patent (CN202550986U) discloses a kind of electrify restoration circuit.This utility model is not needing external voltage benchmark or is producing under the prerequisite of inner band-gap reference accurately to detect various supply voltages, traditional electrify restoration circuit is had to larger performance boost, there is lower power consumption and temperature coefficient and less technique change.But the width of the reset signal pulse of this circuit can not effectively be controlled.
To sum up, in the prior art, if realize stable power-on reset signal, its cost is higher, and also more complicated of control mode, therefore those skilled in the art endeavour research how under the prerequisite guaranteeing in strict cost control always, and the best function that realizes electrification reset, to increase the reliability of chip circuit.
Summary of the invention
The invention provides a kind of chip power-on reset circuit, by using start-up circuit and resistance-capacitance circuit time delay to produce circuit, the in the situation that of less cost, realized larger time delay output and stable power-on reset signal.
A chip power-on reset circuit, in described electrify restoration circuit application and the start-up circuit of integrated circuit.Described circuit provides a reset signal with certain pulse duration, comprising: start-up circuit, biasing circuit, resistance-capacitance circuit, voltage comparator, output buffering.
Described start-up circuit connects biasing circuit, provides enabling signal, and determine the time started point of the time delay of power-on reset signal for biasing circuit produces required current offset.In start-up circuit, transistor (M2) and transistor (M3) are down that its grid point is connected on supply voltage, the electric current of transistor (M1) mirror image biasing circuit than pipe.Transistor (M4) is used as a switching tube, controls the operating state of biasing circuit.
Described biasing circuit produces resistance-capacitance circuit and the required bias current of voltage comparator.
Described resistance-capacitance circuit consists of metal-oxide-semiconductor, resistance, electric capacity, completes the delay function of power-on reset signal.
Described voltage comparator completes the comparison of two circuit node voltage swings in described resistance-capacitance circuit, and voltage ratio result is exported after by described output buffer stage shaping.
Described output buffering is to consist of a plurality of not circuits, plays the effect of signal shaping in circuit, starts the chip circuit of rear class.
Two circuit node voltages of described resistance-capacitance circuit, one is node voltage VA, by two electric resistance partial pressures, is obtained, another node voltage VB, is obtained by the series connection node of resistance and electric capacity.These two node voltages are sent into respectively two inputs of voltage comparator.
Described comparator circuit comprises image current pipe unit and the difference input utmost point, at the output of comparator, has increased an electric capacity, strengthens the stability of comparator.
Above-mentioned resistance-capacitance circuit, the grid of transistor (M9) is received on the bias voltage of drain terminal of transistor in biasing circuit (M6), and resistance (R1) is connected with resistance (R2), and resistance (R3) is connected with electric capacity (C1), after two series arm parallel connections, be connected to the drain electrode of transistor (M9).
Described biasing circuit is comprised of PMOS mirrored transistor and NMOS mirrored transistor, and resistance (R0) is connected between transistor (M8) and ground level.
Because the present invention has adopted above technical scheme, by resistance-capacitance circuit, control the pulse duration of reset signal, can send the more stable signal delay with independent from voltage, meanwhile, by the design and use of biasing circuit, can realize a rational circuit start threshold voltage, make the generation of power-on reset signal more accurate, avoided rising at supply voltage process in, produce uncertain reset signal, realized the electrify restoration circuit that can produce reliable and stable reset signal.
Accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that the present invention and feature thereof, profile and advantage will become.In whole accompanying drawings, identical mark is indicated identical part.Deliberately proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is the electrifying startup circuit that uses capacitance-resistance mode to realize in prior art;
Fig. 2 utilizes band gap voltage to realize the circuit diagram of electrification reset in prior art;
Fig. 3 is a kind of electrify restoration circuit structure chart provided by the invention;
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
A kind of electrify restoration circuit structure chart that invention provides, as shown in Figure 3, a kind of electrify restoration circuit, comprises start-up circuit, biasing circuit, resistance-capacitance circuit, voltage comparator, output buffer.
In start-up circuit, transistor M2 and transistor M3 are down that its grid point is connected on supply voltage, the leakage current of transistor M1 mirror image biasing circuit transistor M5 than pipe.Transistor M4 is used as a switching tube, controls the operating state of biasing circuit.
Biasing circuit comprises transistor M5, M6, the image current pipe unit that M7, M8 form, and wherein resistance R 0 is connected between transistor M8 and ground level.
In resistance-capacitance circuit, the grid of transistor M9 is received the drain electrode of M6, forms image current mirror unit.Resistance R 1 and R2 series connection, resistance R 3 and capacitor C 1 series connection.One end of resistance R 1 and R3 joins, and one end of resistance R 2 and capacitor C 1 is connected to ground level.The intermediate point of resistance R 1 and resistance R 2 forms voltage VA, and the intermediate point of resistance R 3 and capacitor C 1 forms voltage VB.Positive input terminal and negative input end that the voltage VA producing and VB are connected respectively to differential-voltage comparator.
Normal phase input end and negative-phase input that the input of voltage comparator is comparator to the grid of pipe M12 and M13.The source electrode of transistor M12 and M13 is connected, and is jointly connected in the drain electrode of tail current transistor M14.Transistor M10 and M11 are diode connections, as the load of input stage, use, and transistor M15 and M17 are the inputs of the second level of amplifier, and two transistorized grids are connected to respectively the grid of transistor M10 and M11.Transistor M16 and M18 form current mirror to pipe.
The output of voltage comparator is received ground level by capacitor C 2.
Output buffer stage consists of the Digital Logic not gate of two cascades.Final power-on reset signal is sent by exit point POR.
When supply voltage rises, first, start-up circuit judges whether biasing circuit works.If biasing circuit does not also enter operating state, the electric current of transistor M1 is very little, now transistor M2 and M3 have entered saturated, the drain voltage of transistor M1 is drawn as low level, the grid of transistor M4 is connected to the drain electrode of transistor M1, when the grid of transistor M4 is input as low level, can allow transistor M4 conducting, make the grid voltage of mirrored transistor M7 and M8 for high, make transistor M7 and M8 in operate in saturation.After circuit arrives balance point, the bias current that biasing circuit forms is determined by the parameter of transistor M7, M8 and resistance R 0.
After biasing circuit normal operation, resistance-capacitance circuit also enters operating state.When circuit is initial, the voltage at capacitor C 1 two ends is zero.The electric current of transistor M9 mirror image biasing circuit, starts to charge by 3 pairs of capacitor C 1 of resistance R.The voltage at capacitor C 1 two ends raises gradually, and the maximum of its final voltage is the drain voltage of transistor M9.This voltage is determined jointly by electric current, resistance R 1 and the resistance R 2 of transistor M9.When capacitor C 1 charging finishes, it is consistent with the drain voltage of transistor M9 that the voltage at its two ends reaches.The required time is only relevant with the parameter value of capacitor C 1 by resistance R 3.When the value of resistance R 1 is very little, the time constant that the charging interval of capacitor C 1 consists of the parameter product of resistance R 3 and capacitor C 1 is relevant, and magnitude of voltage when finishing with concrete charging is irrelevant.That is to say, in charging process, node voltage VA is the stable magnitude of voltage of a Rapid Establishment, node voltage VB is the end-point voltage of capacitor C 1, and voltage VB starts from scratch to be increased gradually, now, the voltage of node voltage VB is less than the value of node voltage VA, voltage comparator is two point voltages relatively, export a high level, as reset signal level.Along with the continuation of charging process, node voltage VB raises gradually, finally surpasses the stable voltage of node voltage VA, and now, voltage comparator is two point voltages relatively, export a low level, and the reset of rear class chip circuit is controlled and finished.
The output of voltage comparator connects capacitor C 2 can be so that the Output rusults of voltage comparator be subject to the impact of the less ripple of supply voltage, the comparative result of stable output.
Working method by resistance-capacitance circuit is analyzed, and resistance-capacitance circuit can complete comparatively precise time time delay and control, and the time length of its time delay is determined by resistance R 3 and capacitor C 1, is not subject to the impact of supply voltage, is a constant substantially.The need of work of biasing circuit rises to certain electrical voltage point at supply voltage just to start, therefore,, when biasing circuit works, supply voltage can be more than the twice higher than transistor threshold voltage, now, other circuit can enter operating state smoothly.
The electrify restoration circuit of implementing, when supply voltage is lower, is sent high level signal as the output of reset signal, if need to send low level reset signal, can in output buffer stage circuit, increase inverter, realizes the upset of logic level.
In sum, because this law has adopted above technical scheme, do not need bandgap voltage circuits to produce a fixing band gap voltage as the input of voltage comparator, can guarantee that electrify restoration circuit is in the process of supply voltage rising, produce required reset level signal, and then the chip circuit connecting is carried out to correct control.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (8)
1. in the electrify restoration circuit application described in and the start-up circuit of integrated circuit.Described circuit provides a reset signal with certain pulse duration, comprising: start-up circuit, biasing circuit, resistance-capacitance circuit, voltage comparator, output buffering;
Described start-up circuit connects biasing circuit, provides enabling signal, and determine the time started point of the time delay of power-on reset signal for biasing circuit produces required current offset;
Described biasing circuit produces resistance-capacitance circuit and the required bias current of voltage comparator;
Described resistance-capacitance circuit consists of metal-oxide-semiconductor, resistance, electric capacity, completes the delay function of power-on reset signal;
Described voltage comparator completes the comparison of two circuit node voltage swings in described resistance-capacitance circuit, and voltage ratio result is exported after by described output buffer stage shaping;
Described output buffering is to consist of a plurality of not circuits, plays the effect of signal shaping in circuit, starts the chip circuit of rear class.
2. electrify restoration circuit according to claim 1, is characterized in that, it is that resistance R 1 and R2 series connection ，Yi road are resistance R 3 and capacitor C 1 series connection that described resistance-capacitance circuit forms ，Yi road by two series arm parallel connections.Intermediate point output node voltage VA and the node voltage VB of two series arms.After two series arm parallel connections, be connected to a fixing voltage high level simultaneously.
3. electrify restoration circuit according to claim 2, is characterized in that, an end of resistance-capacitance circuit is connected to a fixing voltage high level, and this voltage high level can be to be formed by multiple circuit.
4. electrify restoration circuit according to claim 2, is characterized in that, two node voltage VA of resistance-capacitance circuit and node voltage VB receive respectively two inputs of voltage comparator;
Described voltage comparator is to have the structure of difference input to pipe.
5. electrify restoration circuit according to claim 1, it is characterized in that, the grid of the transistor M9 in resistance-capacitance circuit is connected on the bias voltage node of biasing circuit formation, when supply voltage rises to certain magnitude of voltage, just conducting of transistor M9, by 1 charging of 3 pairs of capacitor C of resistance R.
6. electrify restoration circuit according to claim 1, is characterized in that, capacitor C 2 of output termination of voltage comparator, and in the process that supply voltage rises, the impact of the fluctuation that reduces voltage on voltage comparator Output rusults.
7. electrify restoration circuit according to claim 1, is characterized in that, the output of voltage comparator is connected to output buffer stage circuit, after carrying out the drive amplification of signal, finally sends.Output buffer stage circuit consists of Digital Logic not circuit.
8. electrify restoration circuit according to claim 1, is characterized in that, described image current pipe unit comprises a plurality of image current pipes, and the described difference input utmost point comprises the difference transistor (M12, M13) that at least one pair of is in parallel;
Described in each, the source electrode of difference transistor (M12, M13) all connects the wherein drain electrode of a mirrored transistor.
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| CN201310647791.2A CN103633974A (en) | 2013-12-04 | 2013-12-04 | Power-on reset circuit with fixed resistance-capacitance time delay characteristic |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104378093A (en) * | 2014-11-17 | 2015-02-25 | 锐迪科创微电子（北京）有限公司 | Power-on reset method and circuit using MIPI standard circuit |
| CN104734679A (en) * | 2015-02-05 | 2015-06-24 | 西安中颖电子有限公司 | Low-voltage reset circuit |
| CN105425887A (en) * | 2015-12-30 | 2016-03-23 | 广西师范大学 | Correctable low-power consumption voltage reference source with power-on reset function |
| WO2016119471A1 (en) * | 2015-01-28 | 2016-08-04 | 无锡华润上华半导体有限公司 | Power on reset circuit |
| CN105892553A (en) * | 2016-05-06 | 2016-08-24 | 芯原微电子(上海)有限公司 | Power supply voltage electrification detection circuit and achieving method for electrification detection |
| CN107078735A (en) * | 2014-10-24 | 2017-08-18 | 索尼半导体解决方案公司 | Electrification reset circuit and high-frequency communication apparatus |
| CN107222192A (en) * | 2017-05-30 | 2017-09-29 | 长沙方星腾电子科技有限公司 | A kind of electrification reset circuit |
| CN108667443A (en) * | 2018-05-18 | 2018-10-16 | 上海艾为电子技术股份有限公司 | A kind of electrification reset circuit |
| CN109300492A (en) * | 2017-07-25 | 2019-02-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of electrification signal generating circuit |
| CN111781984A (en) * | 2020-08-29 | 2020-10-16 | 深圳市爱协生科技有限公司 | POR circuit and design method thereof |
| CN113810032A (en) * | 2021-09-24 | 2021-12-17 | 电子科技大学 | Power-on reset circuit structure |
| CN117040510A (en) * | 2023-10-10 | 2023-11-10 | 浙江地芯引力科技有限公司 | Power supply power-on and power-off detection reset circuit, chip and electronic equipment |
| CN117749150A (en) * | 2024-02-19 | 2024-03-22 | 北京中天星控科技开发有限公司成都分公司 | Quick and slow power-on reset circuit |
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| US20090267659A1 (en) * | 2008-04-28 | 2009-10-29 | Hong Fu Jin Precision Industry (Shenzhen) Co.,Ltd. | Power-on reset circuit and electronic device using the same |
| CN101588167A (en) * | 2009-06-18 | 2009-11-25 | 广州润芯信息技术有限公司 | Electrifying reset and undervoltage turnoff circuit |
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| JPH11163702A (en) * | 1997-11-28 | 1999-06-18 | Matsushita Electric Ind Co Ltd | Resetting circuit |
| US20090267659A1 (en) * | 2008-04-28 | 2009-10-29 | Hong Fu Jin Precision Industry (Shenzhen) Co.,Ltd. | Power-on reset circuit and electronic device using the same |
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Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107078735A (en) * | 2014-10-24 | 2017-08-18 | 索尼半导体解决方案公司 | Electrification reset circuit and high-frequency communication apparatus |
| CN104378093A (en) * | 2014-11-17 | 2015-02-25 | 锐迪科创微电子（北京）有限公司 | Power-on reset method and circuit using MIPI standard circuit |
| CN105991119B (en) * | 2015-01-28 | 2019-01-04 | 无锡华润上华科技有限公司 | Electrification reset circuit |
| WO2016119471A1 (en) * | 2015-01-28 | 2016-08-04 | 无锡华润上华半导体有限公司 | Power on reset circuit |
| CN105991119A (en) * | 2015-01-28 | 2016-10-05 | 无锡华润上华半导体有限公司 | Power-on reset circuit |
| US10340912B2 (en) | 2015-01-28 | 2019-07-02 | Csmc Technologies Fab2 Co., Ltd. | Power on reset circuit |
| CN104734679B (en) * | 2015-02-05 | 2018-05-22 | 西安中颖电子有限公司 | Low voltage reset circuit |
| CN104734679A (en) * | 2015-02-05 | 2015-06-24 | 西安中颖电子有限公司 | Low-voltage reset circuit |
| CN105425887A (en) * | 2015-12-30 | 2016-03-23 | 广西师范大学 | Correctable low-power consumption voltage reference source with power-on reset function |
| CN105892553A (en) * | 2016-05-06 | 2016-08-24 | 芯原微电子(上海)有限公司 | Power supply voltage electrification detection circuit and achieving method for electrification detection |
| CN107222192A (en) * | 2017-05-30 | 2017-09-29 | 长沙方星腾电子科技有限公司 | A kind of electrification reset circuit |
| CN109300492A (en) * | 2017-07-25 | 2019-02-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of electrification signal generating circuit |
| CN109300492B (en) * | 2017-07-25 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Electrifying signal generating circuit |
| CN108667443A (en) * | 2018-05-18 | 2018-10-16 | 上海艾为电子技术股份有限公司 | A kind of electrification reset circuit |
| CN108667443B (en) * | 2018-05-18 | 2021-11-23 | 上海艾为电子技术股份有限公司 | Power-on reset circuit |
| CN111781984A (en) * | 2020-08-29 | 2020-10-16 | 深圳市爱协生科技有限公司 | POR circuit and design method thereof |
| CN113810032A (en) * | 2021-09-24 | 2021-12-17 | 电子科技大学 | Power-on reset circuit structure |
| CN113810032B (en) * | 2021-09-24 | 2023-08-22 | 电子科技大学 | Power-on reset circuit structure |
| CN117040510A (en) * | 2023-10-10 | 2023-11-10 | 浙江地芯引力科技有限公司 | Power supply power-on and power-off detection reset circuit, chip and electronic equipment |
| CN117040510B (en) * | 2023-10-10 | 2024-01-16 | 浙江地芯引力科技有限公司 | Power supply power-on and power-off detection reset circuit, chip and electronic equipment |
| CN117749150A (en) * | 2024-02-19 | 2024-03-22 | 北京中天星控科技开发有限公司成都分公司 | Quick and slow power-on reset circuit |
| CN117749150B (en) * | 2024-02-19 | 2024-04-19 | 北京中天星控科技开发有限公司成都分公司 | Quick and slow power-on reset circuit |
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Application publication date: 20140312 |