CN202772848U - Fully third generation telecommunication (3G) complementary metal oxide semiconductor (CMOS) difference low noise amplifier based on controllable active inductor - Google Patents

Abstract

A fully third generation telecommunication (3G) complementary metal oxide semiconductor (CMOS) difference low noise amplifier based on a controllable active inductor can be applied in front-end circuits of receivers of a wideband code division multiple access (WCDMA), a code division multiple access (CDMA) 2000, a time division-synchronization code division multiple access (TD-SCDMA) and Bluetooth. The fully 3G CMOS difference low noise amplifier is mainly composed of an input impedance matching circuit, an inductor negative feedback cascode amplifying circuit with a source electrode, and an output impedance matching circuit. The output impedance matching circuit is composed of a grid electrode inductor, a stray capacitor of a common source pipe and a source electrode inductor. The amplifying circuit ensures high degree of linearity, low noise and high gains of the circuit through utilization of negative feedback of the source electrode inductor and positive feedback of the capacitor. The output impedance matching circuit is formed by parallel connection of a launch control (LC) resonance network and a resistor to realize output impedance matching. The active inductor is used as the inductor. By means of changing bias current of the active inductor, the low noise amplifier is enabled to work at different frequency so as to realize amplification of signals of the WCDMA, the CDMA 2000, the TD-SCDMA and the Bluetooth.

Description

A kind of full 3G CMOS differential low noise amplifier based on the Controllable Active inductance

Technical field

The invention belongs to wireless communication technology field, relate to a low noise amplifier, be specifically related to one based on the full 3G CMOS differential low noise amplifier of Controllable Active inductance.

Background technology

Along with appearance and the development of 3G (Third Generation) Moblie technology (3rd-generation, 3G), our daily life has been come in 3G communication.Wireless communication field in China mainly contains three kinds of 3G communication standards at present: the WCDMA communication standard that CHINAUNICOM uses, the CDMA2000 communication standard that China Telecom uses, and the TD-SCDMA communication standard of China Mobile's use.These three kinds of standards at the downstream frequency of China are respectively: WCDMA is 2130-2145MHz, and CDMA2000 is 2110-2125MHz, and TD-SCDMA is 2010-2025MHZ.Along with the increase of global synchronization roaming and integrated mobile phone demand, integrated a plurality of communication standards are just becoming a kind of inexorable trend on a mobile phone terminal.The existing a lot of integrated mobile phone of two standards on the current mobile phone market, such as WCDMA+GSM, TD-SWCDMA+GSM, CDMA+CDMA2000 or CDMA2000+GSM etc.; Also there is the mobile phone of multimode to occur, such as WCDMA+GSM+CDMA2000+CDMA, but just for compatible Generation Mobile Telecommunication System standard, do not realize integrated all 3G communication standards.In addition, bluetooth (Bluetooth) host-host protocol is as a kind of common wireless communication technology, be mainly used in carrying out between mobile phone, wireless headset, notebook computer and the relevant peripheral hardware wireless messages exchange, its operating frequency is 2.4GHz, as a kind of very useful Wireless Data Transmission instrument, being integrated in that right and wrong are usually seen on the mobile phone terminal, also is very necessary.

Research about active inductance has had a lot, compares with on-chip spiral inductor, the characteristics such as area is little, quality factor is high, controllability is good that it has.Accompanying drawing 1 has provided the circuit diagram of Controllable Active inductance.Can change its equivalent inductance value by the bias current that changes active inductance, be used for the impedance matching under the various criterion.

In order to solve deficiency of the prior art, the present invention is mainly based on 3G communication standard and Bluetooth standard, provide an energy compatible WCDMA, CDMA2000, TD-SCDMA and four kinds of communication standards of Bluetooth based on Controllable Active inductance CMOS differential low noise amplifier.

Summary of the invention

In view of the deficiency that prior art exists, purpose of the present invention aims to provide the CMOS differential low noise amplifier of a kind of controlled, full 3G, low-power consumption, small size, and this amplifier realizes having the advantages such as noise is little, gain is high, the linearity is good based on CMOS technique.

The present invention is achieved through the following technical solutions:

A kind of full 3G CMOS differential low noise amplifier based on the Controllable Active inductance, it comprises input impedance matching circuit, amplifying circuit and output impedance match circuit; It is characterized in that: described input impedance matching circuit is used for reception from the signal of antenna and realizes WCDMA, CDMA2000, TD-SCDMA and four substandard input impedance couplings of Bluetooth; Described amplifying circuit is connected between described input impedance matching circuit and the described output impedance match circuit, is used for amplifying the signal that described input impedance circuit receives; Described output impedance match circuit is connected between described amplifying circuit and the output to mate the output impedance of described four standards, and exports final output signal;

Described amplifying circuit is the cascodes with source inductance negative feedback and electric capacity positive feedback, and in the place's parallel connection of common bank tube a positive feedback electric capacity; Described amplifying circuit comprises a NMOS pipe M1, the 2nd NMOS pipe M2, the 3rd NMOS pipe M3, the 4th NMOS pipe M4, the first capacitor C f1, the second capacitor C f2 and the first inductance L s, wherein the first inductance L s is as source negative feedback, the first capacitor C f1 and the second capacitor C f2 are as positive feedback electric capacity, the one NMOS pipe M1, the 2nd NMOS pipe M2 is the difference input pipe, and the 3rd NMOS pipe M3, the 4th NMOS pipe M4 is current source load;

Described input impedance matching circuit comprises the second inductance L g1 and the 3rd inductance L g2, and the end of the second inductance L g1 is used for the anode input of differential signal, and the other end links to each other with the grid of M1; The end of the 3rd inductance L g2 is used for the negative terminal input of differential signal, and the other end links to each other with the grid of the 3rd NMOS pipe M3;

Described output impedance match circuit comprises the first resistance R d1, the second resistance R d2, the 4th inductance L d1, the 5th inductance L d2, the 3rd capacitor C out1 and the 4th capacitor C out2;

Wherein, the grid of the 2nd NMOS pipe M2 links to each other with the first bias voltage Vdc1, the drain terminal of the 2nd NMOS pipe M2 is connected with the other end of the first capacitor C f1, and tell three branch roads and link to each other with the end of the 3rd capacitor C out1 with the first resistance R d1, the 4th inductance L d1 respectively, the other end of the first resistance R d1, the 4th inductance L d1 is connected on the power supply Vdd jointly, and the other end of the 3rd capacitor C out1 links to each other with the anode of signal output part; The source electrode of drain electrode difference the 4th NMOS pipe M4 of the 3rd NMOS pipe M3 and the end of the second capacitor C f2 link to each other, the grid of the 4th NMOS pipe M4 links to each other with the second bias voltage Vdc2, the drain terminal of the 4th NMOS pipe M4 is connected with the other end of Cf2, and tell three branch roads and link to each other with the end of the 4th capacitor C out2 respectively at the second resistance R d2, the 5th inductance L d2, the other end of the second resistance R d2 and the 5th inductance L d2 is connected on the power supply Vdd jointly, and the other end of the 4th capacitor C out2 links to each other with the negative terminal of signal output part; Described input impedance matching circuit is mated the input impedance of described four standards, when inputting the signal of different frequency, changes the equivalent inductance value of active inductance by the bias current that changes active inductance, to realize the input impedance coupling of described four standards.

The present invention also provides:

Described electric capacity is mos capacitance.Described mos capacitance is that the grid of the mos capacitance of metal-oxide-semiconductor forms with the source electrode that links together, drain electrode, substrate, and its capacitance is by the wide and long decision of metal-oxide-semiconductor.Described inductance is active inductance.Described active inductance adopts MOS technique to realize.

Description of drawings

Fig. 1: the circuit diagram of Controllable Active inductance in the prior art.

Fig. 2: the full 3G CMOS differential low noise amplifier based on the Controllable Active inductance provided by the invention.

Fig. 3: the simulation result of Controllable Active induction quality factor Q in the prior art.

Fig. 4: the S11 parameters simulation result of the full 3G CMOS differential low noise amplifier based on the Controllable Active inductance provided by the invention.

Fig. 5: the S12 parameters simulation result of the full 3G CMOS differential low noise amplifier based on the Controllable Active inductance provided by the invention.

Fig. 6: the S21 parameters simulation result of the full 3G CMOS differential low noise amplifier based on the Controllable Active inductance provided by the invention.

Fig. 7: the S22 parameters simulation result of the full 3G CMOS differential low noise amplifier based on the Controllable Active inductance provided by the invention.

Fig. 8: the noise factor NF simulation result of the full 3G CMOS differential low noise amplifier based on the Controllable Active inductance provided by the invention.

Embodiment

The invention will be further described below in conjunction with concrete accompanying drawing and case study on implementation.

The full 3G CMOS differential low noise amplifier based on the Controllable Active inductance of the present invention's design, it is the difference narrow-band low-noise amplifier of compatible WCDMA, a CDMA2000, TD-SCDMA and four wireless communication standards of Bluetooth, difference according to each standard operation frequency, bias current by the control active inductance, and then the equivalent inductance value of control active inductance, again in conjunction with the parasitic capacitance of common source pipe, realize the input impedance coupling of low noise amplifier under various criterion, it can be operated under the corresponding wireless communication standard.In addition, the low noise amplifier of the present invention's design adopts controlled active inductance, make circuit multiplexer reach maximization, therefore not only have the advantages such as low-power consumption, small size, low cost, and have the advantages such as low noise, high-gain, low input reflection coefficient and high linearity.

The present invention design based on the circuit theory of the full 3G CMOS differential low noise amplifier of Controllable Active inductance as shown in Figure 2, comprise input impedance matching circuit, amplifying circuit and output impedance match circuit.

Described input impedance matching circuit comprises the first active inductance Ls, the second active inductance Lg1, the 3rd active inductance Lg2.Input impedance matching circuit changes the equivalent inductance value of active inductance by the bias current that changes the Controllable Active inductance, thereby realizes the input impedance coupling under the various criterion.

Described amplifying circuit for the band source inductance negative feedback cascodes and in the place's parallel connection of common bank tube a positive feedback electric capacity, comprise NMOS pipe M1, the 2nd NMOS manages M2, the 3rd NMOS manages M3, the 4th NMOS manages M4, the first inductance L s, the first capacitor C f1 and the second capacitor C f2, wherein Ls is as source negative feedback, Cf1 and Cf1 are positive feedback electric capacity, M1, M3 is the difference input pipe, M2, M4 is current source load, wherein Ls realizes source negative feedback, in order to improve the linearity of circuit, reduce circuit noise, Cf1 and Cf2 realize the positive feedback of circuit, in order to promote the gain of circuit.

Described output impedance match circuit comprises the first resistance R d1, the second resistance R d2, the 4th inductance L d1, the 5th inductance L d2, the 3rd capacitor C out1, the 4th capacitor C out2, in order to realize the output impedance coupling under the different frequency.

The concrete connected mode of circuit is: the end of inductance L g1 is used for the anode input of differential signal, the other end links to each other with the grid of M1, the drain electrode of M1 links to each other with the source electrode of M2 and the end of Cf1 respectively, the grid of M2 links to each other with bias voltage Vdc1, the drain terminal of M2 is connected with the other end of Cf1, tell again three branch roads and link to each other with the end of Rd1, Ld1 and Cout1 respectively, the other end of Rd1 and Ld1 is connected on the Vdd jointly, and the other end of Cout1 links to each other with the anode of signal output part; The end of inductance L g2 is used for the negative terminal input of differential signal, the other end links to each other with the grid of M3, the source electrode of the drain electrode difference M4 of M3 and the end of Cf2 link to each other, the grid of M4 links to each other with bias voltage Vdc2, the drain terminal of M4 is connected with the other end of Cf2, tell again three branch roads and link to each other respectively at the end of Rd2, Ld2 and Cout2, the other end of Rd2 and Ld2 is connected on the Vdd jointly, and the other end of Cout2 links to each other with the negative terminal of signal output part.

Amplifying circuit adopt the band degenerative cascodes of source inductance and in the place's parallel connection of common bank tube a positive feedback electric capacity, adopt the source inductance negative feedback, can reduce system noise, improve the system linearity degree; Adopt the electric capacity positive feedback, can improve amplifier gain, and not increase the dc power of system.

The output impedance match circuit uses the LC resonant network in parallel with resistance, to reduce the ghost effect of resistance under high frequency, realizes the broadband coupling.

Specific works mechanism is as follows:

1, inductance L g1, inductance L g2 and inductance L s are the shared active inductances under the various criterion, when guaranteeing the input impedance coupling, reach the purpose that reduces circuit area by the common circuit element.The equivalent inductance value l of its inductance _EqWith equivalent resistance r _EqBe respectively

$l_{\mathrm{eq}}=\frac{g_{m2}{g}_{m3}{c}_{\mathrm{gs}2}+{\mathrm{\&omega;}}^2{c}_{\mathrm{gs}2}^2{c}_{\mathrm{gs}3}({\mathrm{<figure-callout\; id="3"\; label="Rg\; ds"\; filenames="HSA00000775314200011.png"\; state="\{\{state\}\}">Rg</figure-callout>}}_{\mathrm{ds}}+1)}{g_{m2}^2{g}_{m3}{g}_{m1}+{\mathrm{\&omega;}}^2{g}_{m3}{g}_{m2}{c}_{\mathrm{gs}2}^2}---\left(1\right)$

$r_{\mathrm{eq}}=\frac{g_{m2}{g}_{\mathrm{ds}3}{g}_{\mathrm{ds}1}+{\mathrm{\&omega;}}^2(g_{m3}{c}_{\mathrm{gs}2}^2-g_{m2}{c}_{\mathrm{gs}2}{c}_{\mathrm{gs}3}({\mathrm{<figure-callout\; id="3"\; label="Rg\; ds"\; filenames="HSA00000775314200011.png"\; state="\{\{state\}\}">Rg</figure-callout>}}_{\mathrm{ds}}+1))}{g_{m2}^2{g}_{m3}{g}_{m1}+{\mathrm{\&omega;}}^2{g}_{m3}{g}_{m1}{c}_{\mathrm{gs}2}^2}---\left(2\right)$

Wherein, g _M1, g _M2And g _M3Respectively transistor M1, the mutual conductance of M2 and M3; C _Gs2And C _Gs3The grid source electric capacity of transistor M2 and M3; ω is operating frequency; R is negative feedback resistor; g _Ds1For leaking mutual conductance in the source of M1.By changing the bias current I of active inductance ₁And I ₂, can change each transistorized mutual conductance, and then equivalent inductance value and the quality factor of control active inductance.The simulation result of Controllable Active induction quality factor Q as shown in Figure 3.

2, be by changing the bias current of active inductance based on the input impedance of the full 3G CMOS differential low noise amplifier of Controllable Active inductance, and then change that the equivalent inductance value of active inductance realizes.The input impedance Z of this low noise amplifier _LnFor

$Z_m=s(L_s+L_{g\mathrm{1,2}})+\frac{1}{s{C}_{\mathrm{gs}}}+\frac{g_{m\mathrm{1,3}}}{c_{\mathrm{gs}}}{L}_s---\left(3\right)$

Wherein, g _M1,3The mutual conductance of expression transistor M1 and M3, s=j ω, j are imaginary unit, ω is the frequency of input signal, C _GsThe grid source electric capacity of expression M1 and M3.For guaranteeing that input impedance is 50 Ω under each frequency range, require following formula (2) and formula (3) to set up:

$\mathrm{\&omega;}(L_{g\mathrm{1,2}}+L_s)=\frac{1}{\mathrm{\&omega;}{C}_{\mathrm{gs}}}---\left(4\right)$

$Z_m=\frac{g_{m\mathrm{1,3}}}{C_{\mathrm{gs}}}{L}_s=50\mathrm{\&Omega;}---\left(5\right)$

3, the output impedance matching networks Z of the low noise amplifier shown in the accompanying drawing 2 _OutFor

$Z_{\mathrm{out}}=\frac{1}{{\mathrm{sC}}_{\mathrm{out}\mathrm{1,2}}}+\frac{{\mathrm{sR}}_{d\mathrm{1,2}}{L}_{d\mathrm{1,2}}}{R_{d\mathrm{1,2}}+{\mathrm{sL}}_{d\mathrm{1,2}}}---\left(6\right)$

Because sC under corresponding four operating frequencies _Out1,2And sL _D1,2Very large, Z then _{Out ≈ Rd1,2}, therefore can eliminate R _D1,2The parasitic capacitance of resistance and parasitic resistance effect obtain the output impedance with frequency-independent, realize the output impedance coupling under four frequencies.

4, the linearity of low noise amplifier shown in the accompanying drawing 2 can be with inputting three rank node IIP ₃Represent, when transistor M1, M2, M3 and M4 are operated in the saturation region, three rank node IIP ₃For

IIP ₃≈V _gs1，3-V _th1，2 (7)

Wherein, V _Gs1,3The gate source voltage of transistor M1 and M3, V _Th1,3It is the threshold voltage of transistor M1 and M3.

5, the present invention design based on the simulation result of S11, S12, S21, S22 parameter and the noise factor NF of the full 3G CMOS differential low noise amplifier of Controllable Active inductance respectively such as accompanying drawing 4 to shown in the accompanying drawing 8.

Than prior art, the present invention has following beneficial effect:

1, realized the signal under WCDMA, CDMA2000, TD-SCDMA and four wireless communication standards of Bluetooth is amplified;

2, the inductance in the low noise amplifier is realized by the Controllable Active inductance, makes the circuit multiplexer maximization, has significantly reduced chip area, has simplified technique, has reduced cost;

3, in the low noise amplifier, introduce positive feedback electric capacity in the source of M2 and M4 with between leaking, not only improved circuit gain, and do not increase the dc power of circuit; Because the positive feedback of introducing is on common bank tube, can not cause the unstable of circuit;

4, the output impedance match circuit of low noise amplifier has been realized the stable of output impedance by the LC resonant network.

Flourish along with the increasing and mobile phone market of wireless communication standard, developing full 3G CMOS differential low noise amplifier is a kind of inevitable development trend, therefore, a kind of full 3G CMOS differential low noise amplifier based on the Controllable Active inductance of the present invention's proposition has the very strong market competitiveness.

Explanation is at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although with reference to preferred embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from aim and the scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.

Claims (5)

1. full 3G CMOS differential low noise amplifier based on the Controllable Active inductance, it comprises input impedance matching circuit, amplifying circuit and output impedance match circuit; It is characterized in that: described input impedance matching circuit is used for reception from the signal of antenna and realizes WCDMA, CDMA2000, TD-SCDMA and four substandard input impedance couplings of Bluetooth; Described amplifying circuit is connected between described input impedance matching circuit and the described output impedance match circuit, is used for amplifying the signal that described input impedance circuit receives; Described output impedance match circuit is connected between described amplifying circuit and the output to mate the output impedance of described four standards, and exports final output signal;

Described amplifying circuit is the cascodes with source inductance negative feedback and electric capacity positive feedback; Described amplifying circuit comprises a NMOS pipe M1, the 2nd NMOS pipe M2, the 3rd NMOS pipe M3, the 4th NMOS pipe M4, the first capacitor C f1, the second capacitor C f2 and the first inductance L s, wherein the first inductance L s is as source negative feedback, the first capacitor C f1 and the second capacitor C f2 are as positive feedback electric capacity, the one NMOS pipe M1, the 2nd NMOS pipe M2 is the difference input pipe, and the 3rd NMOS pipe M3, the 4th NMOS pipe M4 is current source load;

Described input impedance matching circuit comprises the second inductance L g1 and the 3rd inductance L g2, and the end of the second inductance L g1 is used for the anode input of differential signal, and the other end links to each other with the grid of NMOS pipe M1; The end of the 3rd inductance L g2 is used for the negative terminal input of differential signal, and the other end links to each other with the grid of the 3rd NMOS pipe M3;

Described output impedance match circuit comprises the first resistance R d1, the second resistance R d2, the 4th inductance L d1, the 5th inductance L d2, the 3rd capacitor C out1 and the 4th capacitor C out2;

The grid of described the 2nd NMOS pipe M2 links to each other with the first bias voltage Vdc1, the drain terminal of the 2nd NMOS pipe M2 is connected with the other end of the first capacitor C f1, and tell three branch roads and link to each other with the end of the 3rd capacitor C out1 with the first resistance R d1, the 4th inductance L d1 respectively, the other end of the first resistance R d1, the 4th inductance L d1 is connected on the power supply Vdd jointly, and the other end of the 3rd capacitor C out1 links to each other with the anode of signal output part; The source electrode of drain electrode difference the 4th NMOS pipe M4 of the 3rd NMOS pipe M3 and the end of the second capacitor C f2 link to each other, the grid of the 4th NMOS pipe M4 links to each other with the second bias voltage Vdc2, the drain terminal of the 4th NMOS pipe M4 is connected with the other end of Cf2, and tell three branch roads and link to each other with the end of the 4th capacitor C out2 respectively at the second resistance R d2, the 5th inductance L d2, the other end of the second resistance R d2 and the 5th inductance L d2 is connected on the power supply Vdd jointly, and the other end of the 4th capacitor C out2 links to each other with the negative terminal of signal output part;

Described input impedance matching circuit is mated the input impedance of described four standards, when inputting the signal of different frequency, changes the equivalent inductance value of active inductance by the bias current that changes active inductance, to realize the input impedance coupling of described four standards.

2. the full 3G CMOS differential low noise amplifier based on the Controllable Active inductance according to claim 1, it is characterized in that: described the first inductance L s, the second inductance L g1, the 3rd inductance L g2, the 4th inductance L d1 and the 5th inductance L d2 are controlled active inductance.

3. the full 3G CMOS differential low noise amplifier based on the Controllable Active inductance according to claim 2, it is characterized in that: described active inductance is MOS technique active inductance.

4. the full 3G CMOS differential low noise amplifier based on the Controllable Active inductance according to claim 1, it is characterized in that: described the first capacitor C f1, the second capacitor C f2, the 3rd capacitor C out1 and the 4th capacitor C out2 are mos capacitance.

5. the full 3G CMOS differential low noise amplifier based on the Controllable Active inductance according to claim 4, it is characterized in that: described mos capacitance is that the grid of the mos capacitance of metal-oxide-semiconductor forms with the source electrode that links together, drain electrode, substrate, and its capacitance is by the wide and long decision of metal-oxide-semiconductor.

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