CN202663360U - High-speed phase splitting circuit with band spreading function - Google Patents
High-speed phase splitting circuit with band spreading function Download PDFInfo
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Abstract
The utility model belongs to the communication circuit field, relates to a high-speed phase splitting circuit with a band spreading function and aims at removing limit of trans-impedance amplifier bandwidth in the existing phase splitting circuit to work frequency of a head amplifier. The high-speed phase splitting circuit with the band spreading function comprises a first P-channel metal oxide semiconductor (PMOS) transistor M1, a resistor R1, a resistor R 2, a phase splitting amplifier and an integrator. The phase splitting amplifier is composed of a first amplifier A1 and a second amplifier A 2 in cascading mode. The integrator is composed of a third amplifier A3, a resistor R3, a resistor R4 and a capacitor C1. A source electrode of the first PMOS transistor M1 is connected with a power supply through the resistor R1, a drain electrode of the first PMOS transistor M1 is grounded through the resistor R 2, and the source electrode of the first PMOS transistor M1 is further connected with a normal-phase input end of the first amplifier A1. Two output ends of the second amplifier A 2 are respectively connected with two input ends of the integrator, and the output end of the integrator is connected with a reverse-phase input end of the first amplifier A1.
Description
Technical field
The utility model relates to a kind of high speed phase splitting circuit for the optical fiber preamplifier, this phase place division circuit application have the phase place splitting amplifier of band spreading function, improve the operating frequency of preamplifier.
Background technology
Optical fiber communication is take light as information carrier, and optical fiber is as a kind of communications mode of transmission medium, have bandwidth height, loss low, be subjected to the advantages such as outside electromagnetic interference is little, become the principal mode of network service.Optical transceiver module is the core devices of Optical Access Network, mainly is comprised of receiver module and transmitter module two parts.Wherein transmitter module mainly is comprised of laser drive circuit and laser diode (LD) two parts, the signal of telecommunication that laser diode sends the user is transformed into light signal to be launched, and drive circuit provides drive current to determine power output and speed for laser diode.Receiver module mainly is comprised of several parts such as photodiode (PD), preamplifier and limiting amplifiers, photodiode receives the light signal of Internet Transmission and to the current signal of converting, and preamplifier is enlarged into voltage signal with this current signal.Limiting amplifier further amplifies the output signal of preamplifier, becomes the digital signal that satisfies user's amplitude requirement.
Preamplifier and photodiode work basic principle as shown in Figure 1, wherein photodiode receives the light signal of Internet Transmission, and this light signal is transformed into corresponding with it current signal I
INBe input to preamplifier.C among Fig. 1
DBe the equivalent parasitic capacitances of photodiode, part is preamplifier in the dotted line frame.Preamplifier mainly is comprised of trans-impedance amplifier and phase place division circuit two parts.Trans-impedance amplifier is by amplifier A and feedback resistance R
FCommon formation is transformed into single-ended voltage signal V with the current signal of inputting
O_TIAOutput.But single-ended output signal is easy to be subject to the impact of electric source disturbance and noise, causes the erroneous judgement to output signal.For this reason, the preamplifier of present industrial extensive use has all been introduced phase place division circuit in the back of trans-impedance amplifier, the single-ended signal of trans-impedance amplifier output is transformed into the form of difference, to improve signal for the inhibition ability of power supply and common-mode voltage variation.Generally speaking, phase place division circuit only is transformed into the differential signal with 180 degree phase differences with the single-ended signal of input, substantially can not have influence on gain and the operating frequency of preamplifier.Be that the important indicators such as the gain of preamplifier and bandwidth are determined by the gain of trans-impedance amplifier and the parameters such as parasitic capacitance of photodiode.Therefore, the trans-impedance amplifier bandwidth becomes the Main Bottleneck of the whole preamplifier operating frequency of restriction.
Phase place in traditional fiber preamplifier division circuit, generally be by with input signal through a low pass filter to obtain its common-mode voltage.But the electric capacity of this low pass filter is all very large, and to obtain lower cut-off frequency, this needs more chip area, and the response time of this low pass filter also can be longer.Therefore, the equal situation of two ends common-mode voltage inaccuracy of phase place splitting amplifier often can occur, cause common-mode voltage imbalance or two paths of differential signals phase place appearance skew to occur.Some other solution is also arranged simultaneously, Chinese patent " high speed phase splitting circuit " for example, its publication number is CN101626232, the open date is on January 13rd, 2010, a kind of phase place division circuit of high speed has been proposed, its phase place division circuit is by the phase place splitting amplifier and diminish integrator etc. and partly consist of, it diminishes the integrator input signal from the output of phase place splitting amplifier, to produce the common-mode voltage of phase place splitting amplifier input, the phase place splitting amplifier is amplified the single-ended signal of input with the difference of the common-mode voltage that diminishes integrator output, obtain having the differential signal of 180 degree phase differences.But there is following weak point in this scheme: at first, this phase place division circuit does not possess the frequency expansion function, can't improve the operating frequency of whole preamplifier.Secondly, this diminishes integrator needs a linear resistance in parallel with integrating capacitor, the low-frequency gain that this has improved to a great extent the area of chip and has reduced this amplifier.The 3rd, added compensating resistance at the in-phase input end that diminishes integrator, to compensate the difference between current of its homophase and end of oppisite phase.But because the existence of course of processing random mismatch, compensating resistance can't be realized accurately equating with the linear resistance that diminishes integrator, deviation appears in this output common mode voltage that can cause diminishing integrator, so that obvious DC deviation appears in the output difference sub-signal of phase place splitting amplifier, late-class circuit is produced unnecessary DC maladjustment, cause Optical Receivers erroneous judgement to occur.
Summary of the invention
The utility model purpose is in order to solve trans-impedance amplifier bandwidth in the existing phase place division circuit to the restriction of preamplifier operating frequency, proposed a kind of phase place division circuit with band spreading function, this phase place division circuit can improve the operating frequency of preamplifier.
High speed phase splitting circuit with band spreading function described in the utility model, it comprises a PMOS transistor M1, resistance R 1, resistance R 2, phase place splitting amplifier sum-product intergrator,
The phase place splitting amplifier is comprised of the first amplifier A1 and the second amplifier A2 cascade,
Integrator is comprised of the 3rd amplifier A3, resistance R 3, resistance R 4 and capacitor C 1,
One termination power of resistance R 1 VDD! The other end of resistance R 1 connects the source electrode of a PMOS transistor M1 and the in-phase input end VIP of the first amplifier A1 simultaneously, the grid of the one PMOS transistor M1 is as trans-impedance amplifier output signal VO_TIA receiving terminal, the end of the drain electrode contact resistance R2 of the one PMOS transistor M1, the other end of resistance R 2 connects GND!
The inverting input VIN of the first amplifier A1 connects the output VCM of the 3rd amplifier A3,
The end of the reversed-phase output VON contact resistance R4 of the second amplifier A2, the other end of resistance R 4 connects the in-phase input end of the 3rd amplifier A3,
The end of the in-phase output end VOP contact resistance R3 of the second amplifier A2, the other end of resistance R 3 connects the inverting input of the 3rd amplifier A3,
Capacitor C 1 is connected between the inverting input and output of the 3rd amplifier A3.
The first amplifier A1 comprises the first nmos pass transistor MN1_A1, the second nmos pass transistor MN2_A1, the 3rd nmos pass transistor MN3_A1, the 4th nmos pass transistor MN4_A1, the 5th nmos pass transistor MN5_A1, the 6th nmos pass transistor MN6_A1, resistance R B_A1, resistance R S1_A1, resistance R S2_A1 and resistance R CM_A1
The end of resistance R B_A1 connect power vd D! , the other end of resistance R B_A1 connects the grid of the 6th nmos pass transistor MN6_A1 and the common port of drain electrode thereof, the source electrode of the 6th nmos pass transistor MN6_A1 connect GND!
The end of resistance R CM_A1 connect power vd D! , the other end of resistance R CM_A1 connects the drain electrode common port of the 3rd nmos pass transistor MN3_A1 and the 4th nmos pass transistor MN4_A1;
The end of the grid contact resistance RS1_A1 of the 3rd nmos pass transistor MN3_A1, the other end of the other end contact resistance RB_A1 of resistance R S1_A1;
The source electrode of the 3rd nmos pass transistor MN3_A1 be connected the connection common port of drain electrode of nmos pass transistor MN1_A1 as the in-phase output end VOP1 of the first amplifier A1; The grid of the first nmos pass transistor MN1_A1 is as the inverting input VIN of the first amplifier A1, the first nmos pass transistor MN1_A1 be connected the source electrode common port of nmos pass transistor MN2_A1 and connect the drain electrode of the 5th nmos pass transistor MN5_A1, the grid of the 5th nmos pass transistor MN5_A1 is as the first amplifier A1 tail current bias voltage input, and the source electrode of the 5th nmos pass transistor MN5_A1 connects GND!
The connection common port of the drain electrode of the second nmos pass transistor MN2_A1 and the source electrode of the 4th nmos pass transistor MN4_A1 is as the reversed-phase output VON1 of the first amplifier A1, and the grid of the second nmos pass transistor MN2_A1 is as the in-phase input end VIP of the first amplifier A1;
The end of the grid contact resistance RS2_A1 of the 4th nmos pass transistor MN4_A1, the other end of the other end contact resistance RB_A1 of resistance R S2_A1.
The second amplifier A2 comprises the 7th nmos pass transistor MN1_A2, the 8th nmos pass transistor MN2_A2, the 9th nmos pass transistor MN3_A2, the 2nd PMOS transistor MP1_A2, the 3rd PMOS transistor MP2_A2, resistance R L1_A2, resistance R L2_A2, resistance R C_A2, capacitor C L1_A2 and capacitor C L2_A2
The end of resistance R C_A2 connect power vd D! , the other end of resistance R C_A2 connects the source electrode common port of the 2nd PMOS transistor MP1_A2 and the 3rd PMOS transistor MP2_A2,
Capacitor C L1_A2 is connected between the source electrode and grid of the 2nd PMOS transistor MP1_A2, and resistance R L1_A2 is connected between the drain and gate of the 2nd PMOS transistor MP1_A2,
Capacitor C L2_A2 is connected between the source electrode and grid of the 3rd PMOS transistor MP2_A2, and resistance R L2_A2 is connected between the drain and gate of the 3rd PMOS transistor MP2_A2,
The drain electrode of the drain electrode of the 2nd PMOS transistor MP1_A2 and the 7th nmos pass transistor MN1_A2 connects common port as the in-phase output end VOP of the second amplifier A2, and the grid of the 7th nmos pass transistor MN1_A2 is as the inverting input VIN2 of the second amplifier A2;
The drain electrode of the 3rd PMOS transistor MP2_A2 is connected common port as the reversed-phase output VON of the second amplifier A2 with the drain electrode of the 8th nmos pass transistor MN2_A2, and the grid of the 8th nmos pass transistor MN2_A2 is as the in-phase input end VIP2 of the second amplifier A2;
The source electrode of the source electrode of the 7th nmos pass transistor MN1_A2 and the 8th nmos pass transistor MN2_A2 connects, and the source electrode of the 7th nmos pass transistor MN1_A2 also is connected with the drain electrode of the 9th nmos pass transistor MN3_A2,
The grid of the 9th nmos pass transistor MN3_A2 is as the tail current bias voltage input of the second amplifier A2;
The source electrode of the 9th nmos pass transistor MN3_A2 connect GND!
Advantage of the present utility model: the utility model has designed the phase place division circuit with band spreading function, it mainly is comprised of phase place splitting amplifier sum-product intergrator two parts, wherein this phase place splitting amplifier is comprised of the amplifier with frequency expansion function of two cascades, can expand the bandwidth of operation of phase place division circuit, and then improve the operating frequency of whole preamplifier.
Compare with the phase place division circuit of not using the band spreading function, this band spreading function is the active inductance that forms by elements such as the MOS transistor on the sheet, resistance and electric capacity, and the size of its inductance can realize by the adjustment for the resistance on the sheet and capacitance size.
Concrete effect of the present utility model is by Simulation results checking under the circuit simulation worst case.The transistor threshold voltage of the course of processing changes and can be embodied by process corner (Process Corner) variation in emulation, and (typical) transistorized threshold voltage deviation is zero in typical case, generally is called the TT situation.When transistor turns accelerated, the threshold voltage of all crystals pipe all reduced, and this is the FF pattern of process corner, and its threshold voltage reduces about 20% more in typical case; Otherwise then be the SS pattern, its threshold voltage increases about 20% than typical case.Course of processing changes in process parameters can exert an influence to factors such as transistorized threshold voltage, electron mobilities, and this also can significantly impact trans-impedance amplifier-three dB bandwidth.Table 1 has provided under the process corner situation of change, use the phase place division circuit with band spreading function and used preamplifier in the breeding situations such as having band spreading function phase place division circuit-three dB bandwidth relatively.As can be seen from Table 1, when the FF of course of processing situation occured, the bandwidth of preamplifier was minimum, only has 1.63GHz, after having used the phase place division circuit with band spreading function, the bandwidth of preamplifier has then reached 2.336GHz, and its bandwidth has been improved 706MHz.When the TT of course of processing situation occured, the bandwidth of preamplifier was 1.981GHz, used the phase place division circuit with band spreading function after, the bandwidth of preamplifier is 2.423GHz, bandwidth is improved and has been reached 442MHz.And in the SS situation, this bandwidth improvement with phase place division circuit of frequency expansion function only has 276MHz.The result of table 1 shows that this phase place division circuit with frequency expansion function can significantly improve the bandwidth of operation of preamplifier, and has reduced the rate of change of bandwidth in the situation of different process angle.
The bandwidth of preamplifier is improved under the table 1 process corner situation of change
Description of drawings
Fig. 1 is the operation principle block diagram of background technology preamplifier and photodiode;
Fig. 2 is the phase place division circuit theory diagrams with band spreading function;
The amplifier A1 circuit structure diagram that has the band spreading function in Fig. 3 phase place splitting amplifier;
The amplifier A2 circuit structure diagram that has the band spreading function in Fig. 4 phase place splitting amplifier.
Embodiment
Embodiment one: below in conjunction with Fig. 2 present embodiment is described, the described high speed phase splitting circuit with band spreading function of present embodiment, it comprises a PMOS transistor M1, resistance R 1, resistance R 2, phase place splitting amplifier sum-product intergrator,
The phase place splitting amplifier is comprised of the first amplifier A1 and the second amplifier A2 cascade,
Integrator is comprised of the 3rd amplifier A3, resistance R 3, resistance R 4 and capacitor C 1,
One termination power of resistance R 1 VDD! The other end of resistance R 1 connects the source electrode of a PMOS transistor M1 and the in-phase input end VIP of the first amplifier A1 simultaneously, the grid of the one PMOS transistor M1 is as trans-impedance amplifier output signal VO TIA receiving terminal, the end of the drain electrode contact resistance R2 of the one PMOS transistor M1, the other end of resistance R 2 connects GND!
The inverting input VIN of the first amplifier A1 connects the output VCM of the 3rd amplifier A3,
The end of the reversed-phase output VON contact resistance R4 of the second amplifier A2, the other end of resistance R 4 connects the in-phase input end of the 3rd amplifier A3,
The end of the in-phase output end VOP contact resistance R3 of the second amplifier A2, the other end of resistance R 3 connects the inverting input of the 3rd amplifier A3,
Capacitor C 1 is connected between the inverting input and output of the 3rd amplifier A3.
The one PMOS transistor M1 forms source follower, the input signal of the one PMOS transistor M1 is the output signal VO_TIA of trans-impedance amplifier, the output signal of the one PMOS transistor M1 is transferred to the phase place splitting amplifier, the phase place splitting amplifier is comprised of two amplifier A1 and A2 cascades with band spreading function, and (also being the phase place splitting amplifier) in-phase output end VOP and the reversed-phase output VON of the second amplifier A2 mainly contain two functions:
The first, the late-class circuit of preamplifier provides input voltage;
The second, both common mode voltage difference are transferred to the input of integrator.Integrator will amplify the common mode voltage difference of VOP and VON, according to amplifying the result common-mode voltage of phase place splitting amplifier inverting input VIP is adjusted, the common-mode voltage of guaranteeing the in-phase input end VIN of phase place splitting amplifier equates with VIP, realizes the function of phase place division amplifying circuit.
The circuit implementation:
A kind of phase place division circuit with band spreading function connects a phase place splitting amplifier by a source follower, and the phase place splitting amplifier connects an integrator; Its source follower, the signal that trans-impedance amplifier is exported carries out level shift; Its phase place splitting amplifier converts the single-ended signal of inputting to the both-end differential signal, and has the band spreading function; Its integrator, two inputs are connected on respectively on the output of phase place splitting amplifier, and output is connected on the inverting input of phase place splitting amplifier, for the phase place splitting amplifier provides common-mode voltage.
Described phase place splitting amplifier is comprised of the fully-differential amplifier of two cascades, for having the amplifier of band spreading function.
Embodiment two: present embodiment is described below in conjunction with Fig. 3, present embodiment is further specifying execution mode one, the first amplifier A1 comprises the first nmos pass transistor MN1_A1, the second nmos pass transistor MN2_A1, the 3rd nmos pass transistor MN3_A1, the 4th nmos pass transistor MN4_A1, the 5th nmos pass transistor MN5_A1, the 6th nmos pass transistor MN6_A1, resistance R B_A1, resistance R S1_A1, resistance R S2_A1 and resistance R CM_A1
The end of resistance R B_A1 connect power vd D! , the other end of resistance R B_A1 connects the grid of the 6th nmos pass transistor MN6_A1 and the common port of drain electrode thereof, the source electrode of the 6th nmos pass transistor MN6_A1 connect GND!
The end of resistance R CM_A1 connect power vd D! , the other end of resistance R CM_A1 connects the drain electrode common port of the 3rd nmos pass transistor MN3_A1 and the 4th nmos pass transistor MN4_A1;
The end of the grid contact resistance RS1_A1 of the 3rd nmos pass transistor MN3_A1, the other end of the other end contact resistance RB_A1 of resistance R S1_A1;
The source electrode of the 3rd nmos pass transistor MN3_A1 be connected the connection common port of drain electrode of nmos pass transistor MN1_A1 as the in-phase output end VOP1 of the first amplifier A1; The grid of the first nmos pass transistor MN1_A1 is as the inverting input VIN of the first amplifier A1, the first nmos pass transistor MN1A1 be connected the source electrode common port of nmos pass transistor MN2_A1 and connect the drain electrode of the 5th nmos pass transistor MN5_A1, the grid of the 5th nmos pass transistor MN5_A1 is as the first amplifier A1 tail current bias voltage input, and the source electrode of the 5th nmos pass transistor MN5_A1 connects GND!
The connection common port of the drain electrode of the second nmos pass transistor MN2_A1 and the source electrode of the 4th nmos pass transistor MN4_A1 is as the reversed-phase output VON1 of the first amplifier A1, and the grid of the second nmos pass transistor MN2_A1 is as the in-phase input end VIP of the first amplifier A1;
The end of the grid contact resistance RS2_A1 of the 4th nmos pass transistor MN4_A1, the other end of the other end contact resistance RB_A1 of resistance R S2_A1.
Resistance R B_A1 among Fig. 3 and the 6th transistor MN6_A1 have formed biasing circuit, produce a bias voltage VB2, and its voltage swing can be expressed as
VB2＝VGS
MN6_A1＝VDD-I*R
RB_A1 (1)
In the formula (1), VGS
MN6_A1Be voltage between the gate-to-source of the 6th transistor MN6_A1, R
RB_A1Resistance for resistance R B_A1.
Bias voltage VB2 provides gate bias voltage for the 3rd nmos pass transistor MN3_A1 and the 4th nmos pass transistor MN4_A1.The first nmos pass transistor MN1_A1, the second nmos pass transistor MN2A_1, the 3rd nmos pass transistor MN3_A1, the 4th nmos pass transistor MN4_A1 and the 5th nmos pass transistor MN5_A1 have formed the agent structure of the first amplifier A1, wherein the 5th nmos pass transistor MN5_A1 grid is driven by VB1, for the first amplifier A1 provides bias current.The grid of the first nmos pass transistor MN1_A1 links to each other with the inverting input VIN of the first amplifier A1, and the 2nd NMOS MN2_A1 links to each other with in-phase input end VIP, forms the differential pair tube of the first amplifier A1.The 3rd nmos pass transistor MN3_A1 and the 4th nmos pass transistor MN4_A1 have formed, and its source electrode is connected on the bias voltage VB2 by resistance R S1_A1 and resistance R S2_A1.Formed an active inductance by the 3rd nmos pass transistor MN3_A1 and its source resistance RS1_A1, its impedance can be expressed as
Z in the formula
OutThe equiva lent impedance that the 3rd nmos pass transistor MN3_A1 sees from source electrode, g
mBe the mutual conductance of the 3rd nmos pass transistor MN3_A1, s is complex frequency, C
GSThe grid of the 3rd nmos pass transistor MN3_A1 and the capacitance of source electrode overlap capacitance, R
SThe resistance of the resistance of the 3rd nmos pass transistor MN3_A1, and R
S=R
RS1_A1, R
RS1_A1Be the resistance of resistance R S1_A1, therefore reasonable adjusting resistance R
S1_A1Resistance just can realize active inductance, and expand the working band of the first amplifier A1.
Embodiment three: present embodiment is described below in conjunction with Fig. 4, present embodiment is that execution mode one or two is described further, the second amplifier A2 comprises the 7th nmos pass transistor MN1_A2, the 8th nmos pass transistor MN2_A2, the 9th nmos pass transistor MN3_A2, the 2nd PMOS transistor MP1_A2, the 3rd PMOS transistor MP2_A2, resistance R L1_A2, resistance R L2_A2, resistance R C_A2, capacitor C L1_A2 and capacitor C L2_A2
The end of resistance R C_A2 connect power vd D! , the other end of resistance R C_A2 connects the source electrode common port of the 2nd PMOS transistor MP1_A2 and the 3rd PMOS transistor MP2_A2,
Capacitor C L1_A2 is connected between the source electrode and grid of the 2nd PMOS transistor MP1_A2, and resistance R L1_A2 is connected between the drain and gate of the 2nd PMOS transistor MP1_A2,
Capacitor C L2_A2 is connected between the source electrode and grid of the 3rd PMOS transistor MP2_A2, and resistance R L2_A2 is connected between the drain and gate of the 3rd PMOS transistor MP2_A2,
The drain electrode of the drain electrode of the 2nd PMOS transistor MP1_A2 and the 7th nmos pass transistor MN1_A2 connects common port as the in-phase output end VOP of the second amplifier A2, and the grid of the 7th nmos pass transistor MN1_A2 is as the inverting input VIN2 of the second amplifier A2;
The drain electrode of the 3rd PMOS transistor MP2_A2 is connected common port as the reversed-phase output VON of the second amplifier A2 with the drain electrode of the 8th nmos pass transistor MN2_A2, and the grid of the 8th nmos pass transistor MN2_A2 is as the in-phase input end VIP2 of the second amplifier A2;
The source electrode of the source electrode of the 7th nmos pass transistor MN1_A2 and the 8th nmos pass transistor MN2_A2 connects, and the source electrode of the 7th nmos pass transistor MN1_A2 also is connected with the drain electrode of the 9th nmos pass transistor MN3_A2,
The grid of the 9th nmos pass transistor MN3_A2 is as the tail current bias voltage input of the second amplifier A2;
The source electrode of the 9th nmos pass transistor MN3_A2 connect GND!
Among Fig. 4, the grid of the 9th nmos pass transistor MN3_A2 is driven by bias voltage VB3, determined the tail current of the second amplifier A2, the 7th nmos pass transistor MN1_A2 and the 8th nmos pass transistor MN2_A2 have formed the differential pair tube of the second amplifier A2, the grid of the 7th nmos pass transistor MN1_A2 is as the inverting input VIN2 of the second amplifier A2, the drain electrode of the 7th nmos pass transistor MN1_A2 is as the in-phase output end VOP of the second amplifier A2, the grid of the 8th nmos pass transistor MN2_A2 is as the in-phase input end VIP2 of the second amplifier A2, and the drain electrode of the 8th nmos pass transistor MN2_A2 is as the reversed-phase output VON of the second amplifier A2.
The 2nd PMOS transistor MP1_A2, resistance R L1_A2 and capacitor C L1_A2 have formed the active inductance of the second amplifier A2, and the 3rd PMOS transistor MP2_A2, resistance R L2_A2 and capacitor C L2_A2 have formed another active inductance of the second amplifier A2.Its basic principle is as follows, looks from the drain electrode of the 2nd PMOS transistor MP1_A1, has considered that the equiva lent impedance after this transistor transconductance can be expressed as
In the formula, Z
OutFor the drain electrode from the 2nd PMOS transistor MP1_A2 looks, considered the equiva lent impedance after the resistance R L1_A2 that transistor transconductance, grid connect and the capacitor C L1_A2 that grid is connected, g
mThe mutual conductance of the 2nd PMOS transistor MP1_A2, C
CL1_A2Be the capacitance of capacitor C L1_A2, R
RL1_A2Be the resistance value of resistance R L1_A2, S is complex frequency.
The size of the resistance value of therefore rational adjusting resistance RL1_A2 and the capacitance of capacitor C L1_A2 just can significantly be expanded the bandwidth of the second amplifier A2, and then realizes the bandwidth expansion function of phase place division circuit.
Claims (3)
1. have the high speed phase splitting circuit of band spreading function, it is characterized in that, it comprises a PMOS transistor M1, resistance R 1, resistance R 2, phase place splitting amplifier sum-product intergrator,
The phase place splitting amplifier is comprised of the first amplifier A1 and the second amplifier A2 cascade,
Integrator is comprised of the 3rd amplifier A3, resistance R 3, resistance R 4 and capacitor C 1,
One termination power of resistance R 1 VDD! The other end of resistance R 1 connects the source electrode of a PMOS transistor M1 and the in-phase input end VIP of the first amplifier A1 simultaneously, the grid of the one PMOS transistor M1 is as trans-impedance amplifier output signal VO_TIA receiving terminal, the end of the drain electrode contact resistance R2 of the one PMOS transistor M1, the other end of resistance R 2 connects GND!
The inverting input VIN of the first amplifier A1 connects the output VCM of the 3rd amplifier A3,
The end of the reversed-phase output VON contact resistance R4 of the second amplifier A2, the other end of resistance R 4 connects the in-phase input end of the 3rd amplifier A3,
The end of the in-phase output end VOP contact resistance R3 of the second amplifier A2, the other end of resistance R 3 connects the inverting input of the 3rd amplifier A3,
Capacitor C 1 is connected between the inverting input and output of the 3rd amplifier A3.
2. described high speed phase splitting circuit with band spreading function according to claim 1, it is characterized in that, the first amplifier A1 comprises the first nmos pass transistor MN1_A1, the second nmos pass transistor MN2_A1, the 3rd nmos pass transistor MN3_A1, the 4th nmos pass transistor MN4_A1, the 5th nmos pass transistor MN5_A1, the 6th nmos pass transistor MN6_A1, resistance R B_A1, resistance R S1_A1, resistance R S2_A1 and resistance R CM_A1
The end of resistance R B_A1 connect power vd D! , the other end of resistance R B_A1 connects the grid of the 6th nmos pass transistor MN6_A1 and the common port of drain electrode thereof, the source electrode of the 6th nmos pass transistor MN6_A1 connect GND!
The end of resistance R CM_A1 connect power vd D! , the other end of resistance R CM_A1 connects the drain electrode common port of the 3rd nmos pass transistor MN3_A1 and the 4th nmos pass transistor MN4_A1;
The end of the grid contact resistance RS1_A1 of the 3rd nmos pass transistor MN3_A1, the other end of the other end contact resistance RB_A1 of resistance R S1_A1;
The source electrode of the 3rd nmos pass transistor MN3_A1 be connected the drain electrode of nmos pass transistor MN1_A1 and connect common port as the in-phase output end VOP1 of the first amplifier A1; The grid of the first nmos pass transistor MN1_A1 is as the inverting input VIN of the first amplifier A1, the first nmos pass transistor MN1_A1 be connected the source electrode common port of nmos pass transistor MN2_A1 and connect the drain electrode of the 5th nmos pass transistor MN5_A1, the grid of the 5th nmos pass transistor MN5_A1 is as the first amplifier A1 tail current bias voltage input, and the source electrode of the 5th nmos pass transistor MN5_A1 connects GND!
The connection common port of the drain electrode of the second nmos pass transistor MN2_A1 and the source electrode of the 4th nmos pass transistor MN4_A1 is as the reversed-phase output VON1 of the first amplifier A1, and the grid of the second nmos pass transistor MN2_A1 is as the in-phase input end VIP of the first amplifier A1;
The end of the grid contact resistance RS2_A1 of the 4th nmos pass transistor MN4_A1, the other end of the other end contact resistance RB_A1 of resistance R S2_A1.
3. described high speed phase splitting circuit with band spreading function according to claim 1 and 2, it is characterized in that, the second amplifier A2 comprises the 7th nmos pass transistor MN1_A2, the 8th nmos pass transistor MN2_A2, the 9th nmos pass transistor MN3_A2, the 2nd PMOS transistor MP1_A2, the 3rd PMOS transistor MP2_A2, resistance R L1_A2, resistance R L2_A2, resistance R C_A2, capacitor C L1_A2 and capacitor C L2_A2
The end of resistance R C_A2 connect power vd D! , the other end of resistance R C_A2 connects the source electrode common port of the 2nd PMOS transistor MP1_A2 and the 3rd PMOS transistor MP2_A2,
Capacitor C L1_A2 is connected between the source electrode and grid of the 2nd PMOS transistor MP1_A2, and resistance R L1_A2 is connected between the drain and gate of the 2nd PMOS transistor MP1_A2,
Capacitor C L2_A2 is connected between the source electrode and grid of the 3rd PMOS transistor MP2_A2, and resistance R L2_A2 is connected between the drain and gate of the 3rd PMOS transistor MP2_A2,
The drain electrode of the drain electrode of the 2nd PMOS transistor MP1_A2 and the 7th nmos pass transistor MN1_A2 connects common port as the in-phase output end VOP of the second amplifier A2, and the grid of the 7th nmos pass transistor MN1_A2 is as the inverting input VIN2 of the second amplifier A2;
The drain electrode of the 3rd PMOS transistor MP2_A2 is connected common port as the reversed-phase output VON of the second amplifier A2 with the drain electrode of the 8th nmos pass transistor MN2_A2, and the grid of the 8th nmos pass transistor MN2_A2 is as the in-phase input end VIP2 of the second amplifier A2;
The source electrode of the source electrode of the 7th nmos pass transistor MN1_A2 and the 8th nmos pass transistor MN2_A2 connects, and the source electrode of the 7th nmos pass transistor MN1_A2 also is connected with the drain electrode of the 9th nmos pass transistor MN3_A2,
The grid of the 9th nmos pass transistor MN3_A2 is as the tail current bias voltage input of the second amplifier A2;
The source electrode of the 9th nmos pass transistor MN3_A2 connect GND!
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220304452 CN202663360U (en) | 2012-06-26 | 2012-06-26 | High-speed phase splitting circuit with band spreading function |
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| CN 201220304452 CN202663360U (en) | 2012-06-26 | 2012-06-26 | High-speed phase splitting circuit with band spreading function |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102723916A (en) * | 2012-06-26 | 2012-10-10 | 福建一丁芯光通信科技有限公司 | High-speed phase splitting circuit with band spreading function |
| WO2020082262A1 (en) * | 2018-10-24 | 2020-04-30 | 深圳市傲科光电子有限公司 | Limiting amplifier and tia circuit |
| WO2023108793A1 (en) * | 2021-12-17 | 2023-06-22 | 厦门亿芯源半导体科技有限公司 | High-speed trans-impedance amplifier having bandwidth extension characteristic within full-temperature range, and bandwidth extension method |
-
2012
- 2012-06-26 CN CN 201220304452 patent/CN202663360U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102723916A (en) * | 2012-06-26 | 2012-10-10 | 福建一丁芯光通信科技有限公司 | High-speed phase splitting circuit with band spreading function |
| WO2020082262A1 (en) * | 2018-10-24 | 2020-04-30 | 深圳市傲科光电子有限公司 | Limiting amplifier and tia circuit |
| WO2023108793A1 (en) * | 2021-12-17 | 2023-06-22 | 厦门亿芯源半导体科技有限公司 | High-speed trans-impedance amplifier having bandwidth extension characteristic within full-temperature range, and bandwidth extension method |
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