CN110690865B - High transconductance low input capacitance rail-to-rail operational amplifier - Google Patents
High transconductance low input capacitance rail-to-rail operational amplifier Download PDFInfo
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- CN110690865B CN110690865B CN201911016065.4A CN201911016065A CN110690865B CN 110690865 B CN110690865 B CN 110690865B CN 201911016065 A CN201911016065 A CN 201911016065A CN 110690865 B CN110690865 B CN 110690865B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45273—Mirror types
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45288—Differential amplifier with circuit arrangements to enhance the transconductance
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Abstract
The invention discloses a high transconductance low input capacitance rail-to-rail operational amplifier, and relates to the technical field of operational amplifiers. The invention comprises NMOS tubes mn 1-5 and PMOS tubes mp 1-7; mn2 and mn3 form an NMOS differential pair; mp1 and mp2 form a PMOS differential pair; mp3 constitutes the tail current bias; mn4, mn5 constitute a current mirror. In the rail-to-rail input operational amplifier, two stages of mirror image operational amplifiers are adopted, the first stage is a differential input pair, the width-to-length ratio is small, and the current multiple is amplified from the first stage mirror image to the output stage, so that the purpose of increasing the equivalent input transconductance of the whole operational amplifier is achieved, and the effect of small input capacitance is realized; on the premise of rail-to-rail input, the high transconductance is realized, and meanwhile, the equivalent input capacitance of the operational amplifier is reduced, so that the load on a preceding stage circuit is small, and the interference on the preceding stage circuit is small; and moreover, the equivalent input capacitance is small, and the work of high-frequency small signals is facilitated.
Description
Technical Field
The invention belongs to the technical field of operational amplifiers, and particularly relates to a high transconductance low input capacitance rail-to-rail operational amplifier.
Background
The input stage of the operational amplifier is generally required to be designed in a rail-to-rail input mode, and the total span of the amplifying circuit is preferably not changed with the input common-mode voltage, because the change of the span can cause the change of the characteristics of the circuit such as gain, speed, noise and the like.
The prior art of rail-to-rail input is shown in fig. 2, and is formed by connecting two simple differential amplifiers in parallel, wherein a differential pair of NMOS inputs and a differential pair of PMOS inputs are used as inputs, and a current mirror structure is used as a load. The disadvantage is that when a large transconductance is required, the width-to-length ratio of the input differential pair becomes large, which results in an increase in the area of the input tube, and the capacitance of the equivalent input becomes large, which results in a large load capacitance for the preceding stage circuit, and is also not favorable for the transmission of high-frequency small signals.
A rail-to-rail operational amplifier with high transconductance and low input capacitance solves the problems of high transconductance and low input capacitance on the premise of rail-to-rail input.
Disclosure of Invention
The invention aims to provide a high-transconductance low-input capacitance rail-to-rail operational amplifier, which adopts two stages of mirror image operational amplifiers in the rail-to-rail input operational amplifier, wherein the first stage is a differential input pair, the width-to-length ratio is small, and the current multiple is amplified from the first stage mirror image to the output stage, so that the purpose of enlarging the equivalent input transconductance of the whole operational amplifier is achieved, meanwhile, the input capacitance is small, and the problem provided in the background technology is solved.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention relates to a high transconductance low input capacitance rail-to-rail operational amplifier, which comprises an NMOS (N-channel metal oxide semiconductor) tube mn1, an NMOS tube mn2, an NMOS tube mn3, an NMOS tube mn4, an NMOS tube mn5, a PMOS tube mp1, a PMOS tube mp2, a PMOS tube mp3, a PMOS tube mp4, a PMOS tube mp5, a PMOS tube mp6 and a PMOS tube mp 7; the NMOS transistor mn2 and the NMOS transistor mn3 form an NMOS differential pair; the PMOS transistor mp1 and the PMOS transistor mp2 form a PMOS differential pair; the PMOS transistor mp3 forms a tail current bias; the NMOS tube mn4 and the NMOS tube mn5 form a current mirror; when the current is mirrored to a PMOS tube mp4 and an NMOS tube mn4 to an NMOS tube mn5 by the PMOS tube mp5, the current is amplified by multiple times, the width-to-length ratio of a differential pair formed by the NMOS tube mn2 and the NMOS tube mn3 is small, but when the PMOS tube mp5 is mirrored to the PMOS tube mp4 and the NMOS tube mn4 is mirrored to the NMOS tube mn5, the current is amplified by multiple times, so that large transconductance is realized, in order to realize rail-to-rail input at the same time, the current mirror pair of the NMOS tube mn4 and the NMOS tube mn5 is used for loading, and the PMOS tube mp1, the PMOS tube mp2 and the tail current of the PMOS tube mp3 of the differential pair of the PMOS tube mp4 and the NMOS tube mn5 of the PMOS tube are added to bias the PMOS tube.
Furthermore, the gates of the NMOS transistor mn2 and the NMOS transistor mn3 are respectively connected to an input voltage, the sources of the NMOS transistor mn2 and the NMOS transistor mn3 are both connected to the drain of the NMOS transistor mn1, and the source of the NMOS transistor mn1 is grounded; the gates of the PMOS transistor mp1 and the PMOS transistor mp2 are respectively connected with input voltage, and the drain of the PMOS transistor mp1 is respectively connected with the gate of the NMOS transistor mn4 and the gate of the NMOS transistor mn 5; the drain electrode of the NMOS tube mn4 is in short circuit with the grid electrode, and the source electrode is grounded.
Further, when a low level is input to enable the NMOS differential pair to enter a cut-off region, the PMOS transistor mp1, the PMOS transistor mp2, the PMOS transistor mp3, the NMOS transistor mn4 and the NMOS transistor mn5 form a simple current mirror load differential pair single-stage amplifier, and the single-stage amplifier still works when the low level is input; when the input level makes the NMOS differential pair and the PMOS differential pair in the saturation region, the two amplifiers work simultaneously.
Furthermore, the drain electrode of the PMOS tube mp5 is in short circuit with the grid electrode, and the source electrode is connected with the power supply; the drain electrode of the PMOS transistor mp5 is connected with the drain electrode of the NMOS transistor mn2, and the gate electrode of the PMOS transistor mp5 is connected with the gate electrode of the PMOS transistor mp 4.
Furthermore, the drain electrode of the PMOS tube mp6 is in short circuit with the grid electrode, and the source electrode is connected with the power supply; the drain electrode of the PMOS tube mp6 is connected with the drain electrode of the NMOS tube mn 3; the grid electrode of the PMOS tube mp6 is connected with the grid electrode of the PMOS tube mp7, and the source electrode of the PMOS tube mp7 is connected with a power supply.
Furthermore, the gate of the NMOS transistor mn4 is connected to the gate of the NMOS transistor mn5, the drain of the NMOS transistor mn4 is connected to the drain of the PMOS transistor mp7, and the source of the NMOS transistor mn4 and the source of the NMOS transistor mn5 are both grounded.
Furthermore, the drain of the PMOS tube mp4 is connected with the drain of the NMOS tube mn5, the drain of the PMOS tube mp4 and the drain of the NMOS tube mn5 are both connected with the drain of the PMOS tube mp2, and the source of the PMOS tube mp4 is connected with a power supply.
The invention has the following beneficial effects:
in the rail-to-rail input operational amplifier, two stages of mirror image operational amplifiers are adopted, the first stage is a differential input pair, the width-to-length ratio is small, and the current multiple is amplified from the first stage mirror image to the output stage, so that the purpose of increasing the equivalent input transconductance of the whole operational amplifier is achieved, and the effect of small input capacitance is realized; on the premise of rail-to-rail input, the high transconductance is realized, and meanwhile, the equivalent input capacitance of the operational amplifier is reduced, so that the load on a preceding stage circuit is small, and the interference on the preceding stage circuit is small; and moreover, the equivalent input capacitance is small, and the work of high-frequency small signals is facilitated.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a high transconductance low input capacitance rail-to-rail operational amplifier of the present invention;
fig. 2 is a schematic diagram of the prior art rail-to-rail input scheme.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the invention relates to a high transconductance low input capacitance rail-to-rail operational amplifier, which comprises an NMOS transistor mn1, an NMOS transistor mn2, an NMOS transistor mn3, an NMOS transistor mn4, an NMOS transistor mn5, a PMOS transistor mp1, a PMOS transistor mp2, a PMOS transistor mp3, a PMOS transistor mp4, a PMOS transistor mp5, a PMOS transistor mp6, and a PMOS transistor mp 7; the NMOS transistor mn2 and the NMOS transistor mn3 form an NMOS differential pair; the PMOS transistor mp1 and the PMOS transistor mp2 form a PMOS differential pair; the PMOS transistor mp3 forms a tail current bias; the NMOS tube mn4 and the NMOS tube mn5 form a current mirror; when the current is mirrored to a PMOS tube mp4 from a PMOS tube mp5 and mirrored to an NMOS tube mn5 from an NMOS tube mn4, the current is amplified by multiple times, the width-to-length ratio of a differential pair formed by the NMOS tube mn2 and the NMOS tube mn3 is small, but when the PMOS tube mp5 is mirrored to the PMOS tube mp4 and the NMOS tube mn4 is mirrored to the NMOS tube mn5, the current is amplified by multiple times, so that large transconductance is achieved, in order to achieve rail-to-rail input at the same time, the current mirrors of the NMOS tube mn4 and the NMOS tube mn5 are used for loading, and the differential pair of the PMOS tube mp1 and the PMOS tube mp2 of the PMOS input and the tail current bias tube mp3 of the PMOS input are added.
When a low level is input to enable the NMOS differential pair to enter a cut-off region, the PMOS tube mp1, the PMOS tube mp2, the PMOS tube mp3, the NMOS tube mn4 and the NMOS tube mn5 form a simple current mirror load differential pair single-stage amplifier, and the single-stage amplifier still works when the low level is input; when the input level makes both the NMOS differential pair and the PMOS differential pair in the saturation region, both amplifiers operate simultaneously.
As shown in fig. 1, the connection mode of the high transconductance low input capacitance rail-to-rail operational amplifier is specifically as follows: the gates of the NMOS transistor mn2 and the NMOS transistor mn3 are respectively connected with input voltage, the sources of the NMOS transistor mn2 and the NMOS transistor mn3 are both connected with the drain of the NMOS transistor mn1, and the source of the NMOS transistor mn1 is grounded; the gates of the PMOS transistor mp1 and the PMOS transistor mp2 are respectively connected with input voltage, and the drain of the PMOS transistor mp1 is respectively connected with the gate of the NMOS transistor mn4 and the gate of the NMOS transistor mn 5; the drain electrode of the NMOS tube mn4 is in short circuit with the grid electrode, the source electrode is grounded, the drain electrode of the PMOS tube mp5 is in short circuit with the grid electrode, and the source electrode is connected with the power supply; the drain electrode of the PMOS tube mp5 is connected with the drain electrode of the NMOS tube mn2, and the gate electrode of the PMOS tube mp5 is connected with the gate electrode of the PMOS tube mp 4; the drain electrode of the PMOS tube mp6 is in short circuit with the grid electrode, and the source electrode is connected with the power supply; the drain electrode of the PMOS tube mp6 is connected with the drain electrode of the NMOS tube mn 3; the grid electrode of the PMOS tube mp6 is connected with the grid electrode of the PMOS tube mp7, and the source electrode of the PMOS tube mp7 is connected with a power supply; the grid electrode of the NMOS tube mn4 is connected with the grid electrode of the NMOS tube mn5, the drain electrode of the NMOS tube mn4 is connected with the drain electrode of the PMOS tube mp7, and the source electrode of the NMOS tube mn4 and the source electrode of the NMOS tube mn5 are both grounded; the drain electrode of the PMOS tube mp4 is connected with the drain electrode of the NMOS tube mn5, the drain electrode of the PMOS tube mp4 and the drain electrode of the NMOS tube mn5 are both connected with the drain electrode of the PMOS tube mp2, and the source electrode of the PMOS tube mp4 is connected with a power supply.
Under the condition of temporarily not considering PMOS transistor mp1, PMOS transistor mp2 and PMOS transistor mp3, the circuit is a common NMOS differential input operational amplifier structure, the structure can make the width-length ratio of a differential pair small at an input end, so that an input capacitance is small, a load effect on a front stage is small, meanwhile, the width-length ratio of the transistor can be increased at an output stage, so that the whole OP equivalent transconductance is increased, when an input level is low and the NMOS differential pair enters a cut-off region, the functions of the PMOS transistor mp1, the PMOS transistor mp2 and the PMOS transistor mp3 are obvious, and at the moment, the PMOS transistor mp1, the NMOS transistor mn4 and the NMOS transistor mn5 form a simple current mirror load differential pair single-stage amplifier, and the single-stage amplifier can still work when the input level is low. Of course, when the input levels are such that both the NMOS differential pair and the PMOS differential pair are in the saturation region, both amplifiers are simultaneously operated.
A high transconductance low input capacitance rail-to-rail operational amplifier adopts two-stage mirror image operational amplifier in the rail-to-rail input operational amplifier, the first stage is a differential input pair, the width-to-length ratio is small, current multiple amplification is carried out from the first stage mirror image to the output stage, thereby achieving the purpose of increasing the equivalent input transconductance of the whole operational amplifier and simultaneously realizing the effect of small input capacitance; on the premise of rail-to-rail input, the high transconductance is realized, and meanwhile, the equivalent input capacitance of the operational amplifier is reduced, so that the load on a preceding stage circuit is small, and the interference on the preceding stage circuit is small; and moreover, the equivalent input capacitance is small, and the work of high-frequency small signals is facilitated.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (1)
1. The high transconductance low input capacitance rail-to-rail operational amplifier is characterized by comprising an NMOS (N-channel metal oxide semiconductor) tube mn1, an NMOS tube mn2, an NMOS tube mn3, an NMOS tube mn4, an NMOS tube mn5, a PMOS tube mp1, a PMOS tube mp2, a PMOS tube mp3, a PMOS tube mp4, a PMOS tube mp5, a PMOS tube mp6 and a PMOS tube mp 7;
the gates of the NMOS transistor mn2 and the NMOS transistor mn3 are respectively connected with an input voltage, the sources of the NMOS transistor mn2 and the NMOS transistor mn3 are both connected with the drain of the NMOS transistor mn1, and the source of the NMOS transistor mn1 is grounded;
the gates of the PMOS transistor mp1 and the PMOS transistor mp2 are respectively connected with input voltage, and the drain of the PMOS transistor mp1 is respectively connected with the gate of the NMOS transistor mn4 and the gate of the NMOS transistor mn 5;
the drain electrode of the NMOS tube mn4 is in short circuit with the grid electrode, and the source electrode is grounded;
the drain electrode of the PMOS tube mp5 is in short circuit with the grid electrode, and the source electrode is connected with a power supply; the drain electrode of the PMOS tube mp5 is connected with the drain electrode of the NMOS tube mn2, and the gate electrode of the PMOS tube mp5 is connected with the gate electrode of the PMOS tube mp 4;
the drain electrode of the PMOS tube mp6 is in short circuit with the grid electrode, and the source electrode is connected with a power supply; the drain electrode of the PMOS tube mp6 is connected with the drain electrode of the NMOS tube mn 3;
the grid electrode of the PMOS tube mp6 is connected with the grid electrode of the PMOS tube mp7, and the source electrode of the PMOS tube mp7 is connected with a power supply;
the grid electrode of the NMOS tube mn4 is connected with the grid electrode of the NMOS tube mn5, the drain electrode of the NMOS tube mn4 is connected with the drain electrode of the PMOS tube mp7, and the source electrode of the NMOS tube mn4 and the source electrode of the NMOS tube mn5 are both grounded;
the drain electrode of the PMOS tube mp4 is connected with the drain electrode of the NMOS tube mn5, the drain electrode of the PMOS tube mp4 and the drain electrode of the NMOS tube mn5 are both connected with the drain electrode of the PMOS tube mp2, and the source electrode of the PMOS tube mp4 is connected with a power supply;
the NMOS transistor mn2 and the NMOS transistor mn3 form an NMOS differential pair;
the PMOS transistor mp1 and the PMOS transistor mp2 form a PMOS differential pair;
the PMOS transistor mp3 forms a tail current bias;
the NMOS tube mn4 and the NMOS tube mn5 form a current mirror, and the current mirror is loaded by the NMOS tube mn4 and the NMOS tube mn 5;
when the current is mirrored to a PMOS tube mp4 from the PMOS tube mp5 and mirrored to an NMOS tube mn5 from the NMOS tube mn4, the current is amplified by multiple times;
when a low level is input to enable the NMOS differential pair to enter a cut-off region, the PMOS transistor mp1, the PMOS transistor mp2, the PMOS transistor mp3, the NMOS transistor mn4 and the NMOS transistor mn5 form a current mirror load differential pair single-stage amplifier, and the single-stage amplifier still works when the low level is input.
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| CN201911016065.4A CN110690865B (en) | 2019-10-24 | 2019-10-24 | High transconductance low input capacitance rail-to-rail operational amplifier |
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| CN110690865B true CN110690865B (en) | 2020-11-13 |
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| CN111900975A (en) * | 2020-08-06 | 2020-11-06 | 中科亿海微电子科技（苏州）有限公司 | Level conversion circuit for converting high-voltage domain signal into low-voltage domain signal |
| CN114094948B (en) * | 2021-10-19 | 2024-05-24 | 道崇电子科技(浙江)股份有限公司 | Rail-to-Rail Amplifier Common Mode Sensing Control Constant Transconductance Input Method |
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