CN103248324B - A kind of high linearity low noise amplifier - Google Patents
A kind of high linearity low noise amplifier Download PDFInfo
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Abstract
The present invention proposes a kind of high linearity low noise amplifier. Described amplifier detects two common mode electrical levels by common mode feedback circuit from two difference output ends of fully-differential amplifier, and the deviation electric current of resonance-amplifier output feedback voltage is to the grid of tail current source, increase the overdrive voltage of tail current source, and then raising input current, reach the object that improves the linearity, solved due to the unstable non-linear distortion causing of output common mode level. The present invention is with solving the carrier leak problem existing in current ultrahigh frequency RFID receiver zero intermediate frequency reciver, and in the time that reception exists large block signal, linearity is amplified faint useful signal without distortion; In addition, the inter-stage cross coupling capacitor of introducing, is used for increasing power gain, has advantages of low-noise factor, low-power consumption, high linearity.
Description
Technical field
The invention belongs to RF IC design field, be specifically related to a kind of high linearity low noise amplifier.
Background technology
In recent years, wireless communication technology obtains swift and violent development, is playing the part of in social life more and more importantRole. The development of radio communication is had higher requirement to transceiver front ends circuit.
Low-noise amplifier LNA(LowNoiseAmplifier) as the receiver front end first order, its propertyThe quality of energy has directly affected the performance of whole receiver system, and the total noise coefficient of system depends on that the first order is lowThe noiseproof feature of noise amplifier. Except the overall noise of system, no matter be transmitting or reception data,Antenna can continue the carrier signal that transmitting is very large, and carrier signal is leaked to enter by circulator or directional coupler and connectReceipts machine front end, more than energy can reach 0dBm, is far longer than the energy that receives signal. Again due to major partIn communication system, reception and transmitted signal are same carrier frequency, cannot be at receiver front end by the logical filter of radio frequency bandRipple device, by the carrier signal filtering of leaking, produces receiver front end and subtracts quick and block, and has had a strong impact on receptionThe dynamic range of link.
More than summary, how, in the situation that ensureing natural sensitivity, suppressing carrier leakage causes receiverImpact is the key that improves receiver performance. This has just proposed performance requirement to receiver RF front-end circuit,LNA no longer only pays close attention to noiseproof feature, needs to focus on the linearity more, receiving large obstruction letterNumber time can linear amplify faint useful signal.
At present, in communication system carrier leak problem at RF identification (RadioFrequencyIdentification) particularly outstanding in technology, and research discovery, be more suitable for future, particularly commercial offersWhat in chain, apply is ultra-high frequency band system, and therefore, stimulation frequency of the present invention is set as ultra-high frequency band.
Figure 1 shows that a kind of typical differential low noise amplifier. NM1, NM3 and NM2, NM4 form altogetherSource common gate structure provides the gain of low-noise amplifier, has reduced the capacitance of drain of NM1, NM2 simultaneously and has producedRaw Miller effect, and improved the isolation between input and output.
L1, L2, L3, L4 are used for realizing coupling to make input impedance are 50 ohm, wherein L1, L2 conductSource degeneration resistance, adjusting L3, L4 are used for controlling the frequency of whole LNA work, and at NM1, NM2The upper C1 of shunt capacitance respectively, C2 can improve the grid source capacitor C gs of two metal-oxide-semiconductors, have increased control inductanceNargin.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, in order to meet the requirement of radio circuit front end to the linearity, proposeA kind of high linearity low noise amplifier. Described amplifier has comprised fully-differential amplifier and common mode feedback circuit(Common-Feedback, CMFB) two modules, detect by the difference output end of fully-differential amplifierGo out common mode electrical level, and by common mode feedback circuit CMFB negative-feedback the grid to tail current source, raising work electricityStream, to increase the linearity; This amplifier circuit has positive and negative two-way input, output, and this two-way circuit is completely rightClaim design.
The present invention, for solving the problems of the technologies described above, adopts following technical scheme:
A kind of high linearity low noise amplifier, comprises fully-differential amplifier and common mode feedback circuit; Described entirely poorThe difference output end output common mode level of point amplifier, and by described common mode feedback circuit negative-feedback to tail current sourceGrid; Described common mode feedback circuit, the differential output signal of its anodal and described fully-differential amplifier just defeatedGo out end and connect, negative pole is connected with the negative output terminal of the differential output signal of described fully-differential amplifier.
Described fully-differential amplifier is made up of jointly typical fully differential circuit and cross coupling capacitor; Described typical caseFully differential circuit comprise NMOS pipe to the five NMOS pipes, the 7th PMOS pipe, the 8th PMOSPipe, the first to the 4th inductance, the first electric capacity, the second electric capacity, the 3rd resistance, the 4th resistance; Described intersection couplingClose electric capacity and comprised the 3rd electric capacity, the 4th electric capacity, the first resistance, the second resistance;
The method of attachment of described typical fully differential circuit is as follows: the drain electrode of NMOS pipe and the 3rd NMOSPipe source electrode is connected; The 2nd NMOS pipe drain electrode is connected with the 4th NMOS pipe source electrode; The 3rd NMOS pipe leaksThe utmost point is connected with the 7th PMOS pipe drain electrode; The 4th NMOS pipe drain electrode is connected with the 8th PMOS pipe drain electrode; TheThree NMOS tube grids, the 4th NMOS tube grid, the 7th PMOS pipe source electrode, the 8th PMOS pipe sourceThe utmost point is connected with power supply; The 7th gate pmos utmost point, the 8th gate pmos utmost point connect the 3rd bias voltage; FirstBetween NMOS pipe source electrode and grid, be connected the first electric capacity, a NMOS pipe source electrode is connected with first inductance one end;Between the 2nd NMOS pipe source electrode and grid, be connected the second electric capacity; The 2nd NMOS pipe source electrode and second inductance one endBe connected; The first inductance other end, the second inductance other end with as the 5th of fully differential circuit tail current sourceThe drain electrode of NMOS pipe is connected; The 5th NMOS pipe source ground, grid connects the second bias voltage; FirstNMOS tube grid is connected with the 3rd inductance one end, another termination input signal of the 3rd inductance and with the 3rd resistanceOne end is connected, another termination first bias voltage of the 3rd resistance; The 2nd NMOS tube grid and the 4th inductance oneEnd is connected, and another termination input signal of the 4th inductance is also connected with the 4th resistance one end, the 4th another termination of resistanceThe first bias voltage;
The method of attachment of described typical fully differential circuit and cross coupling capacitor is as follows: one end of the 3rd electric capacity withThe source electrode of the drain electrode of the 2nd NMOS pipe and the 4th NMOS pipe is connected, the other end and the 3rd NMOS pipeGrid is connected; One end of the first resistance is connected with the grid of the 3rd NMOS pipe, and the other end is connected with power supply;One end of the 4th electric capacity is connected with the drain electrode of a NMOS pipe and the source electrode of the 3rd NMOS pipe, the other end withThe grid of the 4th NMOS pipe is connected; One end of the second resistance is connected with the grid of the 4th NMOS pipe, anotherEnd is connected with power supply.
Described the 3rd electric capacity, the 4th electric capacity are the electric capacity that standard CMOS process is supported.
Described common mode feedback circuit comprises PMOS pipe to the six PMOS pipes and a 6th NMOS pipe; ItsIn, the 5th PMOS pipe source electrode, the 6th PMOS pipe source electrode are connected with power supply; The 5th gate pmos utmost point,The 6th gate pmos utmost point is connected with the 6th resistance one end, and the 6th resistance other end is connected with bias voltage; TheThe two gate pmos utmost points, the 3rd gate pmos utmost point are connected with the 7th resistance one end, the 7th resistance other end withReference voltage is connected; The one PMOS pipe source electrode and the 2nd PMOS pipe source electrode, the 5th PMOS pipe drain electrode phaseConnect; The 3rd PMOS pipe source electrode is connected with the 4th PMOS pipe source electrode, the 6th PMOS pipe drain electrode; The one PMOSPipe drain electrode is connected with the 4th PMOS pipe drain electrode; The first gate pmos utmost point and the 4th gate pmos utmost point are respectivelyAs the positive and negative input of common mode feedback circuit; Common-mode voltage is compared with reference voltage, the voltage mistake of gainedThe poor namely feedback voltage of common mode feedback circuit, this feedback voltage is exported by the grid of the 6th NMOS pipe,The grid of the 6th NMOS pipe is connected with drain electrode.
The negative-feedback of described common mode feedback circuit output voltage is to the grid of tail current source the 5th NMOS pipe, andBetween the 5th NMOS tube grid and the second bias voltage, connect the 5th resistance.
The invention has the beneficial effects as follows: the present invention proposes a kind of high linearity low noise amplifier. Described amplificationDevice detects common mode electrical level by common mode feedback circuit CMFB from two difference output ends of fully-differential amplifier,And export the grid of feedback voltage to tail current source, thereby the overdrive voltage of tail current source, Jin Erti are increasedHigh operating current reaches the object that improves the linearity, solved again simultaneously due to output common mode level unstable andThe non-linear distortion causing; In addition, cross coupling capacitor, be used for increasing gain, and noise decrease coefficient is to carryNoise performance, this structure has advantages of low-noise factor, low-power consumption, high linearity. The present invention is used for separatingThe carrier leak problem existing in current zero intermediate frequency reciver of determining, improves the linearity of low-noise amplifier, makes itCan be in there is large block signal, the faint useful signal of linear amplification without distortion.
Brief description of the drawings
Fig. 1 is a kind of typical differential low noise amplifier structure;
Fig. 2 is a kind of high linearity low noise amplifier architecture provided by the invention;
Fig. 3 is a kind of common mode feedback circuit structure that the present invention adopts;
Fig. 4 is the noise coefficient schematic diagram of typical differential low noise amplifier;
Fig. 5 is the noise coefficient schematic diagram of high linearity low noise amplifier of the present invention;
Fig. 6 is input third order intermodulation point (IIP3) schematic diagram of typical differential low noise amplifier;
Fig. 7 is input third order intermodulation point (IIP3) schematic diagram of high linearity low noise amplifier of the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing, further illustrate a kind of high linearity low noise amplifier of the present invention.
With reference to Fig. 2, a kind of high linearity low noise amplifier provided by the present invention is by difference amplifier and negative anti-Current feed circuit constitutes, and difference amplifier adopts typical fully differential circuit and cross coupling capacitor structure.This amplifier circuit has positive and negative two-way input, output, this two-way circuit full symmetric design. RFopFor differenceThe positive output end of amplifier; RFonFor the negative output terminal of difference amplifier.
Described typical fully differential circuit comprises NMOS pipe to the five NMOS pipes, the 7th PMOS pipePM7, the 8th PMOS pipe PM8, the first to the 4th inductance, the first capacitor C 1, the second capacitor C 2, theThree resistance R 3, the 4th resistance R 4; Described cross coupling capacitor comprised the 3rd capacitor C 3, the 4th capacitor C 4,The first resistance R 1, the second resistance R 2;
The method of attachment of described typical fully differential circuit is as follows: a NMOS pipe NM1 drain electrode is with the 3rdNMOS pipe NM3 source electrode is connected; The 2nd NMOS pipe NM2 drain electrode and the 4th NMOS pipe NM4 source electrodeBe connected; The 3rd NMOS pipe NM3 drain electrode is connected with the 7th PMOS pipe PM7 drain electrode; The 4th NMOSPipe NM4 drain electrode is connected with the 8th PMOS pipe PM8 drain electrode; The 3rd NMOS pipe NM3 grid, the 4thNMOS pipe NM4 grid, the 7th PMOS pipe PM7 source electrode, the 8th PMOS pipe PM8 source electrode and power supplyVdd is connected; The 7th PMOS pipe PM7 grid, the 8th PMOS pipe PM8 grid connect the 3rd bias voltageVbias3; Between the one NMOS pipe NM1 source electrode and grid, be connected the first capacitor C 1, the one NMOS pipe NM1Source electrode is connected with first inductance L 1 one end; Between the 2nd NMOS pipe NM2 source electrode and grid, be connected the second electric capacityC2; The 2nd NMOS pipe NM2 source electrode is connected with second inductance L 2 one end; First inductance L 1 other end,Second inductance L 2 other ends and the drain electrode phase of managing NM5 as the 5th NMOS of fully differential circuit tail current sourceConnect; The 5th NMOS pipe NM5 source ground, grid meets the second bias voltage Vbias2; The one NMOSPipe NM1 grid is connected with the 3rd inductance L 3 one end, the 3rd inductance L 3 another termination input signals with the 3rdResistance R 3 one end are connected, the 3rd resistance R 3 another termination the first bias voltage Vbias1; The 2nd NMOS pipeNM2 grid is connected with the 4th inductance L 4 one end, the 4th inductance L 4 another termination input signals and with the 4th electricityResistance R4 one end is connected, the 4th resistance R 4 another termination the first bias voltage Vbias1;
The method of attachment of described typical fully differential circuit and cross coupling capacitor is as follows: one of the 3rd capacitor C 3End is connected with the drain electrode of the 2nd NMOS pipe NM2 and the source electrode of the 4th NMOS pipe NM4, the other end and theThe grid of three NMOS pipe NM3 is connected; The grid of one end of the first resistance R 1 and the 3rd NMOS pipe NM3Extremely connected, the other end is connected with power supply Vdd; One end of the 4th capacitor C 4 and NMOS pipe NM1'sThe source electrode of drain electrode and the 3rd NMOS pipe NM3 is connected, and the other end and the 4th NMOS manage the grid phase of NM4Connect; One end of the second resistance R 2 is connected with the grid of the 4th NMOS pipe NM4, the other end and power supply VddBe connected.
With reference to Fig. 3, described common mode feedback circuit comprises PMOS pipe to the six PMOS pipes and the 6thNMOS pipe, by four PMOS pipe common-mode voltages that detect difference amplifier output parallel with one another;Wherein, the 5th PMOS pipe PM5 source electrode, the 6th PMOS pipe PM6 source electrode are connected with power supply Vdd; TheFive PMOS pipe PM5 grids, the 6th PMOS pipe PM6 grid are connected with the 6th resistance R 6 one end, and the 6thResistance R 6 other ends are connected with bias voltage Vbias; The 2nd PMOS pipe PM2 grid, the 3rd PMOSPipe PM3 grid is connected with the 7th resistance R 7 one end, and the 7th resistance R 7 other ends are connected with reference voltage Vref;The one PMOS pipe PM1 source electrode and the 2nd PMOS pipe PM2 source electrode, the 5th PMOS pipe PM5 drain electrode phaseConnect; The 3rd PMOS pipe PM3 source electrode and the 4th PMOS pipe PM4 source electrode, the 6th PMOS pipe PM6 leakExtremely connected; The one PMOS pipe PM1 drain electrode is connected with the 4th PMOS pipe PM4 drain electrode; The one PMOSPipe PM1 grid and the 4th PMOS manage PM4 grid respectively as the positive and negative input of common mode feedback circuit;Common-mode voltage is compared with reference voltage Vref, and the voltage error of gained is the feedback of common mode feedback circuit namelyVoltage, this feedback voltage is by the grid output of the 6th NMOS pipe NM6, and the 6th NMOS manages NM6'sGrid is connected with drain electrode.
Common mode feedback circuit, its positive pole is connected on the positive output end RF of signalop, namely the 3rd NMOS pipe NM3And between the 7th PMOS pipe PM7, its negative pole is connected on the negative output terminal RF of signalon, namely the 4th NMOSBetween pipe NM4 and the 8th PMOS pipe PM8; Its output is connected on the grid of the tail current source of difference channel,The namely grid of the 5th NMOS pipe NM5;
With reference to Fig. 3, output common mode electrical level detected by common mode feedback circuit CMFB, and and inside circuitReference voltage Vref relatively draws output feedback voltage V cmfb, is added in the grid of tail current source NM5, like thisThe gate source voltage V of NM5GSImprove, by formula:
I in formulaSSFor the current value that tail current source provides, VTHFor the threshold voltage of tail current source NMOS, μnCoxFor process constant, the breadth length ratio that W/L is metal-oxide-semiconductor.
Known: as gate source voltage VGSImprove ISSAlso along with raising, increased operating current, thereby improvedThe input linearity, the index of the linearity is input third order intermodulation point (IIP3), and IIP3 is by inputting the linearity and defeatedGo out the linearity and jointly determine, for the input linearity, common mode feedback circuit of the present invention can improve, and forOutput, often by ensureing that output signal does not enter limiting voltage district and realizes.
But that larger input current often makes to export dc point is on the low side, thereby form output voltage restriction, so IThe normal PMOS pipe that adopts as load, the present invention adopts the 7th PMOS pipe PM7 to manage with the 8th PMOSPM8 is as load, and pipe sizing is large scale. Use PMOS pipe to exist difference channel as loadDistinctive problem: output common mode level is unstable. The present invention has introduced common mode feedback circuit, has increased on the one handInput current improves the input linearity, and in high-gain amplifier, output common mode level is to device on the other handCharacteristic and mismatch quite responsive, this common mode feedback circuit can detect the common mode electrical level of two outputs, andThe deviation electric current of with good grounds ground resonance-amplifier.
In cross coupling capacitor structure, the 3rd capacitor C 3 and the 4th capacitor C 4 are by amplifier tube the one NMOS pipeSignal after NM1 and the 2nd NMOS pipe NM2 amplifies is coupled to respectively the 3rd NMOS pipe NM3 and theThe grid of four NMOS pipe NM4 amplifies again, has increased the gain of amplifier. Meanwhile, this coupling capacitance subtractsLittle amplifier tube the one NMOS pipe NM1 and the 2nd NMOS manage the gate leakage capacitance C of NM2GDTo noise-inducedThe impact of energy.
Figure 4 shows that noise coefficient NF (NoiseFigure) schematic diagram of typical differential low noise amplifier.Can find out, when frequency is 900MHZ, the noise coefficient of low-noise amplifier is 2.86dB; Fig. 5 instituteBe shown the noise coefficient NF schematic diagram of high linearity low noise amplifier of the present invention. Can find out, in frequencyFor 900MHZ time, the noise coefficient of low-noise amplifier is 2.62dB. It is known with Fig. 5 by comparison diagram 4,High linearity low noise noise figure of amplifier of the present invention is than the noise system of typical differential low noise amplifierNumber is low 0.3dB nearly when frequency is 900MHz, has illustrated that noiseproof feature of the present invention is better.
Figure 6 shows that the input third order intermodulation point IIP3 (Input3rd of typical differential low noise amplifierOrderinterceptpoint) schematic diagram. Can find out, when frequency is 900MHz, low noiseThe input third order intermodulation point IIP3 of amplifier is-9.0dBm; Figure 7 shows that high linearity low noise of the present invention putsThe input third order intermodulation point IIP3 schematic diagram of large device. Can find out, when frequency is 900MHZ, low noiseThe input third order intermodulation point IIP3 of acoustic amplifier is-5.4dBm. Known with Fig. 7 by comparison diagram 6, the present inventionThe input third order intermodulation point IIP3 of high linearity low noise amplifier in the time that working frequency points is 900MHz, compare allusion quotationThe high 3.6dB of the differential low noise amplifier left and right of type. Illustrate that the linearity of the present invention is relatively good.
In sum, the high linearity low noise amplifier that the present invention proposes has that the linearity is high, noise coefficient is littleAdvantage, in ultrahigh frequency RFID receiver front end circuit, have broad application prospects.
For those skilled in the art, according to above implementation of class can be easy to association otherAdvantage and distortion. Therefore, the present invention is not limited to above-mentioned instantiation, its as just example to the present inventionA kind of form carry out detailed, exemplary explanation. Not deviating from the scope of aim of the present invention, this area is generalLogical technical staff is equal to by various the technical scheme that replacement obtains according to above-mentioned instantiation, all should be included inWithin claim scope of the present invention and equivalency range thereof.
Claims (3)
1. a high linearity low noise amplifier, is characterized in that, comprises fully-differential amplifier and common mode feedback circuit;The difference output end output common mode level of described fully-differential amplifier, and given by described common mode feedback circuit negative-feedbackThe grid of fully-differential amplifier tail current source; Described common mode feedback circuit, its anodal and described fully-differential amplifierDifferential output signal positive output end connect, the differential output signal of negative pole and described fully-differential amplifier bearOutput connects;
Described fully-differential amplifier is made up of jointly typical fully differential circuit and cross coupling capacitor; Described typical caseFully differential circuit comprise the first to the 5th NMOS pipe, the 7th PMOS pipe, the 8th PMOS pipe, firstTo the 4th inductance, the first electric capacity, the second electric capacity, the 3rd resistance, the 4th resistance; Described cross coupling capacitor bagThe 3rd electric capacity, the 4th electric capacity, the first resistance, the second resistance are drawn together;
The connection of described typical fully differential circuit is as follows: NMOS pipe (NM1) drain electrode and the 3rd NMOSPipe (NM3) source electrode is connected; The 2nd NMOS pipe (NM2) drain electrode and the 4th NMOS pipe (NM4)Source electrode is connected; The 3rd NMOS pipe (NM3) drain electrode is connected with the 7th PMOS pipe (PM7) drain electrode; TheFour NMOS pipe (NM4) drain electrodes are connected with the 8th PMOS pipe (PM8) drain electrode; The 3rd NMOS pipe (NM3)Grid, the 4th NMOS pipe (NM4) grid, the 7th PMOS pipe (PM7) source electrode, the 8th PMOSPipe (PM8) source electrode is connected with power supply (Vdd) respectively; The 7th PMOS pipe (PM7) grid, the 8thPMOS pipe (PM8) grid connects respectively the 3rd bias voltage (Vbias3); The one NMOS pipe (NM1)Between source electrode and grid, be connected the first electric capacity (C1), NMOS pipe (NM1) source electrode and first inductance (L1)One end is connected; Between the 2nd NMOS pipe (NM2) source electrode and grid, be connected the second electric capacity (C2); The 2nd NMOSPipe (NM2) source electrode is connected with the second inductance (L2) one end; The first inductance (L1) other end, the second electricitySense (L2) other end respectively with the leakage of the 5th NMOS pipe (NM5) as fully differential circuit tail current sourceExtremely connected; The 5th NMOS pipe (NM5) source ground, the 5th NMOS pipe (NM5) grid connects secondBias voltage (Vbias2); The one NMOS pipe (NM1) grid is connected with the 3rd inductance (L3) one end,The 3rd another termination input signal of inductance (L3) is also connected with the 3rd resistance (R3) one end, the 3rd resistance (R3)Another termination first bias voltage (Vbias1); The 2nd NMOS pipe (NM2) grid and the 4th inductance (L4)One end is connected, and the 4th another termination input signal of inductance (L4) is also connected with the 4th resistance (R4) one end,Another termination first bias voltage (Vbias1) of the 4th resistance (R4);
The method of attachment of described typical fully differential circuit and cross coupling capacitor is as follows: the 3rd electric capacity (C3) oneEnd is connected with the 2nd NMOS pipe (NM2) drain electrode and the 4th NMOS pipe (NM4) source electrode respectively, and the 3rdElectric capacity (C3) other end is connected with the grid that the 3rd NMOS manages (NM3); One of the first resistance (R1)End is connected with the grid of the 3rd NMOS pipe (NM3), the first resistance (R1) other end and power supply (Vdd)Be connected; Drain electrode and the 3rd NMOS of (NM1) managed respectively in one end of the 4th electric capacity (C4) with a NMOSThe source electrode of pipe (NM3) is connected, the grid of the 4th electric capacity (C4) other end and the 4th NMOS pipe (NM4)Extremely connected; One end of the second resistance (R2) is connected with the grid that the 4th NMOS manages (NM4), the second electricityResistance (R2) other end is connected with power supply (Vdd);
Described common mode feedback circuit comprises the first to the 6th PMOS pipe and the 6th NMOS pipe; Wherein, the 5thPMOS pipe (PM5) source electrode, the 6th PMOS pipe (PM6) source electrode are connected with power supply (Vdd) respectively;The 5th PMOS pipe (PM5) grid, the 6th PMOS pipe (PM6) grid respectively with the 6th resistance (R6)One end is connected, and the 6th resistance (R6) other end is connected with bias voltage (Vbias); The 2nd PMOS pipe (PM2)Grid, the 3rd PMOS pipe (PM3) grid are connected with the 7th resistance (R7) one end respectively, the 7th resistance(R7) other end is connected with reference voltage (Vref); The one PMOS pipe (PM1) source electrode is respectively with secondPMOS pipe (PM2) source electrode, the 5th PMOS pipe (PM5) drain electrode are connected; The 3rd PMOS pipe (PM3)Source electrode is connected with the 4th PMOS pipe (PM4) source electrode, the 6th PMOS pipe (PM6) drain electrode respectively; TheTwo PMOS pipe (PM2) drain electrodes and the 3rd PMOS pipe (PM3) drain electrode, the 6th NMOS pipe (NM6)Drain electrode is connected; The one PMOS pipe (PM1) drain electrode and the 4th PMOS pipe (PM4) drain electrode and the 6thThe source electrode of NMOS pipe (NM6) is connected to the ground simultaneously; The one PMOS pipe (PM1) grid and the 4th PMOSPipe (PM4) grid is respectively as the positive and negative input of common mode feedback circuit; Common-mode voltage and reference voltage(Vref) compare, the voltage error of gained is the feedback voltage of common mode feedback circuit namely, this feedback voltageBy the 6th NMOS pipe (NM6) grid output, the grid of the 6th NMOS pipe (NM6) and drain electrode phaseConnect.
2. a kind of high linearity low noise amplifier as claimed in claim 1, is characterized in that, described the 3rd electric capacity(C3), the 4th electric capacity (C4) is the electric capacity that standard CMOS process is supported.
3. a kind of high linearity low noise amplifier as claimed in claim 1 or 2, is characterized in that described common modeThe negative-feedback of feedback circuit output voltage is to the grid of fully-differential amplifier tail current source the 5th NMOS pipe (NM5)The utmost point, and connect the 5th electricity between the 5th NMOS pipe (NM5) grid and the second bias voltage (Vbias2)Resistance (R5).
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