CN202565236U - Broadband voltage-controlled oscillator circuit with low phase noise and low power consumption - Google Patents

Abstract

The utility model relates to a broadband voltage-controlled oscillator circuit with low phase noise and low power consumption. The existing broadband voltage-controlled oscillator has poor noise performance, high power consumption, and the application in a radio frequency communication system is limited. The broadband voltage-controlled oscillator circuit with low phase noise and low power consumption comprises a negative resistance oscillation structure and two buffer structures. The negative resistance oscillation structure comprises a negative resistance structure and a resonant network, wherein the negative resistance structure comprises two PMOS tubes and two NMOS tubes, and the resonant network comprises a resonant inductor, a switch capacitor array, two variable capacitors and two fixed capacitors. The switch capacitor array comprises fifteen switch capacitor units for forming four selection control ends and sixteen band choices. Each switch capacitor unit comprises two MOM capacitors, two inverters and an NMOS tube, wherein the MOM capacitors are three-dimensional interdigital capacitors. With the broadband voltage-controlled oscillator circuit with low phase noise and low power consumption, a comparatively wide range of frequency adjustment can be realized and properties of low phase noise and low power consumption can be realized through corresponding phase noise optimization.

Description

The low low-power consumption wideband voltage controlled oscillator circuit of making an uproar mutually

Technical field

The utility model belongs to microelectronics technology, a kind of low low-power consumption wideband voltage controlled oscillator circuit of making an uproar mutually.

Background technology

Radio communication develop rapidly in recent years, working frequency range relate to 100,000,000 to 10,000,000,000, so just need the wide band transceiver of design low-power consumption to satisfy the requirement of various wireless communication agreement.As composition module the most basic in the transceiver, voltage controlled oscillator provides local frequency for transmitting and receiving, and is the highest module of operating frequency in the system.Voltage controlled oscillator should have the frequency coverage of broad, to satisfy needs of different applications under the prerequisite that guarantees power consumption and phase noise.

The oscillator common structural has LC oscillator and ring oscillator.Ring oscillator can adopt pure digi-tal CMOS technology to realize, does not need inductance element, can realize the tuning range of broad.But its noiseproof feature is relatively poor, has limited its application in RF communication system.Owing to have pass band filter characteristic, be fit to have the radio system of low noise requirement based on the LC oscillator of negative resistance principle.Utilize variable capacitance and inductance to constitute resonant tank and can obtain voltage controlled oscillator.Because the capacitance variation of variable capacitance is limited in scope, tuning range is narrower, the structure that adopts variable capacitance to combine with switched capacitor array usually.But the too much switching capacity of parallel connection can significantly reduce the quality factor in loop on resonant tank, the output phase noise penalty that causes vibrating, and power consumption increases, the starting of oscillation time lengthening.Therefore, broadband how to reduce phase noise under requiring and power consumption becomes pierce circuit key for design problem.

Summary of the invention

The purpose of the utility model provides a kind of low phase noise, low-power consumption, the wide-band oscillator circuit compatible fully with the CMOS integrated circuit technology.

The utility model comprises a negative resistance oscillation structure and two buffer structures, and the negative resistance oscillation structure comprises negative resistance structure resonant network;

The 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 2nd NMOS pipe MN2 and the 3rd NMOS pipe MN3 constitute the negative resistance structure; Wherein the drain electrode of the grid of the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3 is connected with the grid of the 2nd NMOS pipe MN2, the drain electrode of the 3rd NMOS pipe MN3; As in-phase output end CKP; The drain electrode of the grid of the 3rd PMOS pipe MP3, the 2nd PMOS pipe MP2 is connected with the drain electrode of the grid of the 3rd NMOS pipe MN3, the 2nd NMOS pipe MN2, as reversed-phase output CKN;

Resonant inductance L3, switched capacitor array SCA, the first variable capacitance Cvar1, the second variable capacitance Cvar2, the first fixed capacity C3, the second fixed capacity C4 constitute resonant network; The termination reversed-phase output CKN of the end of the end of the positive pole of the first variable capacitance Cvar1, the first fixed capacity C3, resonant inductance L3, switched capacitor array SCA wherein; Another termination in-phase output end CKP of the end of the positive pole of the second variable capacitance Cvar2, the second fixed capacity C4, the other end of resonant inductance L3, switched capacitor array SCA; The other end of the first fixed capacity C3 is connected with the other end of the second fixed capacity C4; The negative pole of the first variable capacitance Cvar1 is connected with the negative pole of the second variable capacitance Cvar2, as the control voltage input terminal Vctrl of pierce circuit;

The first filter capacitor C1 and the first filter inductance L1 parallel connection be as Power Noise Filter, the termination power VDD after the parallel connection, and the other end after the parallel connection is connected with the source electrode of the 2nd PMOS pipe MP2, the source electrode of the 3rd PMOS pipe MP3; The second filter capacitor C2 and the second filter inductance L2 parallel connection be as the substrate noise filter, the end ground connection after the parallel connection, and the other end after the parallel connection is connected with the source electrode of the 2nd NMOS pipe MN2, the source electrode of the 3rd NPMOS pipe MN3;

The one PMOS pipe MP1 and NMOS pipe MN1 constitute a buffer structure; The grid of the grid of the one PMOS pipe MP1 and NMOS pipe MN1 meets reversed-phase output CKN; The drain electrode of the one PMOS pipe MP1 is connected with the drain electrode of NMOS pipe MN1, as the inversion clock output CLKN of pierce circuit; The 4th PMOS pipe MP4 and the 4th NMOS pipe MN4 constitute another buffer structure; The grid of the grid of the 4th PMOS pipe MP4 and the 4th NMOS pipe MN4 meets in-phase output end CKP; The drain electrode of the 4th PMOS pipe MP4 is connected with the drain electrode of the 4th NMOS pipe MN4, as the in-phase clock output CLKP of pierce circuit; The source electrode of the source electrode of the one PMOS pipe MP1 and the 4th PMOS pipe MP4 meets power vd D, the source ground of the source electrode of NMOS pipe MN1 and the 4th NMOS pipe MN4;

Described switched capacitor array SCA comprises 15 switching capacity unit; The structure of each switching capacity unit is identical; Comprise two MOM electric capacity, two inverters and a NMOS pipe; The drain electrode of the output termination NMOS pipe MNs of the end of the one MOM capacitor C s1, the first inverter Inv1; The source electrode of the output termination NMOS pipe MNs of the end of the 2nd MOM capacitor C s2, the second inverter Inv2, the grid of NMOS pipe MNs is connected with the input of the first inverter Inv1 and the input of the second inverter Inv2, as the gating input of this switching capacity unit; The other end of the one MOM capacitor C s 1 of all switching capacity unit connects, and as the end of switched capacitor array SCA, the other end of the 2nd MOM capacitor C s2 of all switching capacity unit connects, as the other end of switched capacitor array SCA;

The gating input of a switching capacity unit in 15 switching capacity unit independently is provided with, as the one-level frequency band control selecting side D1 of pierce circuit; The gating input of two switching capacity unit connects, as the secondary frequency band control selecting side D2 of pierce circuit; The gating input of four switching capacity unit connects, as three grades of frequency band control selecting side D3 of pierce circuit; The gating input of eight switching capacity unit connects, as the level Four frequency band control selecting side D4 of pierce circuit.

MOM electric capacity in the switching capacity unit adopts three-dimensional interdigital capacitor; Comprise the horizontally disposed plane of multilayer interdigital capacitor; Described plane interdigital capacitor is to be arranged on the metal film that pair of planar on the silicon substrate is the broach shape, and each metal film comprises parallel broach bar C-2 and intercell connector C-1, and intercell connector C-1 is with a plurality of broach bar C-2 and connect; Two metal films are the interdigitated setting; Two metal film location swaps of the plane interdigital capacitor of adjacent two layers, and through being arranged on the plated-through hole C-3 connection at intercell connector place, in the vertical direction forms the facade interdigital capacitor.

The pierce circuit of the utility model has been realized the frequency-tuning range of broad, through the respective phase noise optimization, has realized the performance of low phase noise and low-power consumption.The voltage controlled oscillator reference frequency output of realizing through the flow of SMIC 65nm CMOS technology is 0.75～1.5GHz, and frequency-tuning range reaches 83%, and phase noise at 1.21GHz frequency place is-125.84dBc/Hz, and FOM can reach-184, and power consumption is merely 2.25mW.

Description of drawings

Fig. 1 is the integrated circuit figure of the utility model;

Fig. 2 is the circuit diagram of switched capacitor array among Fig. 1;

Fig. 3-1 is the planar structure sketch map of MOM electric capacity among Fig. 2;

Fig. 3-2 is the facade structures sketch map of MOM electric capacity among Fig. 2;

Fig. 4 is the relation curve of phase noise and NMOS pipe trench road breadth length ratio;

Fig. 5 is the relation curve of phase noise and resonant cavity inductance sense value.

Embodiment

Below in conjunction with accompanying drawing the circuit structure and the phase noise optimization method of the utility model are done further explain.For the effect of the utility model is described, adopt 65nm CMOS technology to design the flow checking.

As shown in Figure 1, a kind of low low-power consumption wideband voltage controlled oscillator circuit of making an uproar mutually comprises a negative resistance oscillation structure and two buffer structures, and the negative resistance oscillation structure comprises negative resistance structure resonant network;

The 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 2nd NMOS pipe MN2 and the 3rd NMOS pipe MN3 constitute the negative resistance structure; Wherein the drain electrode of the grid of the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3 is connected with the grid of the 2nd NMOS pipe MN2, the drain electrode of the 3rd NMOS pipe MN3; As in-phase output end CKP; The drain electrode of the grid of the 3rd PMOS pipe MP3, the 2nd PMOS pipe MP2 is connected with the drain electrode of the grid of the 3rd NMOS pipe MN3, the 2nd NMOS pipe MN2, as reversed-phase output CKN;

Resonant inductance L3, switched capacitor array SCA, the first variable capacitance Cvar1, the second variable capacitance Cvar2, the first fixed capacity C3, the second fixed capacity C4 constitute resonant network; The termination reversed-phase output CKN of the end of the end of the positive pole of the first variable capacitance Cvar1, the first fixed capacity C3, resonant inductance L3, switched capacitor array SCA wherein; Another termination in-phase output end CKP of the end of the positive pole of the second variable capacitance Cvar2, the second fixed capacity C4, the other end of resonant inductance L3, switched capacitor array SCA; The other end of the first fixed capacity C3 is connected with the other end of the second fixed capacity C4; The negative pole of the first variable capacitance Cvar1 is connected with the negative pole of the second variable capacitance Cvar2, as the control voltage input terminal Vctrl of pierce circuit;

The first filter capacitor C1 and the first filter inductance L1 parallel connection be as Power Noise Filter, the termination power VDD after the parallel connection, and the other end after the parallel connection is connected with the source electrode of the 2nd PMOS pipe MP2, the source electrode of the 3rd PMOS pipe MP3; The second filter capacitor C2 and the second filter inductance L2 parallel connection be as the substrate noise filter, the end ground connection after the parallel connection, and the other end after the parallel connection is connected with the source electrode of the 2nd NMOS pipe MN2, the source electrode of the 3rd NPMOS pipe MN3;

The one PMOS pipe MP1 and NMOS pipe MN1 constitute a buffer structure; The grid of the grid of the one PMOS pipe MP1 and NMOS pipe MN1 meets reversed-phase output CKN; The drain electrode of the one PMOS pipe MP1 is connected with the drain electrode of NMOS pipe MN1, as the inversion clock output CLKN of pierce circuit; The 4th PMOS pipe MP4 and the 4th NMOS pipe MN4 constitute another buffer structure; The grid of the grid of the 4th PMOS pipe MP4 and the 4th NMOS pipe MN4 meets in-phase output end CKP; The drain electrode of the 4th PMOS pipe MP4 is connected with the drain electrode of the 4th NMOS pipe MN4, as the in-phase clock output CLKP of pierce circuit; The source electrode of the source electrode of the one PMOS pipe MP1 and the 4th PMOS pipe MP4 meets power vd D, the source ground of the source electrode of NMOS pipe MN1 and the 4th NMOS pipe MN4.

As shown in Figure 2; Switched capacitor array SCA comprises 15 switching capacity unit; The structure of each switching capacity unit is identical; Comprise two MOM electric capacity, two inverters and a NMOS pipe, the drain electrode of the output termination NMOS pipe MNs of the end of a MOM capacitor C s 1, the first inverter Inv1, the source electrode of the output termination NMOS pipe MNs of the end of the 2nd MOM capacitor C s2, the second inverter Inv2; The grid of NMOS pipe MNs is connected with the input of the first inverter Inv1 and the input of the second inverter Inv2, as the gating input of this switching capacity unit; The other end of the one MOM capacitor C s1 of all switching capacity unit connects, and as the end of switched capacitor array SCA, the other end of the 2nd MOM capacitor C s2 of all switching capacity unit connects, as the other end of switched capacitor array SCA;

The gating input of a switching capacity unit in 15 switching capacity unit independently is provided with, as the one-level frequency band control selecting side D1 of pierce circuit; The gating input of two switching capacity unit connects, as the secondary frequency band control selecting side D2 of pierce circuit; The gating input of four switching capacity unit connects, as three grades of frequency band control selecting side D3 of pierce circuit; The gating input of eight switching capacity unit connects, as the level Four frequency band control selecting side D4 of pierce circuit.

With shown in the 3-2, the MOM electric capacity in the switching capacity unit adopts three-dimensional interdigital capacitor, comprises the horizontally disposed plane of multilayer interdigital capacitor like Fig. 3-1.The plane interdigital capacitor is to be arranged on the metal film that pair of planar on the silicon substrate is the broach shape; Each metal film comprises parallel broach bar C-2 and intercell connector C-1; Intercell connector C-1 is with a plurality of broach bar C-2 and connect, and two metal films are the interdigitated setting, two metal film location swaps of the plane interdigital capacitor of adjacent two layers; And through being arranged on the plated-through hole C-3 connection at intercell connector place, in the vertical direction forms the facade interdigital capacitor.

Oscillator is output as sine wave arbitrarily, can be expressed as V _Out=Acos (ω ₀T), wherein A is an amplitude, ω ₀Be angular frequency.According to the model of Harjimiri, near carrier wave 1/f ²The phase noise in zone can be expressed as:

$L\left(\mathrm{\&Delta;\&omega;}\right)=10\log (\frac{{\mathrm{\&Gamma;}}_{\mathrm{rms}}^2}{q_{\max }^2}\&CenterDot;\frac{\stackrel{\&OverBar;}{i_{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">n</figure-callout>}}^2}/\mathrm{\&Delta;<figure-callout\; id="2"\; label="f"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">f</figure-callout>}}{2{\mathrm{\&Delta;\&omega;}}^2})=10\log \left(\frac{P_{\mathrm{noise}}}{P_{\mathrm{carrier}}}\right)---\left(1\right)$

Wherein

Be noise current, Γ is the shock-sensitive degree function (ISF) of noise source, q _MaxBe the maximum charge amplitude of oscillation of injecting on the node capacitor, equal the product of A and C, C is a node capacitor.

At first considering the phase noise that MOS channel current noise is introduced, is example with the second metal-oxide-semiconductor MN2:

The electron mobility of supposing technology is μ, and the gate oxide specific capacitance is C _OxThe bias voltage of MN2 is Vgs, and threshold voltage is Vth, and grid width is W/L with the ratio of grid length.

In the current limited district, A can be expressed as 4I _BIASR _p/ π, wherein I _BIASBe bias current.R _pBe the loss resistance of resonant cavity, can represent the product of resonant cavity quality factor and resonance frequency and resonant inductance, be Q ω ₀L.Therefore A can be expressed as formula (2), can see that A is directly proportional with (W/L):

$A=4\mathrm{\&mu;}{C}_{\mathrm{ox}}(W/L){(V_{\mathrm{gs}}-V_{\mathrm{th}})}^2{R}_p/\mathrm{\&pi;}---\left(2\right)$

In the first current limited district, A＜(Vgs-Vth), MN2 is operated in the saturation region.This moment, oscillation amplitude was very little, and the channel current of metal-oxide-semiconductor can be approximately the stationary noise source:

$\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="i\; ds"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">i</figure-callout>}}_{\mathrm{ds}}^{}}=4\mathrm{kT\&gamma;}{g}_m=4\mathrm{kT\&gamma;}{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}(W/L)(V_{\mathrm{GS}}-V_{\mathrm{TH}})\&infin;W/L---\left(3\right)$

In the saturation region, it doesn't matter for the ISF of MN2 and W/L, can know that by formula (1) and (2), (3) noise carrier power ratio and W/L are inversely proportional to:

$\frac{P_{\mathrm{noise}}}{P_{\mathrm{carrier}}}=\frac{{\mathrm{\&Gamma;}}_{\mathrm{<figure-callout\; id="2"\; label="rms"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">rms</figure-callout>}}^2}{2{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">C</figure-callout>}}^2\mathrm{\&Delta;}{\mathrm{\&omega;}}^2}\&CenterDot;\frac{\stackrel{\&OverBar;}{i_{\mathrm{<figure-callout\; id="2"\; label="ds"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">ds</figure-callout>}}^2}}{{\mathrm{<figure-callout\; id="2"\; label="A"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">A</figure-callout>}}^2}\&infin;\frac{1}{(W/L)}---\left(4\right)$

In the second current limited district, A＞(Vgs-Vth), the MN2 part-time is operated in cut-off region.This moment, the channel current noise of MN2 can be expressed as a stationary noise source

With one-period function (α ²=(cos φ-cos Φ)) product:

$\stackrel{\&OverBar;}{i_{\mathrm{<figure-callout\; id="2"\; label="ds"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">ds</figure-callout>}}^2}=4\mathrm{kT\&gamma;}{g}_m=4\mathrm{kT\&gamma;}{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}(W/L)A(\cos \mathrm{\&phi;}-\cos \mathrm{\&Phi;})=\stackrel{\&OverBar;}{i_{n0}^2}\&CenterDot;{\mathrm{\&alpha;}}^2---\left(5\right)$

Wherein Φ is half angle of flow of MN2, equals π-arccos [(Vgs-Vth)/A].φ is the phase place of oscillator output.Periodic function α is included in the impulse function considers that the noise carrier power ratio can be expressed as:

$\frac{P_{\mathrm{noise}}}{P_{\mathrm{carrier}}}=\frac{{\mathrm{\&Gamma;}}_{\mathrm{<figure-callout\; id="2"\; label="rms"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">rms</figure-callout>}}^2}{2{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">C</figure-callout>}}^2\mathrm{\&Delta;}{\mathrm{\&omega;}}^2}\&CenterDot;\frac{\stackrel{\&OverBar;}{i_{\mathrm{<figure-callout\; id="2"\; label="ds"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">ds</figure-callout>}}^2}}{{\mathrm{<figure-callout\; id="2"\; label="A"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">A</figure-callout>}}^2}\&infin;{\mathrm{\&Gamma;}}_{\mathrm{rms}}^2---\left(6\right)$

Can see that the noise carrier power ratio is and Γ ² _RmsBe directly proportional.And Γ ² _RmsAnalytic solutions can be expressed as:

${\mathrm{\&Gamma;}}_{\mathrm{<figure-callout\; id="2"\; label="rms"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">rms</figure-callout>}}^2=\frac{1}{2\mathrm{\&pi;}}\underset{-\mathrm{\&Phi;}}{\overset{\mathrm{\&Phi;}}{\&Integral;}}{\sin }^2\left(\mathrm{\&phi;}\right){\left(\frac{\cos \left(\mathrm{\&phi;}\right)+\cos \left(\mathrm{\&Phi;}\right)}{\cos \left(\mathrm{\&Phi;}\right)}\right)}^2(\cos \left(\mathrm{\&phi;}\right)-\cos \left(\mathrm{\&Phi;}\right)\mathrm{d\&phi;}---\left(7\right)$

In the voltage-limited district, A equals VDD/2, can know that according to formula (1), (5) and (6) the noise carrier power ratio is directly proportional with W/L.The optimal value that therefore the noise carrier power ratio is only arranged in the second current limited district.With each circuit and technological parameter substitution formula (7), the expression formula that can get shock-sensitive degree function is:

${\mathrm{\&Gamma;}}_{\mathrm{<figure-callout\; id="2"\; label="rms"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">rms</figure-callout>}}^2=\frac{6\sin \left(\mathrm{\&Phi;}\right){\cos }^4\left(\mathrm{\&Phi;}\right)+23{\cos }^2\left(\mathrm{\&Phi;}\right)\sin \left(\mathrm{\&Phi;}\right)+16\sin \left(\mathrm{\&Phi;}\right)+15\mathrm{\&Phi;}\cos \left(\mathrm{\&Phi;}\right)-40{\cos }^2\left(\mathrm{\&Phi;}\right){\sin }^3\left(\mathrm{\&Phi;}\right)-60\mathrm{\&Phi;}{\cos }^3\left(\mathrm{\&Phi;}\right)}{60{\cos }^2\left(\mathrm{\&Phi;}\right)}---\left(8\right)$

Fig. 4 is to be under the 1.5GHz condition in frequency of oscillation, the relation curve of phase noise and NNMOS channel width-over-length ratio.Dotted line is the output phase noise curve of whole VCO among the figure, obtains through the cadence software emulation.Solid line is the phase noise that MN2 introduces among the figure, utilizes formula derivations such as (8) to obtain.At W/L is 32 o'clock, and phase noise reaches optimum point, and this is consistent with result that emulation is come out.

Next consider the phase noise that loss of resonator resistance R p introduces:

The noise power spectral density of Rp is expressed as:

$\stackrel{\&OverBar;}{i_{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">n</figure-callout>}}^2}=4\mathrm{kT\&Delta;f}/(R_p/2)---\left(9\right)$

Γ ² _RmsAnalytic solutions can be expressed as:

${\mathrm{\&Gamma;}}_{\mathrm{<figure-callout\; id="2"\; label="rms"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">rms</figure-callout>}}^2=\frac{1}{2\mathrm{\&pi;}}{\&Integral;}_{-\mathrm{\&pi;}}^{\mathrm{\&pi;}}{(-\sin \left(\mathrm{\&phi;}\right))}^2\mathrm{d\&phi;}---\left(10\right)$

With formula (8) and (9) substitution (1) Shi Kede be by the phase noise that Rp introduces:

$L\left(\mathrm{\&Delta;\&omega;}\right)=10\log (\frac{{\mathrm{\&Gamma;}}_{\mathrm{rms}}^2}{{\mathrm{<figure-callout\; id="2"\; label="q\; max"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">q</figure-callout>}}_{\max }^{}}\&CenterDot;\frac{\stackrel{\&OverBar;}{i_{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">n</figure-callout>}}^2}/\mathrm{\&Delta;<figure-callout\; id="2"\; label="f"\; filenames="HDA0000152644390000022.png"\; state="\{\{state\}\}">f</figure-callout>}}{2\mathrm{\&Delta;}{\mathrm{\&omega;}}^2})=10\log \left(\frac{\mathrm{KT}}{2A^2{C}^2{R}_p\mathrm{\&Delta;}{\mathrm{\&omega;}}^2}\right)---\left(11\right)$

In the current limited district, as frequency of oscillation ω ₀, under the fixing situation of the quality factor q of the channel dimensions W/L resonant cavity of metal-oxide-semiconductor, can know that according to formula (2) the sense value of the inductance L 3 among amplitude A and Fig. 1 is directly proportional.Simultaneously can know that according to formula (2) and (11) the sense value of phase noise and inductance L 3 is inversely proportional to.In the voltage-limited district, A is a definite value, can know that according to (11) formula phase noise is directly proportional with inductance L.Therefore the value of the corresponding inductance L 3 of phase noise has individual optimum point.In frequency of oscillation is under the 1.5GHz condition, as shown in Figure 5, and dotted line is the VCO output phase noise that obtains of circuit simulation and the relation curve of inductance L 3, and phase noise has optimum performance at the 4nH place.Solid line is the R through theoretical derivation _pThe phase noise of introducing is that 6nH place phase noise has optimum performance at inductance.Receive the influence of inductance process modeling to have certain deviation between theoretical value and the calculated value.

Adopting the voltage controlled oscillator reference frequency output of said method optimization is 0.75～1.5GHz, and frequency-tuning range reaches 83%, and phase noise at 1.21GHz frequency place is-125.84dBc/Hz1MHz, and FOM can reach-184, and power consumption is merely 2.25mW.

Claims (1)

1. the low low-power consumption wideband voltage controlled oscillator circuit of making an uproar mutually comprises a negative resistance oscillation structure and two buffer structures, and the negative resistance oscillation structure comprises negative resistance structure resonant network, it is characterized in that:

The 2nd PMOS pipe (MP2), the 3rd PMOS pipe (MP3), the 2nd NMOS pipe (MN2) and the 3rd NMOS pipe (MN3) constitute the negative resistance structure; Wherein the drain electrode and the 2nd NMOS of the grid of the 2nd PMOS pipe (MP2), the 3rd PMOS pipe (MP3) manage the grid of (MN2), the drain electrode of the 3rd NMOS pipe (MN3) is connected; As in-phase output end (CKP); The drain electrode of the grid of the 3rd PMOS pipe (MP3), the 2nd PMOS pipe (MP2) is managed the grid of (MN3) with the 3rd NMOS, the drain electrode of the 2nd NMOS pipe (MN2) is connected, as reversed-phase output (CKN);

Resonant inductance (L), switched capacitor array (SCA), first variable capacitance (Cvar1), second variable capacitance (Cvar2), first fixed capacity (C3), second fixed capacity (C4) constitute resonant network; A termination reversed-phase output (CKN) of an end of an end of the positive pole of first variable capacitance (Cvar1), first fixed capacity (C3), resonant inductance (L), switched capacitor array (SCA) wherein; Another termination in-phase output end (CKP) of the other end of one end of the positive pole of second variable capacitance (Cvar2), second fixed capacity (C4), resonant inductance (L), switched capacitor array (SCA); The other end of first fixed capacity (C3) is connected with the other end of second fixed capacity (C4); The negative pole of first variable capacitance (Cvar1) is connected with the negative pole of second variable capacitance (Cvar2), as the control voltage input terminal (Vctrl) of pierce circuit;

First filter capacitor (C1) and first filter inductance (L1) are parallelly connected as Power Noise Filter, the termination power VDD after the parallel connection, and the other end after the parallel connection is managed the source electrode of (MP2) with the 2nd PMOS, the source electrode of the 3rd PMOS pipe (MP3) is connected; Second filter capacitor (C2) and second filter inductance (L2) are parallelly connected as the substrate noise filter, the end ground connection after the parallel connection, and the other end after the parallel connection is managed the source electrode of (MN2) with the 2nd NMOS, the source electrode of the 3rd NPMOS pipe (MN3) is connected;

The one PMOS pipe (MP1) and NMOS pipe (MN1) constitute a buffer structure; The grid of the grid of the one PMOS pipe (MP1) and NMOS pipe (MN1) connects reversed-phase output (CKN); The drain electrode of the one PMOS pipe (MP1) is connected with the drain electrode that a NMOS manages (MN1), as the inversion clock output (CLKN) of pierce circuit; The 4th PMOS pipe (MP4) and the 4th NMOS pipe (MN4) constitute another buffer structure; The grid of the grid of the 4th PMOS pipe (MP4) and the 4th NMOS pipe (MN4) connects in-phase output end (CKP); The drain electrode of the 4th PMOS pipe (MP4) is connected with the drain electrode that the 4th NMOS manages (MN4), as the in-phase clock output (CLKP) of pierce circuit; The source electrode of the source electrode of the one PMOS pipe (MP1) and the 4th PMOS pipe (MP4) meets power vd D, the source ground of the source electrode of NMOS pipe (MN1) and the 4th NMOS pipe (MN4);

Described switched capacitor array (SCA) comprises 15 switching capacity unit; The structure of each switching capacity unit is identical; Comprise two MOM electric capacity, two inverters and a NMOS pipe; The drain electrode of the output termination NMOS pipe (MNs) of one end of the one MOM electric capacity (Cs1), first inverter (Inv1); The source electrode of the output termination NMOS pipe (MNs) of one end of the 2nd MOM electric capacity (Cs2), second inverter (Inv2), the grid of NMOS pipe (MNs) is connected with the input of first inverter (Inv1) and the input of second inverter (Inv2), as the gating input of this switching capacity unit; The other end of the one MOM electric capacity (Cs1) of all switching capacity unit connects, and as an end of switched capacitor array (SCA), the other end of the 2nd MOM electric capacity (Cs2) of all switching capacity unit connects, as the other end of switched capacitor array (SCA);

The gating input of a switching capacity unit in 15 switching capacity unit independently is provided with, as the one-level frequency band control selecting side (D1) of pierce circuit; The gating input of two switching capacity unit connects, as the secondary frequency band control selecting side (D2) of pierce circuit; The gating input of four switching capacity unit connects, as three grades of frequency band control selecting sides (D3) of pierce circuit; The gating input of eight switching capacity unit connects, as the level Four frequency band control selecting side (D4) of pierce circuit;

MOM electric capacity in the switching capacity unit adopts three-dimensional interdigital capacitor; Comprise the horizontally disposed plane of multilayer interdigital capacitor; Described plane interdigital capacitor is to be arranged on the metal film that pair of planar on the silicon substrate is the broach shape, and each metal film comprises parallel broach bar (C-2) and intercell connector (C-1), and intercell connector (C-1) is with a plurality of broach bars (C-2) and connect; Two metal films are the interdigitated setting; Two metal film location swaps of the plane interdigital capacitor of adjacent two layers, and plated-through hole (C-3) connection through being arranged on the intercell connector place, in the vertical direction forms the facade interdigital capacitor.

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