CN202551094U - Frequency offset estimating and eliminating system - Google Patents

Abstract

The utility model provides a frequency offset estimating and eliminating system. The system comprises a receiver, an analog-digital converter, a zero-cross detecting module, a decimation filter, a direct-current detecting module and a frequency offset estimating module, wherein the receiver is used for receiving baseband signals; the analog-digital converter converts analog signals of the baseband signals received by the receiver into single-bit signals x(n); the zero-cross detecting module is connected with the analog-digital converter and differentiates the absolute values of the input single-bit signals x(n), and signals y(n) output by the zero-cross detecting module are a string of pulse signals related to the frequencies of the baseband signals; the decimation filter connects and receives the pulse signals input by the zero-cross detecting module and outputs signals with n-time symbol rates; the direct-current detecting module converts the signals with n-time symbol rates, which are input by the decimation filter, into n paths of parallel signals with 1-time symbol rates, and then synchronously samples and selectively filters n paths of signals at the same time; and the frequency offset estimating module converts the output of the direct-current detecting module into frequency offset.

Description

Frequency offset estimating and elimination system

Technical field

The utility model relates to digital wireless communication field, and especially the signal processing field is specifically related to a kind of communication system that is used for, the frequency offset estimating and the elimination of Low Medium Frequency zero passage detection receiver institute acknowledge(ment) signal.

Background technology

Along with the develop rapidly of technology such as Internet of Things, the more and more many employings of many low-consumption wireless communication systems quilts, comprising bluetooth (BLUETOOTH), ZIGBEE, ANT or the like.These technology have all adopted the constant amplitude modulation system, GFSK/FSK/MSK for example, and this makes the design of transceiver to simplify greatly.

In the design of this type of transceiver, because transmitter adopts the direct frequency modulation (direct-modulation) or the open loop structure (open-loop) of low-power consumption, transmitting includes bigger frequency departure or frequency drift usually.For the effective reception signal, in the design of receiver, must take effective method carrier frequency is estimated accurately and to be followed the tracks of.

Traditional receiver adopts many bit A of I/Q binary channel C mode more, makes frequency offset estimating algorithm more complicated in the receiver, is not suitable for the realization of low power consumption and low cost.The utility model realize to propose a kind of framework of single-bit simplified receiver, and has solved the problem of frequency offset estimating and tracking in this system.

The utility model content

The technical problem that the utility model will solve is the corresponding relation between a kind of baseband signal direct current biasing and the intermediate-freuqncy signal frequency shift (FS) is provided, through reponse system, and the system of correction of frequency skew.

The utility model solves above-mentioned technical problem through such technical scheme:

A kind of frequency offset estimating and elimination system are provided, and this system comprises:

Receiver is in order to accept baseband signal;

Analog to digital converter, receive that receiver receives with baseband signal, and be converted into single-bit signal x (n);

The zero passage detection module, connection also receives the single-bit signal x (n) that analog to digital converter is imported, and the absolute value of single-bit signal x (n) digital signal is carried out differential, and the signal y (n) of zero passage detection module output is a string pulse signal relevant with base-band signal frequency;

Decimation filter, connection also receives the pulse signal by the input of zero passage detection module, and the signal of N times of symbol rate of output;

The direct current detection module, the parallel 1 times of symbol rate signal in N road of conversion of signals one-tenth with the N times of symbol rate of importing carries out sample-synchronous and selective filter to N road signal afterwards more simultaneously;

Frequency deviation estimating modules converts the output of direct current detection module into frequency offset.

As a kind of improvement, the direct current detection module comprises the sample-synchronous module, and in order to find out the optimum sampling path, the signal to noise ratio in optimum sampling path is optimum.

Compared with prior art, the utlity model has following advantage: utilize the frequency offset estimating and the elimination system of the utility model, can realize that multidiameter delay bit synchronous and every Lu Douke carry out real-time direct current/compensate of frequency deviation.Thereby the accumulation through a plurality of Frames of frequency offset estimating of the utility model and elimination system is used to regulate the frequency of receiver improves the whole performance of accepting system.

Description of drawings

Fig. 1 is the framework sketch map of the utility model frequency offset estimating and the system of elimination;

Fig. 2 is the configuration diagram of the direct current detection module in the utility model frequency offset estimating and the elimination system;

Fig. 3 is the configuration diagram of sample-synchronous module in the utility model frequency offset estimating and the elimination system;

Fig. 4 is the structural representation of selective filter module in the utility model frequency offset estimating and the elimination system.

Embodiment

Specify the embodiment of the utility model below in conjunction with accompanying drawing.

In Low Medium Frequency zero passage detection receiver, the frequency shift (FS) of signal has been directly changed into the direct current offset of baseband signal.Need detect the flip-flop of baseband signal through special method, reduce frequency shift (FS) to sign synchronization, the influence of sample-synchronous and signal demodulation.

The utility model just provides the corresponding relation between a kind of baseband signal direct current biasing and the intermediate-freuqncy signal frequency shift (FS), through reponse system, and the system of correction of frequency skew.

The utility model utilizes the method for parallel detection, and the direct current biasing in the baseband signal that estimation Low Medium Frequency zero passage detection receiver receives converts direct current biasing to corresponding frequency shift (FS), utilizes the frequency departure between reponse system cancellation receiver and the transmitter.As shown in Figure 1.Wherein, analog to digital converter ADC carries out zero passage detection in order to analog-signal transitions is become single-bit signal (1-bit) with convenient follow-up zero passage detection module.In unit interval signal through the number of times of zero crossing what, can be used for weighing the height of frequency.The zero passage of frequency-shift keying ripple is counted different with different carrier frequency, counts and can obtain the difference about frequency, the basic thought of zero passage detection method that Here it is so detect zero passage.The function that the zero passage detection module realizes is following:

y(n)＝diff(abs(x(n)))

To the absolute value differential of 1bit data x (n) of input, the signal y (n) of zero passage detection module output is a string pulse signal relevant with frequency input signal.

Decimation filter has two effects, and the first also is appreciated that to asking average the integration of input signal (frequency pulse); It two is to the signal down-sampling behind the integration, and the data rate of output is a N times of character rate.Frequency pulse then is converted into corresponding amplitude information through integration.The corresponding amplitude of high-frequency, the corresponding low amplitude value of low frequency.

As shown in Figure 2, the direct current detection module at first converts the signal (signal of promptly exporting via decimation filter) of the N times of symbol rate of importing to parallel N road 1 times of symbol rate signal.Again N road signal is carried out sample-synchronous and selective filter simultaneously afterwards.The formula of string and conversion is following:

y _n(k)＝x(n+Nk)，n＝1，2...N

Wherein, x (n+Nk) is the signal via decimation filter output, y _n(k) be conversion parallel signal afterwards.

The purpose of sample-synchronous module is to find out the optimum sampling path, and the signal to noise ratio in optimum sampling path is optimum.Therefore, the corresponding direct current estimated value in this path also is an optimal value.Shown in Figure 3 is exactly the sample-synchronous module.This module is at first carried out 1bit to input signal and is quantized, and under the situation that does not influence performance, reduces complexity.The correlation of utilization and local targeting sequencing is found out optimum sample path again.

The relevant formula that slides is following:

${\mathrm{stat}}_n\left(k\right)=\underset{m=1}{\overset{M}{\mathrm{\Σ}}}{x}_n(k+m)\×P\left(m\right),n=\mathrm{1,2},..N;k=\mathrm{1,2},...K$

K in the following formula is the relevant length of sliding.X is the input signal that 1bit quantizes.P then is local targeting sequencing, and length is M.

$\hat{N}={\mathrm{MAX}}_n\left({\mathrm{MAX}}_k\left({\mathrm{stat}}_n\left(k\right)\right)\right)$

Following formula is the judgement formula in optimum sampling path, at first in each path, asks value, again the result in N path relatively.

In the calculating optimum sample path, the N circuit-switched data is carried out selective filter.Selective filter in this patent only carries out filtering to the data that the sign bit variation takes place.For MSK or fsk signal, can simply be interpreted as the combination of two FM signals: fIF+f and fIF-f.These two FM signals convert corresponding range signal to through after zero passage detection and the decimation filter, and the amplitude of response is vIF-v and vIF+v, and wherein vIF is a known quantity.With the input of the data of having eliminated vIF as selective filter, when the sign bit of data changes, what these data (v (k-1), v (k)) before and after constantly characterized is exactly two corresponding range values of FM signal.

dcEst(k)＝(1-α)×dcEst(k-1)+α×symDc(k)

Variation has taken place in the symbol that k is input signal constantly.SymDc in the following formula (k) is the k amplitude difference of two corresponding FM signals, the just direct current biasing of signal constantly.Through the low pass filter filters out evaluated error, obtain final direct current biasing estimated value dcEst.α in the following formula has determined the bandwidth of low pass filter.The optimum sampling path is depended in the final output of selective filter.After sample-synchronous finishes, only need carry out direct current biasing and estimate the data in optional sampling path.

The output of direct current detection module is frequency offset through the appraising frequency bias module converts, and computing formula is following:

Fs is the ADC sample frequency of system, and dcGain then is the DC current gain of decimation filter.

Because whole testing process needs certain convergence time; Can utilize one or more Frame to come estimating frequency offset; After the data convergence, adjust the local frequency of receiver again, reduce the influence of frequency shift (FS) with this to Low Medium Frequency zero passage detection receiver demodulation performance.

Blanket above-mentioned execution mode, the utility model utilization:

Direct current/appraising frequency bias: utilize the corresponding relation of decimation filter output and direct current and frequency deviation that frequency deviation is estimated in real time, and utilize BREATHABLE BANDWIDTH FILTER TO CONTROL tracking velocity and precision;

Parallel detection/optimum sampling Path selection: utilize parallel processing, estimate simultaneously and compensate a plurality of assumed position sample sequences, and utilize the output result and carry out synchronously;

Selective filter: the input data of utilizing selective filter to select direct current to estimate, get rid of the data that influence precision, improve the accuracy of direct current/frequency deviation valuation.

Utilize the direct current/frequency offset estimating of the utility model, can realize that multidiameter delay bit synchronous and every Lu Douke carry out real-time direct current/compensate of frequency deviation.Thereby the accumulation of the direct current/frequency offset estimating of the utility model through a plurality of Frames is used to regulate the frequency of receiver improves the whole performance of accepting system.

The above is merely the preferred embodiments of the utility model; The protection range of the utility model does not exceed with above-mentioned execution mode; As long as the equivalence that those of ordinary skills do according to the utility model institute disclosure is modified or changed, all should include in the protection range of putting down in writing in claims.

Claims (2)

1. frequency offset estimating and elimination system is characterized in that this system comprises:

Receiver is in order to accept baseband signal;

Analog to digital converter receives the baseband signal that receiver receives, and is converted into single-bit signal x (n);

The zero passage detection module, connection also receives the single-bit signal x (n) that analog to digital converter is imported, and the absolute value of single-bit signal x (n) is carried out differential, and the signal y (n) of zero passage detection module output is a string pulse signal relevant with base-band signal frequency;

Decimation filter, connection also receives the pulse signal by the input of zero passage detection module, and the signal of N times of symbol rate of output;

The direct current detection module, the signal with N times of symbol rate of decimation filter input converts the 1 times of symbol rate signal in parallel N road to, again N road signal is carried out sample-synchronous and selective filter simultaneously afterwards;

Frequency deviation estimating modules converts the output of direct current detection module into frequency offset.

2. frequency offset estimating according to claim 1 and elimination system is characterized in that the direct current detection module comprises the sample-synchronous module, and in order to find out the optimum sampling path, the signal to noise ratio in optimum sampling path is optimum.

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