CN103812505B - bit synchronization lock detector - Google Patents
bit synchronization lock detector Download PDFInfo
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- CN103812505B CN103812505B CN201410040561.4A CN201410040561A CN103812505B CN 103812505 B CN103812505 B CN 103812505B CN 201410040561 A CN201410040561 A CN 201410040561A CN 103812505 B CN103812505 B CN 103812505B
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Abstract
A kind of bit synchronization lock detector that the present invention proposes, it is desirable to provide a kind of device that the locking instruction of bit synchronization ring can be provided.The technical scheme is that: in genlocing decision circuit in place, the integrate-dump wave filter being controlled by same phase control pulse is sequentially connected in series absolute value circuit and fixing accumulator composition in-phase branch of counting, the integrate-dump wave filter being controlled by anti-phase control pulse is sequentially connected in series absolute value circuit, fixing accumulator and the fader composition inverting branch of counting, and two branch roads are jointly connected one and export the comparator of locking instruction；Bit synchronization loop circuit exports the control pulse of phase 180 degree simultaneously, control the integrate-dump circuit on two branch roads respectively to input baseband signal as the integrate-dump computing that time width is 1 code element, comparator compares from the operation result of in-phase branch and the locking decision thresholding of inverting branch, the instruction whether output decision bit synchronous ring locks.
Description
Technical field
The present invention relates to a kind of coherent communication system is mainly used in the method that the detection of bit synchronization lock-out state judges.
Background technology
In digital communication systems, transmitting terminal according to the time sequencing determined, each in the digital pulse train of transmission one by one
Code element.And the judgement moment of sampling accurately must be had could correctly to adjudicate sent code element at receiving terminal, therefore, receiving terminal must
One commutator pulse sequence determining the sampling judgement moment must be provided.The repetition rate of this commutator pulse sequence must be with transmission
Digital pulse train is consistent, is sampled adjudicating to receiving symbol in the optimal judgement moment (or referred to as optimum phase moment) simultaneously.
Symbol synchronization can be called producing such commutator pulse sequence at receiving terminal, or claim bit synchronization.Realize bit synchronous method and
Carrier synchronization is similar to, and has direct method (self-synchronizing method) and inserts pilot tone system (external synchronization method) two kinds, and direct method is divided into filter method
And phase locking technique.In coherent communication, receiver signal obtains baseband signal after carrier coherent demodulating, comprises in baseband signal
" 0 " and the input symbols of " 1 ", be respectively adopted symmetrical different wave and represent, bit sync module is used for positioning input symbols and adjusts
System is interval and carries out symbol demodulation by matched filtering.In conventional process, bit synchronous lock-in detection is the most independently carried out, but
In relying on follow-up to process, frame synchronization state or other relevant informations judge, this processing mode be practically without accurately to
Go out bit synchronization lock-out state, and in the engineer applied in the fields such as space flight measurement and control, satellite application, high-speed digital transmission, user often needs
Accurately to understand the bit synchronization lock-out state of present receiving machine.
Summary of the invention
In order to overcome the drawbacks described above of bit synchronization lock-in detection in conventional process, it is an object of the invention to provide one can fit
Answer broader SNR ranges, and can reduce input baseband signal power control requirement, detect result of determination more accurately and reliably,
The locking instruction of bit synchronization ring can be provided, the bit synchronization ring lock-out state in coherent communication is carried out the device that detection judges.
The technical solution adopted for the present invention to solve the technical problems is: a kind of bit synchronization lock detector, including bit synchronization
Loop circuit and bit synchronization locking decision circuit, it is characterised in that: in genlocing decision circuit in place, it is controlled by same phase control arteries and veins
The integrate-dump wave filter of punching is sequentially connected in series absolute value circuit and fixing accumulator composition in-phase branch of counting, and is controlled by anti-phase control
The integrate-dump wave filter of pulse is sequentially connected in series absolute value circuit, fixing accumulator and the fader composition inverting branch of counting,
Above-mentioned two branch road is jointly connected one and exports the comparator of locking instruction；Bit synchronization loop circuit exports phase 180 degree simultaneously
Same phase control pulse and anti-phase control pulse, input baseband signal is made by the integrate-dump circuit controlled respectively on above-mentioned two branch roads
Time width is the integrate-dump computing of 1 code element, and integrate-dump operation result is respectively through control respective on above-mentioned two branch roads
Absolute value circuit, fixing accumulator of counting obtain two-way operation result, and wherein, the operation result of inverting branch is through gain-adjusted
Device with dynamically adjust gain coefficient and be multiplied and obtain locking decision thresholding, comparator is to from the operation result of in-phase branch and anti-phase
The locking decision thresholding on road compares, the instruction whether output decision bit synchronous ring locks.
The present invention has the advantages that compared to prior art
Two branch roads that the present invention uses phase place the most anti-phase are jointly connected one and export the bit synchronization locking decision circuit of locking instruction, position
When genlocing decision circuit enters lock-out state according to bit synchronization ring, input symbols has to the phase place of same phase control pulse with relevant
The phase place of system and anti-phase control pulse has the characteristic of inverted relationship, efficiently extracts out the essence during locking of reflection bit synchronization ring
Feature, simultaneously by the gain coefficient of fader is dynamically adjusted, by dynamically adjusting the effect of locking decision thresholding,
It is suitable for broader SNR ranges, reduces the power control requirements to input baseband signal.Therefore the present invention compares existing position together
The SNR ranges of step lock detecting method adapts to wider, and the power control requirements of input baseband signal is lower, it is not necessary to rely on follow-up
Frame synchronization state or the judgement of other relevant information in information processing.
The present invention compares existing bit synchronization lock detecting method and can provide and detect result of determination more accurately and reliably, and energy
Enough adapt to broader SNR ranges.
Accompanying drawing explanation
With embodiment, this patent is further illustrated below in conjunction with the accompanying drawings.
Fig. 1 is bit synchronization lock detecting method principle schematic of the present invention.
Fig. 2 is input symbols and with phase control pulse, the phase relation schematic diagram of anti-phase control pulse.
Detailed description of the invention
In the most preferred embodiment that Fig. 1 describes, bit synchronization lock detector specifically includes that and exports for realization simultaneously
Baseband signal is carried out by the same phase control pulse of phase 180 degree with the bit synchronization loop circuit of anti-phase control pulse with for realization
The bit synchronization locking decision circuit of locking decision.In other words, described bit synchronization lock detector by two integrate-dump wave filter,
Two absolute value circuits, two fixing count accumulator, a fader, a comparator and bit synchronization rings
NCO circuit forms.Fader uses multiplier to realize the adjustment of locking decision thresholding, and bit synchronization ring NCO circuit is permissible
Accumulator is used to realize the output with phase control pulse Yu anti-phase control pulse.
The first integral of same phase control pulse that what bit synchronization locking decision circuit included being sequentially connected in series be controlled by reset wave filter, the
One absolute value circuit and the in-phase branch of the first fixing accumulator composition of counting, and be sequentially connected in series be controlled by anti-phase control pulse
Second integral reset wave filter, the second absolute value circuit, the second fixing count accumulator and anti-phase of fader composition
Road, above-mentioned two branch road is jointly connected one and exports the comparator of locking instruction.Bit synchronization loop circuit has output phase place phase simultaneously
Differ from the same phase control pulse of 180 degree and the bit synchronization ring digital oscillator NCO circuit of anti-phase control pulse, described bit synchronization ring
NCO circuit uses accumulator to realize, the same phase control pulse of bit synchronization ring NCO circuit and the production method of anti-phase control pulse
For: accumulator is same phase control pulse, to accumulator at the carry pulse carrying out phase control words producing in cumulative process
Highest order carries out the detection that 0 saltus step is 1 and is anti-phase control pulse.Above-mentioned two pulse controls two integrate-dump circuit respectively
To the baseband signal inputted as the integrate-dump computing that time width is 1 code element, the result of integrate-dump computing is respectively through absolutely
Value circuit, fixing accumulator of counting are obtained two-way operation result.The operation result of inverting branch is through fader and gain
Multiplication obtains locking decision thresholding, can dynamically adjust locking decision door by dynamically adjusting the gain coefficient of fader
Limit.In-phase branch under same phase control impulse action as the integrate-dump computing that time width is 1 code element, integrate-dump computing
Result obtain the integrated absolute of 1 code element through absolute value circuit, the above results through fixing accumulator of counting, consolidate
Accumulated value after the integration of the code element of fixed-point number takes absolute value adds noise figure；When inverting branch is made under anti-phase control impulse action
Between width be the integrate-dump computing of 1 code element, the result of integrate-dump computing obtains the long-pending of 1 code element through absolute value circuit
Dividing absolute value, the above results, through fixing count accumulator and fader, obtains noise figure and is multiplied by gain coefficient, Yi Jisuo
Determine decision threshold.The operation result of in-phase branch and locking decision thresholding input comparator, comparator compares the computing of in-phase branch
Result and the size of locking decision thresholding, if the operation result of in-phase branch is more than locking decision thresholding, adjudicate as bit synchronization ring
Locking, otherwise judgement does not locks for bit synchronization ring.
Baseband signal makees time width by being controlled by the integrate-dump wave filter of same phase control pulse and anti-phase control pulse respectively
Degree is the integrate-dump computing of 1 code element, and the result of integrate-dump computing is respectively through absolute value circuit, fixing accumulator of counting
Obtaining two-way operation result, wherein the operation result of inverting branch is multiplied with gain coefficient through fader and obtains locking decision
Thresholding, the operation result of in-phase branch and locking decision thresholding input comparator, comparator is according to comparative result output locking instruction.
If bit synchronization loop circuit enters lock-out state, then the same phase control pulse that input symbols exports with bit synchronization ring NCO circuit
Phase place has the phase place of same phase relation and anti-phase control pulse and has inverted relationship, then the operation result of in-phase branch is to fixing
Accumulated value after the integration of the code element counted takes absolute value adds noise figure, and the operation result of inverting branch is that noise figure is multiplied by gain
Coefficient, the operation result meeting in-phase branch under suitable gain coefficient is more than locking decision thresholding, and comparator decision is that position is same
Step ring locking；If bit synchronization loop circuit does not enters into lock-out state, then input symbols and the output of bit synchronization ring NCO circuit
There is not fixing phase relation with phase control pulse, anti-phase control pulse, under suitable gain coefficient, be unsatisfactory for in-phase branch
Operation result more than locking decision thresholding, comparator decision is that bit synchronization ring does not locks.
Fixing accumulator of counting is made up of accumulator sum counter, and input data are added up by accumulator, unison counter
Count, export the value of accumulator and empty accumulator after the count value of enumerator reaches fixing counting, so circulate, Gu
The value of fixed-point number can be set according to emulation or debugging result, it is possible to dynamically configures in circuit running.
Fader is made up of multiplier, and its gain coefficient dynamically can configure in circuit running, for according to not
Same signal to noise ratio dynamically adjusts locking decision thresholding.
Fig. 2 describes same phase control pulse, the phase of anti-phase control pulse that input symbols exports with bit synchronization ring NCO circuit
Position relation.Foregoing circuit can be as a part for bit synchronization loop circuit, can be real in programmable gate array chip fpga chip
Existing, it is possible to realize in asic chip, its simple in construction, take hardware resource less.
Claims (8)
1. a bit synchronization lock detector, including bit synchronization loop circuit and bit synchronization locking decision circuit, it is characterized in that: in genlocing decision circuit in place, the integrate-dump wave filter being controlled by same phase control pulse is sequentially connected in series absolute value circuit and fixing accumulator composition in-phase branch of counting, the integrate-dump wave filter being controlled by anti-phase control pulse is sequentially connected in series absolute value circuit, fixing accumulator and the fader composition inverting branch of counting, and above-mentioned two branch road is jointly connected one and exports the comparator of locking instruction；nullBit synchronization loop circuit exports the same phase control pulse of phase 180 degree and anti-phase control pulse simultaneously，Control the integrate-dump circuit on above-mentioned two branch roads respectively to input baseband signal as the integrate-dump computing that time width is 1 code element，Integrate-dump operation result is respectively through the absolute value circuit each controlled on above-mentioned two branch roads、Fixing accumulator of counting obtains two-way operation result，Wherein，Inverting branch under anti-phase control impulse action as the integrate-dump computing that time width is 1 code element，The result of integrate-dump computing obtains the integrated absolute of 1 code element through absolute value circuit，The operation result of above-mentioned inverting branch is through fixing count accumulator and fader，Obtain and dynamically adjust the locking decision thresholding that gain coefficient is multiplied，The operation result of in-phase branch and locking decision thresholding input comparator，Comparator compares the operation result of in-phase branch and the size of locking decision thresholding，If the operation result of in-phase branch is more than locking decision thresholding, adjudicates and lock into bit synchronization ring，Otherwise judgement does not locks for bit synchronization ring；Comparator compares from the operation result of in-phase branch and the locking decision thresholding of inverting branch, the instruction whether output decision bit synchronous ring locks.
2. the bit synchronization lock detector as described in claim 1, it is characterised in that: described bit synchronization lock detector is made up of two integrate-dump wave filter, two absolute value circuits, two fixing count accumulator, a fader, a comparator and bit synchronization ring NCO circuit.
3. the bit synchronization lock detector as described in claim 1 or 2, it is characterized in that: in-phase branch under same phase control impulse action as the integrate-dump computing that time width is 1 code element, the result of integrate-dump computing obtains the integrated absolute of 1 code element through absolute value circuit, the above results through fixing accumulator of counting, obtains the accumulated value after the integration of the fixing code element counted takes absolute value plus noise figure.
4. the bit synchronization lock detector as described in claim 1, it is characterized in that: bit synchronization loop circuit has the same phase control pulse of output phase 180 degree simultaneously and the bit synchronization ring numerically-controlled oscillator NCO circuit of anti-phase control pulse, described bit synchronization ring NCO circuit uses accumulator to realize.
5. the bit synchronization lock detector as described in claim 4, it is characterized in that: the same phase control pulse of bit synchronization ring NCO circuit with the production method of anti-phase control pulse is: accumulator is same phase control pulse at the carry pulse carrying out phase control words producing in cumulative process, the highest order of accumulator is carried out the detection that 0 saltus step is 1 and is anti-phase control pulse.
6. the bit synchronization lock detector as described in claim 5, it is characterized in that: if bit synchronization ring does not enters into lock-out state, then there is not fixing phase relation with same phase control pulse, the anti-phase control pulse of the output of bit synchronization ring NCO circuit in input symbols, the operation result being unsatisfactory for in-phase branch under suitable gain coefficient is more than locking decision thresholding, and comparator decision is that bit synchronization ring does not locks.
7. the bit synchronization lock detector as described in claim 1, it is characterized in that: fixing accumulator of counting is made up of accumulator sum counter, input data are added up by accumulator, unison counter counts, export the value of accumulator and empty accumulator after the count value of enumerator reaches fixing counting, so circulation, the fixing value counted is set according to emulation or debugging result, or dynamically configures in circuit running.
8. the bit synchronization lock detector as described in claim 1, it is characterised in that: fader is made up of multiplier, and its gain coefficient dynamically can configure in circuit running, for dynamically adjusting locking decision thresholding according to different signal to noise ratios.
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| CN201410040561.4A CN103812505B (en) | 2014-01-27 | 2014-01-27 | bit synchronization lock detector |
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| CN201410040561.4A CN103812505B (en) | 2014-01-27 | 2014-01-27 | bit synchronization lock detector |
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| CN103812505B true CN103812505B (en) | 2016-12-07 |
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| CN105391539B (en) * | 2015-10-18 | 2018-08-10 | 中国电子科技集团公司第十研究所 | QPSK carrier synchronization lock detectors |
| CN106291608B (en) * | 2016-07-11 | 2019-02-15 | 广东工业大学 | A kind of GPS bit synchronization locking method of inspection |
| CN106941353A (en) * | 2017-02-21 | 2017-07-11 | 江汉大学 | A kind of time-domain signal optimization Simulation system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101776752A (en) * | 2010-01-29 | 2010-07-14 | 中国科学院空间科学与应用研究中心 | Precise tracking and measuring method of high dynamic signal of air fleet link |
| CN101800540A (en) * | 2010-03-15 | 2010-08-11 | 中国电子科技集团公司第十研究所 | Locking and false locking judging circuit |
| CN103414493A (en) * | 2013-08-02 | 2013-11-27 | 北京航空航天大学 | General incoherent direct sequence spread spectrum signal tracking method |
| CN103457629A (en) * | 2013-09-05 | 2013-12-18 | 中国电子科技集团公司第十研究所 | Auxiliary phase discrimination circuit of PN code loop |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2009170968A (en) * | 2008-01-10 | 2009-07-30 | Futaba Corp | Super-broadband wireless transmitter, super-broadband wireless receiver, and super-broadband wireless transmitter/receiver |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101776752A (en) * | 2010-01-29 | 2010-07-14 | 中国科学院空间科学与应用研究中心 | Precise tracking and measuring method of high dynamic signal of air fleet link |
| CN101800540A (en) * | 2010-03-15 | 2010-08-11 | 中国电子科技集团公司第十研究所 | Locking and false locking judging circuit |
| CN103414493A (en) * | 2013-08-02 | 2013-11-27 | 北京航空航天大学 | General incoherent direct sequence spread spectrum signal tracking method |
| CN103457629A (en) * | 2013-09-05 | 2013-12-18 | 中国电子科技集团公司第十研究所 | Auxiliary phase discrimination circuit of PN code loop |
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