CN202395752U - All-digital delay phase-locked loop circuit for Nandflash controller - Google Patents
All-digital delay phase-locked loop circuit for Nandflash controller Download PDFInfo
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- CN202395752U CN202395752U CN2011205384298U CN201120538429U CN202395752U CN 202395752 U CN202395752 U CN 202395752U CN 2011205384298 U CN2011205384298 U CN 2011205384298U CN 201120538429 U CN201120538429 U CN 201120538429U CN 202395752 U CN202395752 U CN 202395752U
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Abstract
The utility model provides an all-digital delay phase-locked loop circuit for a Nandflash controller. The all-digital delay phase-locked loop circuit comprises a main numerical control delay line, a secondary numerical control delay line, a time-digital conversion unit, a phase discriminator and a controller, wherein the time-digital conversion unit is used for measuring delay time from an input clock to an output clock at startup, and then generating a setting signal for setting the controller; the phase discriminator is used for comparing phases of the input clock and the delayed output clock and transferring comparative results to the controller; and the controller is used for controlling the delay time of the main numerical control delay line and the secondary numerical control delay line according to the comparative results. The circuit disclosed by the utility model is compatible with the Nandflash and can work at a synchronous mode, that is, the interface is used for transmitting data in a DDR (Double Data Rate) form; and the data transmission rate is improved, the unnecessary signal turnover is eliminated and the power consumption is greatly reduced.
Description
Technical field
The utility model relates to integrated circuit fields, particularly relates to a kind of digital delay locked-loop circuit of the Nandflash of being used for controller.
Background technology
Existing a kind of digital delay phase-locked loop circuit; The patent No. is CN201010502274.2; Comprise delay line, phase discriminator, frequency divider, this circuit can not be directly applied for the Nandflash interface (the Nand-flash internal memory is a kind of of flash internal memory, the non-linear macrocell pattern of its inner employing) of ONFI2.0 standard; Existing digital dll scheme all is to be applied to the DDR sdram controller basically, only is used for read channel.But in the Nandflash of ONFI2.0 standard controller, all need phase shift on write access and the read channel.
For this reason, need a kind of digital delay locked-loop circuit that is used for the Nandflash controller of design.
The utility model content
Can not adapt to the work of Nandflash interface in order to solve existing phase-locked loop circuit, the utility model provides a kind of digital delay locked-loop circuit of the Nandflash of being used for controller.
The technical scheme that the utility model adopts is: comprise main numerical control delay line, from numerical control delay line, time figure converting unit, phase discriminator and controller; Input clock generation asserts signal after the time of delay of output clock was carried out set to controller when the time figure converting unit was measured start; The phase place of the output clock after phase discriminator compares input clock and postpones; Comparative result is passed to controller, and controller is controlled main numerical control delay line according to comparative result and from time of delay of numerical control delay line.
Preferably, said main numerical control delay line comprises a plurality of delay cells, and each delay cell is made up of coarse adjustment modular circuit and accurate adjustment modular circuit.
Preferably, said main numerical control delay line comprises 4 delay cells.
Preferably, saidly comprise a delay cell from the numerical control delay line, each delay cell is made up of coarse adjustment modular circuit and accurate adjustment modular circuit.
The circuit compatibility ONFI 2.0 of the utility model and the Nandflash of above standard; Can work under the synchronous mode (Synchronous Mode); Be the form transmission data of interface, improved fast data transmission rate, in write/read operation, all need carry out 90 ° of phase shifts the DQS signal with DDR.Adopt 1 main delay line and 2 structures from delay line, main delay line is used for locking, 1 phase shift (being used for write access) that is used to export DQS from delay line, and another is used to import the phase shift (being used for read channel) of DQS from delay line.Simultaneously, consider that main delay line after locking, before the beginning next time adjustment, does not need work, gate is made in the reference clock input of main delay line handled, eliminated unnecessary signal upset, greatly reduced power consumption.
Description of drawings
Fig. 1 is the schematic diagram of a kind of embodiment of the utility model;
Fig. 2 is the circuit diagram of a kind of embodiment of the utility model;
Fig. 3 is the coarse adjustment module circuit diagram;
Fig. 4 is the accurate adjustment module circuit diagram;
Fig. 5 is time figure conversion unit circuit figure;
Fig. 6 is the circuit diagram of this circuit application in the Nandflash controller.
Embodiment
Execution mode below in conjunction with accompanying drawing provides the utility model is done further detailed explanation:
As shown in Figure 1; Be a kind of embodiment of the utility model; Comprise main numerical control delay line, from numerical control delay line, time figure converting unit, phase discriminator and controller; Input clock generation asserts signal after the time of delay of output clock was carried out set to controller when the time figure converting unit was measured start; Phase discriminator relatively input clock CLKIN with postpone after the phase place of output clock CLKOUT, comparative result is passed to controller, controller is controlled main numerical control delay line according to comparative result and from time of delay of numerical control delay line.From Fig. 1, can know; Controller output end is used to control its time of delay with main numerical control delay line, be connected from the numerical control delay line, and an end of time figure converting unit is connected with input clock; It is connected the other end and control, is used for according to input clock signal controller being carried out set; Output clock CLKOUT after the input of phase discriminator connects input clock CLKIN and postpones, its output is connected with controller, and the signal that is used for two clocks of comparison is given controller.
Preferably, said main numerical control delay line comprises a plurality of delay cells, and each delay cell is made up of coarse adjustment modular circuit and accurate adjustment modular circuit.Preferably, said main numerical control delay line comprises 4 delay cells.Preferably, saidly comprise a delay cell from the numerical control delay line, each delay cell is made up of coarse adjustment modular circuit and accurate adjustment modular circuit.
As shown in Figure 2, be the circuit diagram of a kind of embodiment of the utility model, reference clock CLK_REF is input to time figure converting unit and main numerical control delay line respectively through the CLK_GATE signal after the TUNE_EN signal gate of controller.Controller is externally adjusted under the request signal DLL_REQ effect and is provided the original numerical value in the TDC_CLEAR signal removal time figure converting unit earlier, provides the TDC_EN signal again, and the time figure converting unit is started working.The time figure converting unit will return to controller to the rough calculation value TDC_INIT of clock cycle after a clock cycle, be used as the initial value of coarse adjustment sign indicating number C_CODE.
Phase discriminator is CLK_GATE signal and the phase relation between the P360 signal after the main numerical control delay line delay relatively.When the leading P360 of CLK_GATE phase place, phase discriminator sends the UP signal to controller, indicates it to increase the delay of main numerical control delay line; When CLK_GATE phase lag P360, phase discriminator sends the DOWN signal to controller, indicates it to reduce the delay of main numerical control delay line.
Coarse adjustment sign indicating number C_CODE controls main numerical control delay line and the delay of coarse adjustment module from the numerical control delay line, and accurate adjustment sign indicating number F_CODE controls the delay of main numerical control delay line and accurate adjustment module from the numerical control delay line.Controller is according to UP and DOWN signal change coarse adjustment sign indicating number C_CODE and accurate adjustment sign indicating number F_CODE, and when UP and DOWN signal were all invalid, controller got into lock-out state, sends adjustment end signal DLL_DONE to the outside.
When DQS output enable signal DQS_OUTEN control is to Nandflash output DQS signal.DQS_OUTEN and CLK_REF are through one and behind the door, entering article one is output as the DQS_OUT signal of 90 ° of phase shifts from the numerical control delay line.
Get into second from the numerical control delay line from the DQS_IN signal of Nandflash input, be output as the DQS_DELAYED signal of 90 ° of phase shifts.
As shown in Figure 3, be the coarse adjustment module circuit diagram, the coarse adjustment module is made up of c coarse adjustment delay cell, and each coarse adjustment delay cell is by two input Port Multipliers of 1 not gate and 1 reverse output.The form of coarse adjustment control code is: low level is ' 0 ', and a high position is ' 1 '.Suppose that CLK_IN will be through exporting after 3 coarse adjustment delay cells, then coarse adjustment control code is: C_CODE [1-0] is ' 0 ', and C_CODE [c-2] is ' 1 '.
As shown in Figure 4, be the accurate adjustment module circuit diagram, the accurate adjustment module is made up of 1 buffer and f load.Sluggish structure is adopted in first load, and bigger time-delay is arranged, the time-delay of alternative a plurality of and door, thus save area and power consumption, all the other f load is two input nand gates.When accurate adjustment control code in f+1 position is ' 0 ' entirely, postpone minimum; When accurate adjustment control code in f+1 position is ' 1 ' entirely, postpone maximum.
As shown in Figure 5, be time figure conversion unit circuit figure, the time figure converting unit is made up of the accurate adjustment module of t+2 trigger, t two input nand gate, 4 series connection and the coarse adjustment delay cell of 4t series connection.The termination TDC_EN signal that resets of first trigger, the clock CLK_GATE behind the clock termination gate, input fixedly connects ' 1 ', and output START connects input and 4 accurate adjustment modules of second trigger simultaneously.The START signal through the accurate adjustment module of 4 series connection after again through 4t coarse adjustment delay cell of connecting.This 4t coarse adjustment delay cell is divided into the t group, and every group has 4 coarse adjustment delay cells, and every group output connects the input of t trigger of residue respectively.The output STOP signal of second trigger connects clock end, the set end of TDC_CLEAR signal trigger 3 and the reset terminal of trigger 4～(t+2) of t trigger of residue.The output Q [t-1:0] of t trigger of residue with the relation of finally exporting between the TDC_INIT [t-1:0] is: when 0≤i≤t-2, and TDC_INIT [i]=～(Q [i] &Q [i+1]); TDC_INIT [t-2]=～Q [t-2].
As shown in Figure 6; This circuit application is in the circuit diagram of Nandflash controller; The Nandflash controller sends DLL_REQ asks digital delay phase-locked loop to be adjusted according to current work clock CLK_REF, after digital delay phase-locked loop locking, and feedback DQS_DONE signal.The Nandflash controller can carry out write/read operation then.When Nandflash controller during to the Nandflash write data, DQS_OUTEN=1, thus export the DQS_OUT signal of 90 ° of phase shifts, drive the DQS that links to each other with Nandflash.When Nandflash controller during from the Nandflash read data, the DQS that is driven by Nandflash, i.e. the DQS_IN of input, after 90 ° of phase shifts, output DQS_DELAYED signal.Signal is used for DQ is sampled, and obtains read data.
In this specification, the utility model is described with reference to its certain embodiments.But, still can make various modifications and conversion obviously and not deviate from the spirit and the scope of the utility model.Therefore, specification and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (4)
1. digital delay locked-loop circuit that is used for the Nandflash controller; It is characterized in that; Comprise main numerical control delay line, from numerical control delay line, time figure converting unit, phase discriminator and controller; Input clock generation asserts signal after the time of delay of output clock was carried out set to controller when the time figure converting unit was measured start; Phase discriminator relatively input clock with postpone after the phase place of output clock, comparative result is passed to controller, controller is controlled main numerical control delay line according to comparative result and from time of delay of numerical control delay line.
2. digital delay locked-loop circuit according to claim 1 is characterized in that, said main numerical control delay line comprises a plurality of delay cells, and each delay cell is made up of coarse adjustment modular circuit and accurate adjustment modular circuit.
3. digital delay locked-loop circuit according to claim 2 is characterized in that, said main numerical control delay line comprises 4 delay cells.
4. digital delay locked-loop circuit according to claim 1 is characterized in that, saidly comprises a delay cell from the numerical control delay line, and each delay cell is made up of coarse adjustment modular circuit and accurate adjustment modular circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205384298U CN202395752U (en) | 2011-12-21 | 2011-12-21 | All-digital delay phase-locked loop circuit for Nandflash controller |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011205384298U CN202395752U (en) | 2011-12-21 | 2011-12-21 | All-digital delay phase-locked loop circuit for Nandflash controller |
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| CN202395752U true CN202395752U (en) | 2012-08-22 |
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| CN2011205384298U Expired - Fee Related CN202395752U (en) | 2011-12-21 | 2011-12-21 | All-digital delay phase-locked loop circuit for Nandflash controller |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103684438A (en) * | 2013-11-25 | 2014-03-26 | 龙芯中科技术有限公司 | Delay locked loop |
| CN103684437A (en) * | 2013-02-04 | 2014-03-26 | 中国科学院电子学研究所 | A time-delay chain control code self-adaptive rapid delay lock loop |
| CN106374916A (en) * | 2016-11-23 | 2017-02-01 | 成都信息工程大学 | Sequential control all-digital DLL control circuit and control method of NAND Flash controller |
| CN109831206A (en) * | 2019-02-13 | 2019-05-31 | 芯原微电子(上海)股份有限公司 | Delay lock loop and delay lock method |
-
2011
- 2011-12-21 CN CN2011205384298U patent/CN202395752U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103684437A (en) * | 2013-02-04 | 2014-03-26 | 中国科学院电子学研究所 | A time-delay chain control code self-adaptive rapid delay lock loop |
| CN103684437B (en) * | 2013-02-04 | 2016-08-10 | 中国科学院电子学研究所 | The adaptive quick delay-lock loop of time delay chain control code |
| CN103684438A (en) * | 2013-11-25 | 2014-03-26 | 龙芯中科技术有限公司 | Delay locked loop |
| CN103684438B (en) * | 2013-11-25 | 2016-06-08 | 龙芯中科技术有限公司 | Delay phase-locked loop |
| CN106374916A (en) * | 2016-11-23 | 2017-02-01 | 成都信息工程大学 | Sequential control all-digital DLL control circuit and control method of NAND Flash controller |
| CN106374916B (en) * | 2016-11-23 | 2023-08-18 | 深圳市富芯通科技有限公司 | Timing control all-digital DLL control circuit and NAND FLash controller control method |
| CN109831206A (en) * | 2019-02-13 | 2019-05-31 | 芯原微电子(上海)股份有限公司 | Delay lock loop and delay lock method |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120822 Termination date: 20121221 |