CN101482762A - Method and system for regulating CPU clock frequency - Google Patents
Method and system for regulating CPU clock frequency Download PDFInfo
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- CN101482762A CN101482762A CNA200910077450XA CN200910077450A CN101482762A CN 101482762 A CN101482762 A CN 101482762A CN A200910077450X A CNA200910077450X A CN A200910077450XA CN 200910077450 A CN200910077450 A CN 200910077450A CN 101482762 A CN101482762 A CN 101482762A
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Abstract
An embodiment of the invention provides a method for regulating CPU clock frequency and a system thereof, wherein, the method for regulating CPU clock frequency comprises the technical scheme that a double data rate controller is in a self-refreshing state in switching CPU clock frequency. The double data rate controller operates under a switched clock frequency after clock switching. Furthermore the synchronous clock relationship between the double data rate controller and the CPU is kept in the process of clock switching for obtaining a better accessing efficiency.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of method and system of regulating cpu clock frequency.
Background technology
Integrated chip (SoC, System on Chip) is also referred to as " system on a chip ", and it is generally used for portable type electronic product, as mobile phone, notebook computer etc.Along with use in the market that integrated chip is abundant, people have proposed increasing requirement to the design of integrated chip, need and to realize function as much as possible in minimum space with extremely low power consumption, particularly importantly reduce power consumption, so that the working time after the battery charge of realization portable product is long as far as possible.
Therefore, utilize dynamic electric voltage and frequency adjustment (DVFS, Dynamic Voltage andFrequency Scaling) technology, carry out dynamic-configuration according to CPU required service and performance class, CPU is in satisfy the lowest power consumption state of performance requirement, thereby realizes reducing the purpose of power consumption.As shown in Figure 1, integrated chip comprises system controller 11 (System Ctrl), Power Management Unit 12 (PMU, Power Management Unit), clock generation unit 13 (Clock Gen) and central processing unit 14 (CPU, Central Processing Unit).The work clock and the voltage of system controller 11 control clock generation units 13 and 12 pairs of central processing units 14 of Power Management Unit are regulated.
As shown in Figure 2, clock generation unit 13 comprises dominant frequency phaselocked loop 131 (CPLL, Core PhaseLocked Loop), outer frequency phase locked loop 132 (PPLL, Peripheral Phase LockedLoop), clock switch unit 133 (PLL Switch) and frequency division module 134 and frequency division module 135.Clock frequency is exported the two-way clock frequency behind the frequency phase locked loop 132 outside dominant frequency phaselocked loop 131 reaches, clock switch unit 133 realizes that the mutual switching of this two-way clock frequency and output clock frequency cpu_clk give the cpu central processing unit (not shown), the output clock frequency of outer frequency phase locked loop 132 can also directly be exported to and export clock frequency ddr2x_clk to Double Data Rate controller (not shown) after frequency division module 134 reduces frequency simultaneously, the clock frequency of 135 pairs of frequency division modules of frequency division module, 134 outputs is carried out frequency division, output bus clock frequency ahb_clk after the reduction frequency.Wherein, CPU and Double Data Rate controller are asynchronous clock.
When CPU needs the low performance grade, as shown in Figure 2, the clock frequency of CPU is switched to the clock frequency of outer frequency phase locked loop 132 outputs by clock switch unit 133, at this moment, CPU is by the parameter in the phaselocked loop frequency parameter configuration register in the configuration-system controller, to regulate the output clock frequency of dominant frequency phaselocked loop 131, by clock switch unit 133 clock frequency of CPU is switched to the clock frequency of dominant frequency phaselocked loop 133 outputs then.Like this, when regulating the CPU frequency of operation, can guarantee the operate as normal of Double Data Rate controller.
In realizing process of the present invention, the inventor finds that there are the following problems at least in the prior art:
During the dynamic adjustments cpu frequency, because the clock of CPU and Double Data Rate controller is an asynchronous clock, in order to realize regulating DDR in the cpu clock frequency process (Double Data Rate) Double Data Rate controller operate as normal, so increase the asynchronous clock interface between CPU and Double Data Rate controller, making the system logic complexity increase like this influences system effectiveness.
Summary of the invention
Embodiments of the invention provide a kind of method and system of regulating cpu clock frequency, can make Double Data Rate controller operate as normal in regulating the clock frequency process, and can reduce the logical complexity of system, thereby improve system effectiveness.
The embodiment of the invention provides a kind of method of regulating cpu clock frequency, comprising:
When the storer of Double Data Rate controller control is in the self-refresh state, the clock frequency of CPU is switched to the clock frequency of outer frequency phase locked loop output from the clock frequency of dominant frequency phaselocked loop output, make described Double Data Rate controller and CPU be operated in the clock frequency that described outer frequency phase locked loop is exported;
Obtain the target frequency parameter of CPU, the clock frequency of exporting according to the described dominant frequency phaselocked loop of the target frequency parameter regulation of described CPU is the target clock frequency of CPU;
After the storer of affirmation Double Data Rate controller control is in the self-refresh state, the clock frequency of the clock frequency of CPU frequency phase locked loop output outside described is switched to the target clock frequency of the CPU of described dominant frequency phaselocked loop output, make described Double Data Rate controller and CPU be operated in the target cpu clock frequency of dominant frequency phaselocked loop output.
The embodiment of the invention provides a kind of system that regulates cpu clock frequency, comprising: system controller and clock generation unit,
Wherein, this clock generation unit comprises dominant frequency phaselocked loop, outer frequency phase locked loop and clock switch unit;
This system controller, after the storer that is used for determining the control of Double Data Rate controller is in the self-refresh state, control this clock switch unit and carry out the clock switching, this clock switch unit switches to the clock frequency of frequency phase locked loop output outside this with the clock frequency of CPU from the clock frequency of this dominant frequency phaselocked loop output, thereby makes Double Data Rate controller and CPU be operated in the clock frequency of this outer frequency phase locked loop output;
This system controller obtains the target clock frequency parameter of CPU, and the clock frequency of exporting according to this dominant frequency phaselocked loop of target frequency parameter regulation of this CPU is the target clock frequency of CPU;
This system controller, after the storer of determining Double Data Rate controller control is in the self-refresh state, control this clock switch unit and carry out the clock switching, this clock switch unit switches to the target clock frequency of the CPU of this dominant frequency phaselocked loop output with the clock frequency of clock frequency frequency phase locked loop output outside this of CPU, thereby makes this Double Data Rate controller and CPU be operated in the target cpu clock frequency of this dominant frequency phaselocked loop output.
As can be seen from the previous technical solutions, in the process of regulating cpu clock frequency, Double Data Rate controller and CPU can be operated under the synchronous clock frequency, can make the storer operate as normal of Double Data Rate control like this, thereby need not between CPU and Double Data Rate controller, to increase the asynchronous clock interface, make the system logic complexity reduce like this, thereby improved efficient.
Description of drawings
In order to be illustrated more clearly in the technical scheme of the embodiment of the invention, the accompanying drawing of required use is done to introduce simply in will describing embodiment below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the control principle block diagram of dynamic adjustments CPU voltage and frequency in the prior art;
Fig. 2 is a structural representation of regulating the clock generation unit of cpu clock frequency in the prior art;
Fig. 3 is the process flow diagram of the method for the embodiment of the invention one dynamic adjustments cpu clock frequency;
Fig. 4 is the process flow diagram that clock switches in the method for the embodiment of the invention one dynamic adjustments cpu clock frequency;
Fig. 5 is the process flow diagram that clock switches in the method for the embodiment of the invention one dynamic adjustments cpu clock frequency;
Fig. 6 is the structural representation of the system of the embodiment of the invention two dynamic adjustments cpu clock frequencies;
Fig. 7 is the structural representation of system controller in the system of the embodiment of the invention two dynamic adjustments cpu clock frequencies;
Fig. 8 is the structural representation of clock generation unit in the system of the embodiment of the invention two dynamic adjustments cpu clock frequencies;
Fig. 9 is the structural representation of Double Data Rate controller in the system of the embodiment of the invention two dynamic adjustments cpu clock frequencies;
The synoptic diagram that Figure 10 shakes hands for signal between system controller in the system of the embodiment of the invention two dynamic adjustments cpu clock frequencies and the Double Data Rate controller.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
Embodiment one
As shown in Figure 3, a kind of method of regulating cpu clock frequency comprises:
Step 1: when the storer of Double Data Rate controller control is in the self-refresh state, the clock frequency of CPU is switched to the clock frequency of outer frequency phase locked loop output from the clock frequency of dominant frequency phaselocked loop output, make Double Data Rate controller and CPU be operated in the clock frequency that this outer frequency phase locked loop is exported;
Step 2: obtain the target frequency parameter of CPU, and the clock frequency of exporting according to the target frequency parameter regulation dominant frequency phaselocked loop of CPU is the target clock frequency of CPU;
Step 3: when the storer of Double Data Rate controller control is in the self-refresh state, the clock frequency of CPU is switched to the target clock frequency of the CPU of dominant frequency phaselocked loop output from the clock frequency of outer frequency phase locked loop output, make Double Data Rate controller and CPU be operated in the target clock frequency of the CPU of dominant frequency phaselocked loop output.
Can know, the Double Data Rate controller can control store, to realize reading and writing data, when the Double Data Rate controller is not worked, need not provides clock to storer, and Double Data Rate controller control store enters self-refresh state (self refresh), and storer oneself is finished to refresh and preserved its content, Double Data Rate controller control store withdraws from the self-refresh state, and the Double Data Rate controller is resumed work.Therefore, the Double Data Rate controller quits work, and storer is under the self-refresh state, and the clock switching of carrying out above-mentioned CPU is comparatively desirable.
As seen from the above, in the process of regulating cpu clock frequency, during the CPU switching clock frequency, the storer of Double Data Rate controller control is in the self-refresh state, the clock frequency of CPU is switched to the clock frequency of outer frequency phase locked loop output from the clock frequency of dominant frequency phaselocked loop output, thereby make Double Data Rate controller and CPU be operated in the clock frequency that described outer frequency phase locked loop is exported; Then, the clock frequency of exporting according to the target clock frequency adjustment dominant frequency phaselocked loop of CPU is the target clock frequency of CPU; At last, when the storer of Double Data Rate controller control is in the self-refresh state, the clock frequency of CPU is switched to the target clock frequency of the CPU of dominant frequency phaselocked loop output from the clock frequency of outer frequency phase locked loop output, make Double Data Rate controller and CPU be operated in the target cpu clock frequency of dominant frequency phaselocked loop output.In the process of regulating cpu clock frequency, Double Data Rate controller and CPU can be operated under the synchronous clock frequency, can make the storer operate as normal of Double Data Rate control like this, thereby need not between CPU and Double Data Rate controller, to increase the asynchronous clock interface, make the system logic complexity reduce like this, thereby improved efficient.
Wherein, Double Data Rate controller and CPU are operated under the synchronous clock frequency.
Wherein, for above-mentioned steps 1, before the storer of Double Data Rate controller control was in the self-refresh state, CPU need move application software, obtained the CPU self working state, thereby obtained the target frequency parameter of CPU self.For example, CPU is operated under the frequency of 400MHZ, and by the operation application software, the duty that obtains CPU this moment reduces, and at this moment, CPU can be according to application software, and the target cpu frequency parameter after obtaining the CPU duty and having reduced is as 200MHZ.
Be operated under the synchronous clock frequency with CPU and Double Data Rate controller below, the clock frequency of CPU is adjusted to 200MHZ (the target clock frequency of CPU) from 400MHZ (clock frequency of dominant frequency phaselocked loop output), the frequency of outer frequency phase locked loop output is that 100MHZ is an example, sets forth:
At first, CPU passes through application software, obtain the target frequency parameter of CPU self, when the storer of Double Data Rate controller control is in the self-refresh state, the clock frequency of CPU is switched to the clock frequency 100MHZ that outer frequency phase locked loop is exported from the clock frequency 400MHZ of dominant frequency phaselocked loop output, like this, CPU and Double Data Rate controller are operated in the clock frequency 100MHZ of outer frequency phase locked loop output; Then, system controller obtains the target clock frequency parameter that CPU needs, and the clock frequency of regulating the output of dominant frequency phaselocked loop according to the target clock frequency parameter of CPU is 200MHZ; At last, when the storer of Double Data Rate controller control is in the self-refresh state, the clock frequency 100MHZ that the clock frequency of CPU is exported from outer frequency phase locked loop switches to the target cpu clock frequency 200MHZ that the dominant frequency phaselocked loop is exported, and makes Double Data Rate controller and CPU be operated in the target clock frequency 200MHZ of the CPU of dominant frequency phaselocked loop output like this.
As seen from the above,, can make Double Data Rate controller and CPU be operated in the target clock frequency 200MHZ of the CPU of dominant frequency phaselocked loop output, can reduce the power consumption of CPU operate as normal like this by said method.
Wherein, the executive agent of above-mentioned steps 1, step 2 and step 3 can be system controller.The clock frequency of CPU is switched to clock frequency that outer frequency phase locked loop exports from the clock frequency of dominant frequency phaselocked loop output can be controlled the clock switch unit by system controller and finish, in like manner, the target clock frequency that the clock frequency of CPU is switched to the CPU of dominant frequency phaselocked loop output from the clock frequency of outer frequency phase locked loop output can be controlled the clock switch unit by system controller and finishes.Be that system controller is set forth below with the executive agent:
As shown in Figure 4, before the clock frequency that frequency phase locked loop was exported outside the clock frequency that system controller control clock switch unit is exported the clock frequency of CPU in the above-mentioned steps 1 from the dominant frequency phaselocked loop switched to, comprise: step 11:CPU is according to the output clock frequency of outer frequency phase locked loop, and the time sequence parameter of correspondence is deposited in the backup time sequence parameter register of Double Data Rate controller;
Particularly, the output clock frequency of the outer frequency phase locked loop of CPU basis deposits the time sequence parameter of correspondence in the backup time sequence parameter register of Double Data Rate controller in, so that after clock frequency is switched, the Double Data Rate controller is regulated the command timing of interface signal between itself and the storer according to this time sequence parameter, realizes the control to storer;
The output clock frequency of frequency phase locked loop outside the CPU basis, after the time sequence parameter of correspondence being deposited in the backup time sequence parameter register of Double Data Rate controller, the clock frequency of frequency phase locked loop output outside system controller control clock switch unit is exported the clock frequency of CPU from the dominant frequency phaselocked loop clock frequency switches to, make the Double Data Rate controller be operated in the clock frequency of outer frequency phase locked loop output, comprising:
Step 12: the Double Data Rate controller drag down bus do not work and control store enter the self-refresh state;
Step 13: the clock frequency of frequency phase locked loop output outside system controller control clock switch unit is exported the clock frequency of CPU from the dominant frequency phaselocked loop clock frequency switches to;
Step 14: the Double Data Rate controller is written into its time sequence parameter register with the time sequence parameter in its backup time sequence parameter register, and the latency delays locked loop is stable, and after delay-locked loop was stable, storer withdrawed from the self-refresh state;
Step 15: the Double Data Rate controller is drawn high under the bus clock frequency that frequency phase locked loop is exported outside and is resumed work.
After above-mentioned steps 11, system controller is by sending signal and judge the signal that the Double Data Rate controller feeds back to the Double Data Rate controller, whether the storer of confirming the control of Double Data Rate controller is in the self-refresh state, thereby carries out subsequent step, comprising:
System controller switches indicator signal to Double Data Rate controller tranmitting data register, and indication Double Data Rate controller control store enters the self-refresh state;
The Double Data Rate controller receives the clock that system controller sends and switches indicator signal, enters step 12: the Double Data Rate controller drags down that bus is not worked and control store enters the self-refresh state;
The Double Data Rate controller switches the indication feedback signal to the system controller tranmitting data register, and the storer of feedback Double Data Rate controller control has entered the self-refresh state;
System controller receives the clock switching indication feedback signal that the Double Data Rate controller sends, the storer of confirming the control of Double Data Rate controller has been in the self-refresh state, enters step 13: system controller control clock switch unit switches to the clock frequency of dominant frequency phaselocked loop output the clock frequency of outer frequency phase locked loop output.
Wherein, in above-mentioned steps 13: system controller control clock switch unit switches to the clock frequency of dominant frequency phaselocked loop output after the clock frequency that outer frequency phase locked loop exports, system controller is to Double Data Rate controller tranmitting data register handoff completion signal, and indication Double Data Rate controller control store withdraws from the self-refresh state;
The Double Data Rate controller receives the clock handoff completion signal that system controller sends, enter step 14: the Double Data Rate controller is written into its time sequence parameter register with the time sequence parameter in its backup time sequence parameter register, the latency delays locked loop is stable, after delay-locked loop was stable, storer withdrawed from the self-refresh state;
The Double Data Rate controller switches to the system controller tranmitting data register finishes feedback signal, the storer of feedback Double Data Rate controller control has withdrawed from the self-refresh state, enter step 15: the Double Data Rate controller is drawn high bus, resumes work under the clock frequency of Double Data Rate controller frequency phase locked loop output outside;
System controller receives the clock switching of Double Data Rate controller transmission and finishes feedback signal, system controller confirms that storer has withdrawed from the self-refresh state, and CPU knows that by the duty of inquiry system controller the Double Data Rate controller has been operated under the clock frequency of outer frequency phase locked loop output.
System controller obtains the target frequency parameter of CPU in the above-mentioned steps 2, clock frequency according to the described dominant frequency phaselocked loop output of the target frequency parameter regulation of CPU is the target clock frequency of CPU, particularly, system controller has phase-locked loop frequency parameter configuration register, can change the output clock frequency of the phaselocked loop of clock generation unit by the parameter in the configuration phaselocked loop frequency parameter configuration register, so CPU gives the target frequency parameter configuration of CPU according to duty the phase-locked loop frequency parameter configuration register of system controller.
Need to prove, the target clock frequency that system controller is regulated the stable CPU of dominant frequency phaselocked loop output may need hundreds of us (microsecond), in such " stand-by period ", Double Data Rate controller and CPU are operated in the clock frequency of outer frequency phase locked loop output.
In like manner, as shown in Figure 5, system controller control clock switch unit switches to the clock frequency of CPU before the target clock frequency of CPU of dominant frequency phaselocked loop output in the above-mentioned steps 3 from the clock frequency of outer frequency phase locked loop output, comprising:
Step 31:CPU is according to the target clock frequency of the CPU of dominant frequency phaselocked loop output, and the time sequence parameter of correspondence is deposited in the backup time sequence parameter register of Double Data Rate controller.
When the target clock frequency of CPU according to the CPU of the output of dominant frequency phaselocked loop, after the time sequence parameter of correspondence being deposited in the backup time sequence parameter register of Double Data Rate controller, system controller control clock switch unit is exported the clock frequency of CPU from outer frequency phase locked loop clock frequency switches to the target clock frequency of the CPU of dominant frequency phaselocked loop output, comprising:
Step 32: the Double Data Rate controller drag down bus do not work and control store enter the self-refresh state;
Step 33: system controller control clock switches to the target clock frequency that the unit switches to the clock frequency of outer frequency phase locked loop output the CPU of dominant frequency phaselocked loop output;
Step 34: the Double Data Rate controller is written into the time sequence parameter in its backup time sequence parameter register in its time sequence parameter register, and the latency delays locked loop is stable, and after delay-locked loop was stable, storer withdrawed from the self-refresh state;
Step 35: the Double Data Rate controller is drawn high bus and is resumed work under the target clock frequency of the CPU of dominant frequency phaselocked loop output.
After above-mentioned steps 31, system controller is by sending signal and judging that the signal that the Double Data Rate controller feeds back confirms whether the storer of Double Data Rate controller control is in the self-refresh state to the Double Data Rate controller, thereby carry out subsequent step, comprising:
System controller switches indicator signal to Double Data Rate controller tranmitting data register, and indication Double Data Rate controller control store enters the self-refresh state;
The Double Data Rate controller receives the clock that system controller sends and switches indicator signal, enters step 32: the Double Data Rate controller drags down that bus is not worked and control store enters the self-refresh state;
The Double Data Rate controller switches the indication feedback signal to the system controller tranmitting data register, and the storer of feedback Double Data Rate controller control has entered the self-refresh state;
System controller receives the clock switching indication feedback signal that the Double Data Rate controller sends, the storer of confirming the control of Double Data Rate controller is in the self-refresh state, enters step 33: system controller control clock switch unit switches to the clock frequency of outer frequency phase locked loop output the target clock frequency of the CPU of dominant frequency phaselocked loop output.
Above-mentioned steps 33 system controllers control clock switch unit switches to the clock frequency of outer frequency phase locked loop output after the target clock frequency of CPU of dominant frequency phaselocked loop output, system controller is to Double Data Rate controller tranmitting data register handoff completion signal, and indication Double Data Rate controller control store withdraws from the self-refresh state;
The Double Data Rate controller receives the clock handoff completion signal that system controller sends, enter step 34: the Double Data Rate controller is written into the time sequence parameter of its backup time sequence parameter register-stored in its time sequence parameter register, the latency delays locked loop is stable, after delay-locked loop was stable, storer withdrawed from the self-refresh state;
The Double Data Rate controller switches to the system controller tranmitting data register finishes feedback signal, the storer of feedback Double Data Rate controller control has withdrawed from the self-refresh state, enter step 35: the Double Data Rate controller is drawn high bus, and the Double Data Rate controller is resumed work under the target clock frequency of the CPU of dominant frequency phaselocked loop output;
System controller receives the clock switching of Double Data Rate controller transmission and finishes feedback signal, and system controller confirms that storer has withdrawed from the self-refresh state, and the Double Data Rate controller is worked under the clock frequency after the switching.
Can know, the clock that the said system controller sends to the Double Data Rate controller switch indicator signal and clock handoff completion signal can utilize clock switching signal mddrc_clksw_req high and low level (put 1 or put 0) distinguish realization, as mddrc_clksw_req is 1 o'clock, for clock switches indicator signal, be used to indicate Double Data Rate controller control store to enter the self-refresh state; Mddrc_clksw_req is 0 o'clock, is the clock handoff completion signal, is used to indicate Double Data Rate controller control store to withdraw from the self-refresh state.
In like manner, the clock that above-mentioned Double Data Rate controller sends to system controller switches indication feedback signal and clock and switches and finish feedback signal and also can utilize the high and low level of clock switching feedback signal mddrc_clksw_ack (put 1 or put 0) to distinguish realization, as mddrc_clksw_ack is 1 o'clock, for clock switches the indication feedback signal, the storer of feedback Double Data Rate controller control has entered the self-refresh state; Mddrc_clksw_ack is 0 o'clock, finishes feedback signal for clock switches, and the storer of feedback Double Data Rate controller control has withdrawed from the self-refresh state.
With a preferred implementation, come the method for dynamic adjustments cpu clock frequency is elaborated below:
1, the clock frequency of Double Data Rate controller and CPU is the synchronous clock frequency;
2, the output frequency of the outer frequency phase locked loop of CPU basis deposits the time sequence parameter of correspondence in the backup time sequence parameter register of Double Data Rate controller in;
3, system controller is 1 to Double Data Rate controller tranmitting data register switching signal mddrc_clksw_req, and indication Double Data Rate controller control store enters the self-refresh state;
4, the Double Data Rate controller receives that the clock switching signal mddrc_clksw_req that system controller sends is at 1 o'clock, the Double Data Rate controller is handled current multichannel read-write requests, in case current bus request disposes, promptly drag down bus READY signal (putting 0) and storer is not carried out read-write operation, Double Data Rate controller control store enters the self-refresh state;
5, the Double Data Rate controller sends clock to system controller to switch feedback signal mddrc_clksw_ack is 1 o'clock, and the storer of feedback Double Data Rate controller control has entered the self-refresh state;
6, to switch feedback signal mddrc_clksw_ack be 1 o'clock to the system controller clock that receives the Double Data Rate controller, and system controller control clock switch unit switches to the clock frequency that outer frequency phase locked loop is exported with the clock frequency of CPU from the clock frequency of dominant frequency phaselocked loop output;
7, system controller is 0 to Double Data Rate controller tranmitting data register switching signal mddrc_clksw_req, and indication Double Data Rate controller control store withdraws from the self-refresh state;
8, the Double Data Rate controller receives that the clock switching signal mddrc_clksw_req that system controller sends is at 0 o'clock, the Double Data Rate controller is written into the time sequence parameter of backup time sequence parameter register-stored in the time sequence parameter register, the latency delays locked loop is stable, after delay-locked loop was stable, storer withdrawed from the self-refresh state;
9, the Double Data Rate controller is 0 o'clock to system controller tranmitting data register switching feedback signal mddrc_clksw_ack, the storer of expression Double Data Rate controller control has withdrawed from the self-refresh state, the Double Data Rate controller is drawn high bus READY signal (putting 1), resumes work under the clock frequency of Double Data Rate controller frequency phase locked loop output outside;
10, to switch feedback signal mddrc_clksw_ack be 0 o'clock to the system controller clock that receives the Double Data Rate controller, system controller confirms that the storer of Double Data Rate controller control has withdrawed from the self-refresh state, and CPU inquiry system controller state knows that the Double Data Rate controller has been operated under the clock frequency of outer frequency phase locked loop output;
11, system controller obtains the target frequency parameter of CPU, the clock frequency of regulating the output of dominant frequency phaselocked loop according to the target cpu frequency parameter is the target clock frequency of CPU, in " stand-by period " of the target clock frequency of waiting for the CPU that the output of dominant frequency phaselocked loop is stable, work under the clock frequency of Double Data Rate controller and CPU frequency phase locked loop output outside earlier, after waiting for the target clock frequency stabilization of the CPU that the dominant frequency phaselocked loop is exported, refer again to the described flow process of above-mentioned 1-10 the clock frequency of outer frequency phase locked loop output is switched to the target clock frequency of the CPU of dominant frequency stabilized output, realized that promptly cpu clock frequency is adjusted to the target clock frequency of CPU.
Preferably, can be after CPU inquiry system controller state be known under the clock frequency of frequency phase locked loop output outside the Double Data Rate controller has been operated in, CPU just with the time sequence parameter of the target clock frequency correspondence of CPU to backing up in the time sequence parameter register.
In sum, the method for present embodiment dynamic adjustments cpu clock frequency, the power consumption that guarantees to regulate the operate as normal of Double Data Rate controller in the cpu clock frequency process and reduce system.
Embodiment two
As Fig. 6 and shown in Figure 8, a kind of system that regulates cpu clock frequency comprises system controller 5 and clock generation unit 6, and wherein, clock generation unit 6 comprises dominant frequency phaselocked loop 61, outer frequency phase locked loop 62 and clock switch unit 63,
System controller 5, after the storer that is used for determining the control of Double Data Rate controller is in the self-refresh state, control clock switch unit 63 carries out clock and switches, the clock frequency of frequency phase locked loop 62 outputs outside clock switch unit 63 is exported the clock frequency of CPU from dominant frequency phaselocked loop 61 clock frequency switches to, thus make Double Data Rate controller and CPU be operated in the clock frequency of these outer frequency phase locked loop 62 outputs;
This system controller obtains the target clock frequency parameter of CPU, and the clock frequency of exporting according to this dominant frequency phaselocked loop 61 of target frequency parameter regulation of this CPU is the target clock frequency of CPU;
After this system controller 5 confirms that the storer of Double Data Rate controller control is in the self-refresh state, control clock switch unit 63 carries out clock and switches, clock switch unit 63 switches to the target clock frequency of the CPU of dominant frequency phaselocked loop 61 outputs with the clock frequency of clock frequency frequency phase locked loop 62 outputs outside this of CPU, thereby makes Double Data Rate controller and CPU be operated in the target cpu clock frequency of dominant frequency phaselocked loop 61 outputs.
Can know, the Double Data Rate controller can control store to realize reading and writing data, when the Double Data Rate controller is not worked, need not provides clock to storer, Double Data Rate controller control store enters self-refresh state (self refresh), storer oneself is finished to refresh and is preserved memory content, and Double Data Rate controller control store withdraws from the self-refresh state, and the Double Data Rate controller is resumed work can be to memory read data or write data.Therefore, the Double Data Rate controller quits work, and storer is under the self-refresh state, and the clock switching of carrying out above-mentioned CPU is comparatively desirable.
As seen from the above, in the process of regulating cpu clock frequency, during the CPU switching clock frequency, the storer of Double Data Rate controller control is in the self-refresh state, the clock frequency of frequency phase locked loop output outside system controller control clock switch unit is exported the clock frequency of CPU from the dominant frequency phaselocked loop clock frequency switches to, thus make Double Data Rate controller and CPU be operated in the clock frequency of described outer frequency phase locked loop output; Then, system controller is the target clock frequency of CPU according to the clock frequency of the target clock frequency adjustment dominant frequency phaselocked loop output of CPU; At last, when the storer of Double Data Rate controller control is in the self-refresh state, system controller control clock switch unit is exported the clock frequency of CPU from outer frequency phase locked loop clock frequency switches to the target clock frequency of the CPU of dominant frequency phaselocked loop output, makes Double Data Rate controller and CPU be operated in the target cpu clock frequency of dominant frequency phaselocked loop output.In the process of regulating cpu clock frequency, Double Data Rate controller and CPU can be operated under the synchronous clock frequency, can make the storer operate as normal of Double Data Rate control like this, thereby need not between CPU and Double Data Rate controller, to increase the asynchronous clock interface, make the system logic complexity reduce like this, thereby improved efficient.
Wherein, system controller 5 can be integrated in one with clock generation unit 6, can certainly divide to be arranged, and the embodiment of the invention is not limited thereto.
Particularly, as shown in Figure 7, system controller 5 comprises:
Signal transmitting unit 52 is used for to Double Data Rate controller 7 tranmitting data register switching signals;
Signal receiving unit 53 is used to receive the clock switching feedback signal that Double Data Rate controller 7 sends.
System controller 5 passes through to Double Data Rate controller 7 tranmitting data register switching signals, and judges whether the storer of clock switching feedback signal affirmation Double Data Rate controller 7 controls that Double Data Rate controller 7 feeds back is in the self-refresh state.
Wherein, the clock switching signal comprises: the clock that system controller 5 indicates the storer of Double Data Rate controller 7 controls to enter the self-refresh state to Double Data Rate controller 7 being used to of sending switches indicator signal, and the clock handoff completion signal that is used to indicate the self-refresh state that the storer of Double Data Rate controller 7 controls withdraws from;
Wherein, clock switches feedback signal and comprises: the clock that the storer that Double Data Rate controller 7 feeds back 7 controls of Double Data Rate controller to system controller 5 being used to of sending has entered the self-refresh state switches the indication feedback signal, and the storer of the feedback Double Data Rate controller 7 controls clock that withdrawed from the self-refresh state switches and finishes feedback signal.
Further, system controller 5 also comprises:
Clock switch control unit 54, the clock switch unit 63 that is used to control clock generation unit 6 are exported between clock frequencies at the clock frequency of dominant frequency phaselocked loop 61 outputs and outer frequency phase locked loop 62 and are switched.
Main phase-locked loop frequency parameter configuration register 55, the clock frequency that is used for exporting according to the target frequency parameter regulation dominant frequency phaselocked loop of CPU is the target clock frequency of CPU.
Further, system controller 5 also comprises:
Frequency-dividing clock control module 56 is used to control the different frequency-dividing clock ratio of formation, is meant that as 2 frequency divisions input clock frequency is lowered half through frequency behind the frequency division, as 333MHZ:166MHZ, in like manner, 1 frequency division such as 120MHZ:120MHZ.
In conjunction with referring to shown in Figure 7, dominant frequency phaselocked loop 61, outer frequency phase locked loop 62 and clock switch unit 63 provide the synchronous clock frequency for CPU and Double Data Rate controller 7, after the storer of Double Data Rate controller 7 controls was in the self-refresh state, system controller 5 control clock switch units 63 were selected the output clock frequency of dominant frequency phaselocked loop 61 or outer frequency phase locked loop 62.
Further, clock generation unit 6 also comprises central processing unit frequency division module 64 and Double Data Rate controller frequency division module 65.The clock frequency of 64 pairs of inputs of central processing unit frequency division module of clock generation unit 6 is carried out the clock frequency clk_cpu of frequency division output CPU, and the clock frequency of 65 pairs of inputs of Double Data Rate controller frequency division module is carried out the clock frequency clk_ddr2x of frequency division output Double Data Rate controller.
In conjunction with referring to shown in Figure 7, the frequency dividing ratio of central processing unit frequency division module 64 and Double Data Rate controller frequency division module 65 realizes control by the frequency-dividing clock control module 56 of system controller 5, and clock control cell 56 control break frequency dividing ratios can't operate as normal with the low excessively Double Data Rate controller of avoiding exporting behind the frequency division 7 that causes of clock frequency.
As shown in Figure 9, Double Data Rate controller 7 comprises:
Backup time sequence parameter register 71, be used for system controller 5 and confirm that the storer of Double Data Rate controller control is in the self-refresh state, control clock switch unit 63 carries out before clock switches, and store the time sequence parameter that outer frequency phase locked loop 62 is exported the output target cpu clock frequency correspondence of the time sequence parameter of clock frequency correspondences and dominant frequency phaselocked loop 61;
Particularly, system controller 5 confirms that the storer of Double Data Rate controller 7 controls is in the self-refresh state, before the clock frequency that frequency phase locked loop was exported outside system controller control clock switch unit is exported the clock frequency of CPU from the dominant frequency phaselocked loop clock frequency switched to, CPU is according to the clock frequency of the output of outer frequency phase locked loop, and the time sequence parameter of correspondence is deposited in the backup time sequence parameter register of Double Data Rate controller;
System controller confirms that the storer of Double Data Rate controller control is in the self-refresh state, system controller is controlled before the target clock frequency of CPU that described clock switch unit switches to the clock frequency of the clock frequency of CPU frequency phase locked loop output outside described described dominant frequency phaselocked loop output, CPU is according to the target clock frequency of the CPU of dominant frequency phaselocked loop output, and the time sequence parameter of correspondence is deposited in the backup time sequence parameter register of Double Data Rate controller;
Time sequence parameter register 72 is used for being written into the time sequence parameter of backup time sequence parameter register 71 storages after the clock frequency switching of CPU;
Further, Double Data Rate controller 7 also comprises:
Signal generation unit 73 is used to generate clock and switches feedback signal;
Signal transmitting unit 74 is used for switching feedback signal to system controller 5 tranmitting data registers;
Signal receiving unit 75 is used for the clock switching signal that receiving system controller 5 sends.
Described clock switching signal comprises: the clock that system controller 5 indicates the storer of Double Data Rate controller 7 controls to enter the self-refresh state to Double Data Rate controller 7 being used to of sending switches indicator signal, and the clock handoff completion signal that is used to indicate the self-refresh state that the storer of Double Data Rate controller 7 controls withdraws from;
Described clock switches feedback signal and comprises: the clock that the storer that Double Data Rate controller 7 feeds back 7 controls of Double Data Rate controller to system controller 5 being used to of sending has entered the self-refresh state switches the indication feedback signal, and the storer of the feedback Double Data Rate controller 7 controls clock that withdrawed from the self-refresh state switches and finishes feedback signal.
Further, Double Data Rate controller 7 also comprises:
Delay-locked loop 76 is used for realizing control to storer according to the command timing that the time sequence parameters in the time sequence parameter register 72 are regulated interface signal between itself and the storer.
As Fig. 6 and shown in Figure 10, the clock that said system controller 5 sends to Double Data Rate controller 7 switches the high and low level that indicator signal and clock handoff completion signal can utilize clock switching signal mddrc_clksw_req (put 1 or put 0) distinguishes realization, as mddrc_clksw_req is 1 o'clock, for clock switches indicator signal, be used to indicate the storer of Double Data Rate controller 7 controls to enter the self-refresh state; Mddrc_clksw_req is 0 o'clock, is the clock handoff completion signal, is used to indicate the storer of Double Data Rate controller 7 controls to withdraw from the self-refresh state.
In like manner, it is 1 o'clock that the clock that above-mentioned Double Data Rate controller 7 sends to system controller 5 switches feedback signal mddrc_clksw_ack, for clock switches the indication feedback signal, the storer of feedback Double Data Rate controller control has entered the self-refresh state; The mddrc_clksw_ack that the Double Data Rate controller sends is 0 o'clock, finishes feedback signal for clock switches, and the storer of feedback Double Data Rate controller control has withdrawed from the self-refresh state.
Particularly, system controller 5 is by to Double Data Rate controller 7 tranmitting data register switching signals and judge that clock that Double Data Rate controller 7 feeds back switches the indication feedback signal and confirms whether the storer of Double Data Rate controller 7 controls is in the self-refresh state, so that determine whether the clock frequency of CPU is switched to the clock frequency that outer frequency phase locked loop 62 is exported from the clock frequency of dominant frequency phaselocked loop 61 outputs, comprising:
System controller 5 switches indicator signal to Double Data Rate controller 7 tranmitting data registers, and indication Double Data Rate controller control store enters the self-refresh state;
Double Data Rate controller 7 receives the clock that system controller 5 sends and switches indicator signal, and Double Data Rate controller 7 drags down that bus is not worked and control store enters the self-refresh state;
Double Data Rate controller 7 switches the indication feedback signal to system controller 5 tranmitting data registers, and the storer of feedback Double Data Rate controller control has entered the self-refresh state;
System controller 5 receives the clock switching indication feedback signal that Double Data Rate controller 7 sends, and confirms that the storer of Double Data Rate controller 7 controls is in the self-refresh state.Like this, system controller 5 control clock switch units 63 switch to the clock frequency that outer frequency phase locked loop 62 is exported with the clock frequency of CPU from the clock frequency of dominant frequency phaselocked loop 61 outputs.
And, with the clock frequency of CPU after the clock frequency of dominant frequency phaselocked loop 61 outputs switches to the clock frequency that outer frequency phase locked loop 62 exports, system controller 5 is to Double Data Rate controller 7 tranmitting data register handoff completion signals, and indication Double Data Rate controller control store withdraws from the self-refresh state;
Double Data Rate controller 7 receives the clock handoff completion signal that system controller 5 sends, the time sequence parameter that Double Data Rate controller 7 will back up 71 storages of time sequence parameter register is written in the time sequence parameter register 72, latency delays locked loop 76 is stable, after this delay-locked loop 76 was stablized, storer withdrawed from the self-refresh state;
Double Data Rate controller 7 switches to system controller 5 tranmitting data registers finishes feedback signal, the storer of feedback Double Data Rate controller control has withdrawed from the self-refresh state, Double Data Rate controller 7 is drawn high bus, resumes work under the clock frequency of Double Data Rate controller 7 frequency phase locked loop 62 outputs outside;
System controller 5 receives the clock switching of Double Data Rate controller 7 transmissions and finishes feedback signal, and system controller 5 confirms that storeies have withdrawed from the self-refresh state, and Double Data Rate controller 7 is worked under the clock frequency after the switching.
In like manner, system controller 5 is by switching indicator signal and judging whether the storer of signal affirmation Double Data Rate controller 7 controls that Double Data Rate controller 7 feeds back is in the self-refresh state to Double Data Rate controller 7 tranmitting data registers, the clock frequency of CPU is switched to the target clock frequency of the CPU of dominant frequency phaselocked loop 61 outputs from the clock frequency of outer frequency phase locked loop 62 outputs, comprising:
System controller 5 switches indicator signal to Double Data Rate controller 7 tranmitting data registers, and indication Double Data Rate controller control store enters the self-refresh state;
Double Data Rate controller 7 receives the clock that system controller 5 sends and switches indicator signal, and Double Data Rate controller 7 drags down that bus is not worked and control store enters the self-refresh state;
Double Data Rate controller 7 switches the indication feedback signal to system controller 5 tranmitting data registers, and the storer of feedback Double Data Rate controller control has entered the self-refresh state;
System controller 5 receives the clock switching indication feedback signal that Double Data Rate controller 7 sends, and confirms that the storer of Double Data Rate controller 7 controls is in the self-refresh state.Like this, system controller 5 control clock switch units 63 switch to the clock frequency of CPU the target clock frequency of the CPU of dominant frequency phaselocked loop 61 outputs from the clock frequency of outer frequency phase locked loop 62 outputs.
And, said system controller 5 control clock switch units 63 with the clock frequency of CPU after the clock frequency of outer frequency phase locked loop 62 outputs switches to the target clock frequency of CPU of dominant frequency phaselocked loop 61 outputs, system controller 5 is to Double Data Rate controller 7 tranmitting data register handoff completion signals, and indication Double Data Rate controller control store withdraws from the self-refresh state;
Double Data Rate controller 7 receives the clock handoff completion signal that system controller 5 sends, the time sequence parameter that Double Data Rate controller 7 will back up 71 storages of time sequence parameter register is written in the time sequence parameter register 72, latency delays locked loop 76 is stable, after delay-locked loop 76 was stablized, storer withdrawed from the self-refresh state;
Double Data Rate controller 7 switches to system controller 5 tranmitting data registers finishes feedback signal, the storer of feedback Double Data Rate controller control has withdrawed from the self-refresh state, Double Data Rate controller 7 is drawn high bus, and Double Data Rate controller 7 is resumed work under the target clock frequency of the CPU of dominant frequency phaselocked loop 61 outputs;
System controller 5 receives the clock switching of Double Data Rate controller 7 transmissions and finishes feedback signal, and system controller 5 confirms that storeies have withdrawed from the self-refresh state, and Double Data Rate controller 7 is worked under the clock frequency after the switching.
With a preferred implementation, come the system of dynamic adjustments cpu clock frequency is elaborated below:
1, the clock frequency of Double Data Rate controller 7 and central processing unit 8 (CPU) is the synchronous clock frequency;
2, the output frequency of the outer frequency phase locked loop 62 of central processing unit 8 bases deposits the time sequence parameter of correspondence in the backup time sequence parameter register 71 of Double Data Rate controller 7 in;
3, the signal transmitting unit 52 of system controller 5 is 1 to Double Data Rate controller 7 tranmitting data register switching signal mddrc_clksw_req, and the storer of indication Double Data Rate controller control enters the self-refresh state;
4, the signal receiving unit 75 of Double Data Rate controller 7 receives that the clock switching signal mddrc_clksw_req that system controller 5 sends is at 1 o'clock, Double Data Rate controller 7 is handled current multichannel read-write requests, in case current bus request disposes, promptly drag down bus READY signal (putting 0) and do not carry out read-write operation, Double Data Rate controller 7 control stores enter the self-refresh state;
5, the signal transmitting unit 74 of Double Data Rate controller 7 sends clock to system controller 5 to switch feedback signal mddrc_clksw_ack is 1 o'clock, and the storer of feedback Double Data Rate controller control has entered the self-refresh state;
6, to switch feedback signal mddrc_clksw_ack be 1 o'clock to the signal receiving unit 53 of system controller 5 clock that receives Double Data Rate controller 7, and system controller 5 control clock switch units 63 switch to the clock frequency that outer frequency phase locked loop 62 is exported with the clock frequency of dominant frequency phaselocked loop 61 outputs;
7, the signal transmitting unit 52 of system controller 5 is 0 to Double Data Rate controller 7 tranmitting data register switching signal mddrc_clksw_req, and the storer of indication Double Data Rate controller control withdraws from the self-refresh state;
8, Double Data Rate controller 7 signal receiving units 75 receive that the clock switching signal mddrc_clksw_req that system controller 5 sends is at 0 o'clock, Double Data Rate controller 7 is written into the time sequence parameter of backup time sequence parameter register 71 storages in the time sequence parameter register 72 and this time sequence parameter is disposed to delay-locked loop 76, and delay-locked loop 76 control stores withdraw from the self-refresh state;
9, the signal transmitting unit 74 of Double Data Rate controller 7 is 0 o'clock to system controller 5 tranmitting data registers switching feedback signal mddrc_clksw_ack, the storer of expression Double Data Rate controller control has withdrawed from the self-refresh state, Double Data Rate controller 7 is drawn high bus READY signal (putting 1), and Double Data Rate controller 7 is resumed work under the target clock frequency of the CPU of dominant frequency phaselocked loop 61 outputs;
10, to switch feedback signal mddrc_clksw_ack be 0 o'clock to the signal receiving unit 53 of system controller 5 clock that receives Double Data Rate controller 7, system controller 5 confirms that storer has withdrawed from the self-refresh state, and central processing unit 8 inquiry system controllers 5 states know that Double Data Rate controller 7 has been operated under the clock frequency of outer frequency phase locked loop 62 outputs;
11, the clock frequency of regulating 61 outputs of dominant frequency phaselocked loop by the target frequency parameter system controller 5 that disposes CPU is the target clock frequency of CPU, in " stand-by period " of the target clock frequency of waiting for the CPU that 61 outputs of dominant frequency phaselocked loop are stable, work under the clock frequency of Double Data Rate controller 7 and central processing unit 8 frequency phase locked loop 62 outputs outside earlier, after waiting for the target clock frequency stabilization of the CPU that dominant frequency phaselocked loop 61 is exported, refer again to the described flow process of above-mentioned 1-10 the clock frequency of outer frequency phase locked loop 62 outputs is switched to the target clock frequency of the CPU of dominant frequency phaselocked loop 61 stable outputs, realized that promptly cpu clock frequency is adjusted to the target clock frequency of CPU.
In sum, the method for present embodiment dynamic adjustments cpu clock frequency, the power consumption that guarantees to regulate the operate as normal of Double Data Rate controller in the cpu clock frequency process and reduce system.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (10)
1, a kind of method of regulating cpu clock frequency is characterized in that, comprising:
When the storer of Double Data Rate controller control is in the self-refresh state, the clock frequency of CPU is switched to the clock frequency of outer frequency phase locked loop output from the clock frequency of dominant frequency phaselocked loop output, make described Double Data Rate controller and CPU be operated in the clock frequency that described outer frequency phase locked loop is exported;
Obtain the target frequency parameter of CPU, the clock frequency of exporting according to the described dominant frequency phaselocked loop of the target frequency parameter regulation of described CPU is the target clock frequency of CPU;
When the storer of Double Data Rate controller control is in the self-refresh state, the clock frequency of the clock frequency of CPU frequency phase locked loop output outside described is switched to the target clock frequency of the CPU of described dominant frequency phaselocked loop output, make described Double Data Rate controller and CPU be operated in the target cpu clock frequency of dominant frequency phaselocked loop output.
2, the method for adjusting cpu clock frequency according to claim 1 is characterized in that, the step that is in the self-refresh state at the storer of Double Data Rate controller control comprises:
Switch indicator signal to described Double Data Rate controller tranmitting data register, indicate the storer of described Double Data Rate controller control to enter the self-refresh state;
Described Double Data Rate controller receives clock and switches indicator signal, and described Double Data Rate controller drags down bus and do not work, and controls described storer and enter the self-refresh state;
Described Double Data Rate controller tranmitting data register switches the indication feedback signal, indicates the storer of described Double Data Rate controller control to enter the self-refresh state;
The clock that receives described Double Data Rate controller feedback switches the indication feedback signal, confirms that the storer of Double Data Rate controller control is in the self-refresh state.
3, the method for adjusting cpu clock frequency according to claim 1, it is characterized in that, when the storer of Double Data Rate controller control is in the self-refresh state, with the clock frequency of CPU before the clock frequency of dominant frequency phaselocked loop output switches to the clock frequency that outer frequency phase locked loop exports, described CPU is according to the output clock frequency of described outer frequency phase locked loop, and the time sequence parameter of correspondence is deposited in the backup time sequence parameter register of described Double Data Rate controller.
4, the method for adjusting cpu clock frequency according to claim 1, it is characterized in that, when the storer of Double Data Rate controller control is in the self-refresh state, the clock frequency of the clock frequency of CPU frequency phase locked loop output outside described is switched to before the target clock frequency of CPU of described dominant frequency phaselocked loop output, described CPU is according to the target clock frequency of the CPU of described dominant frequency phaselocked loop output, and the time sequence parameter of correspondence is deposited in the backup time sequence parameter register of Double Data Rate controller.
5, the method for adjusting cpu clock frequency according to claim 3 is characterized in that, with the clock frequency of CPU after the clock frequency of dominant frequency phaselocked loop output switches to the clock frequency that outer frequency phase locked loop exports:
To described Double Data Rate controller tranmitting data register handoff completion signal, indicate described Double Data Rate controller control store to withdraw from the self-refresh state;
Described Double Data Rate controller receives the clock handoff completion signal, described Double Data Rate controller is written into the time sequence parameter of its backup time sequence parameter register-stored in its time sequence parameter register, the latency delays locked loop is stable, after described delay-locked loop was stable, described storer withdrawed from the self-refresh state;
Described Double Data Rate controller tranmitting data register switches finishes feedback signal, the storer that feeds back described Double Data Rate controller control has withdrawed from the self-refresh state, described Double Data Rate controller is drawn high bus, resumes work under the clock frequency of described Double Data Rate controller frequency phase locked loop output outside described;
The clock that receives described Double Data Rate controller transmission switches finishes feedback signal, confirms that described storer has withdrawed from the self-refresh state.
6, the method for adjusting cpu clock frequency according to claim 4 is characterized in that, the clock frequency of the clock frequency of CPU frequency phase locked loop output outside described is switched to after the target clock frequency of CPU of described dominant frequency phaselocked loop output:
To described Double Data Rate controller tranmitting data register handoff completion signal, indicate described Double Data Rate controller control store to withdraw from the self-refresh state;
Described Double Data Rate controller receives the clock handoff completion signal of transmission, described Double Data Rate controller is written into the time sequence parameter of its backup time sequence parameter register-stored in its time sequence parameter register, the latency delays locked loop is stable, after described delay-locked loop was stable, described storer withdrawed from the self-refresh state;
Described Double Data Rate controller tranmitting data register switches finishes feedback signal, the storer that feeds back described Double Data Rate controller control has withdrawed from the self-refresh state, described Double Data Rate controller is drawn high bus, resumes work under the target cpu clock frequency of described Double Data Rate controller frequency phase locked loop output outside described master;
The clock that receives described Double Data Rate controller transmission switches finishes feedback signal, confirms that described storer has withdrawed from the self-refresh state.
7, a kind of system that regulates cpu clock frequency is characterized in that, comprising: system controller and clock generation unit,
Wherein, described clock generation unit comprises dominant frequency phaselocked loop, outer frequency phase locked loop and clock switch unit;
Described system controller, after the storer that is used for determining the control of Double Data Rate controller is in the self-refresh state, control described clock switch unit and carry out the clock switching, described clock switch unit switches to the clock frequency of described outer frequency phase locked loop output with the clock frequency of CPU from the clock frequency of described dominant frequency phaselocked loop output, thereby makes Double Data Rate controller and CPU be operated in the clock frequency that described outer frequency phase locked loop is exported;
Described system controller obtains the target clock frequency parameter of CPU, and the clock frequency of exporting according to the described dominant frequency phaselocked loop of the target frequency parameter regulation of described CPU is the target clock frequency of CPU;
Described system controller, after the storer of determining Double Data Rate controller control is in the self-refresh state, control described clock switch unit and carry out the clock switching, described clock switch unit switches to the target clock frequency of the CPU of described dominant frequency phaselocked loop output with the clock frequency of clock frequency frequency phase locked loop output outside described of CPU, thereby makes described Double Data Rate controller and CPU be operated in the target cpu clock frequency of described dominant frequency phaselocked loop output.
8, the system of adjusting cpu clock frequency according to claim 7 is characterized in that, described Double Data Rate controller comprises:
Backup time sequence parameter register, be used for described system controller and confirm that the storer of Double Data Rate controller control is in the self-refresh state, control described clock switch unit and carry out before the clock switching, the time sequence parameter of the time sequence parameter of the output clock frequency correspondence of the described outer frequency phase locked loop of storage and the output target cpu clock frequency correspondence of described dominant frequency phaselocked loop;
The time sequence parameter register is used for after the clock frequency switching of described CPU, and described Double Data Rate controller control store withdraws from before the self-refresh state, is written into the time sequence parameter of described backup time sequence parameter register-stored.
9, the system of adjusting cpu clock frequency according to claim 7 is characterized in that, described system controller also comprises:
The signal generation unit, be used to generate the clock switching signal, described clock switching signal comprises: the clock that is used to indicate described Double Data Rate controller to enter the self-refresh state switches indicator signal and is used to indicate described Double Data Rate controller to withdraw from the clock handoff completion signal of self-refresh state;
Signal transmitting unit is used for to described Double Data Rate controller tranmitting data register switching signal;
Signal receiving unit, be used to receive the clock that described Double Data Rate controller sends and switch feedback signal, described clock switches feedback signal and comprises that being used to feed back clock that described Double Data Rate controller entered the self-refresh state switches the indication feedback signal and be used to feed back clock that described Double Data Rate controller withdrawed from the self-refresh state and switch and finish feedback signal.
According to the system of claim 7 or 8 described adjusting cpu clock frequencies, it is characterized in that 10, described Double Data Rate controller also comprises:
The signal generation unit, be used to generate clock and switch feedback signal, described clock switches feedback signal and comprises: be used to feed back clock that described Double Data Rate controller entered the self-refresh state and switch the indication feedback signal and be used to feed back clock that described Double Data Rate controller withdrawed from the self-refresh state and switch and finish feedback signal;
Signal transmitting unit is used for switching feedback signal to described system controller tranmitting data register;
Signal receiving unit, be used to receive the clock switching signal that described system controller sends, described clock switching signal comprises that the clock that is used to indicate described Double Data Rate controller to enter the self-refresh state switches indicator signal and is used to indicate described Double Data Rate controller to withdraw from clock handoff completion signal behind the self-refresh state.
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