CN101995894B - Self-adaption voltage regulator based on optimized PSM modulation mode - Google Patents

Abstract

The invention relates to a self-adaption voltage regulator based on an optimized PSM modulation mode, belonging to the technical field of power electronics and being used for self-adaption on-line regulation on a power supply voltage of a load processor (CPU or DSP). In the self-adaption voltage regulator, a key path of the load processor is copied by adopting a delay line, an N frequency division signal of a working clock of the load processor is used as a delay test signal, and a trigger is used for detecting whether the transmission speed of the delay test signal reaches the requirement in the delay line. When the load processor is in a certain working frequency, if the VDD (Voltage Drain Drain) is overhigh, the delay test signal can pass through the delay line, a power switch of an external power inverter is trially shut off for reducing the VDD; and when the delay test signal can not pass through the delay line, optimized PSM modulation signals with different duty ratios are trially adopted for conducting the power switch of the external power inverter for improving the VDD, and finally, the load processor is ensured to work with minimum voltage under a given working clock frequency, thus the power consumption of the load processor is effectively reduced.

Description

A kind of based on the adaptive electro voltage regulator of optimizing the PSM modulating mode

Technical field

The invention belongs to electric and electronic technical field, be used for the online adjusting of self-adaptation of the supply voltage with digital control function of object oriented processor (CPU or DSP) load.

Background technology

In recent years, along with the raising of integrated circuit integrated level, the power density of integrated circuit is increasing, and present power consumption of processing unit can reach more than 100 watt, and the heating radiator volume is huge and cost an arm and a leg.Simultaneously, the speed of development of battery technology lags far behind the demand of integrated circuit to electric energy, and this has become the key factor of restriction integrated circuit development.

A lot of complicated electronic parts like central processing unit (CPU) and digital signal processor (DSP), can both be worked under different clock frequencies.In the digital circuit of high-frequency work, the switch power consumption of gate circuit is the chief component of power consumption, and the switch power consumption is directly proportional with frequency of operation, with square being directly proportional of WV.For given task, the clock period number that CPU or DSP finish the work required confirms, only reduces the frequency of operation of CPU or DSP and do not change its WV, and the gross energy of accomplishing this task consumption is constant.And fixedly the time, suitably reducing the supply voltage of CPU or DSP in frequency of operation, the energy of its consumption will obviously reduce.According to different processes deviation, temperature and loaded work piece frequency self-adaptation regulating load in real time supply voltage, make its minimize energy consumption, this low-power consumption method is called adaptive voltage and regulates (AVS, Adaptive Voltage Scaling).

Existing adaptive voltage control method mainly contains following several kinds.1) people such as Mukti Barai utilizes ADC, DPID, DPWM to constitute control loop to make self-adaptation DC-DC transducer and (see document " Dual-Mode Multiple-Band Digital Controller for High-Frepuency DC-DC Converter "; Power Electronics; IEEE Transactions on Volume 24; Issue 3, March 2009 Page (s): 752-766), (modeling of needs process is compensated parameter and digital loop compensates usually but this method needs the digital loop compensation; And the parameter of modeling gained can not be very accurate, will inevitably cause compensation loop to produce oscillatory occurences more or less like this; And finally cause the output voltage unstable); 2) people such as Shidhartha Das comes regulation voltage according to the operation error rate of load circuit in the voltage-regulation process (CPU or DSP); Correct a mistake with error correction schemes simultaneously and realize that adaptive voltage is regulated and (see document " Razor II:In Situ Error Detection and Correction for PVT and SER Tolerance "; Solid-State Circuits; IEEE Journal of Volume 44, Issue 1, Jan.2009Page (s): 32-48); But this method realizes complicated, and system's error correction expends time in.3) people such as Dae Woon Kang has designed the digital self-adaptation Buck power converter that does not need PID (ratio, integration and differential) compensation based on finite state machine and (has seen document " A High-Efficiency Fully Digital Synchronous Buck Converter Power Delivery System Based on a Finite-State Machine "; Very Large Scale Integration (VLSI) Systems; IEEE Transactions on Volume 14; Issue 3; March 2006 Page (s): 229-240), but its circuit realization is more complicated than the method for the invention.

PSM (Pulse Skip Modulation) is a kind of new type of modulation pattern of power conversion system, regulates output voltage through skipping certain clock period, and when output voltage was higher than setting value, the power tube control signal was skipped, not conducting power tube; When output voltage was lower than setting value, the power tube control signal had pulse signal conducting power tube.Advantages such as the PSM controller has efficient height under the underload, strong robustness, response speed is fast, antijamming capability is strong, the electromagnetic compatibility characteristic is good.

Summary of the invention

It is a kind of based on the adaptive electro voltage regulator of optimizing the PSM modulating mode that the present invention provides; This adaptive electro voltage regulator can be according to the difference of the load processor work at present clock frequency WV of regulating load processor adaptively; Proof load processor WV under given working clock frequency is minimum, thereby reduces the power consumption of load processor effectively.Advantages such as simultaneously, the adaptive electro voltage regulator of employing PSM modulating mode has efficient height under the underloading, strong robustness, response speed is fast, antijamming capability is strong, the electromagnetic compatibility characteristic is good.

Basic ideas of the present invention are: for processor is the large scale digital circuit of representative, when wherein critical path (in the load processor the longest operating path) when postponing less than a clock period, and can operate as normal.And critical path delay and its WV are inversely proportional to, and make the processor cisco unity malfunction thereby low excessively WV will increase the delay of critical path.Adopt lag line to duplicate the critical path of load processor, the Fractional-N frequency signal that adopts the load processor work clock detects delayed test signal transmission speed in lag line with trigger and whether reaches requirement as delayed test signal.When load processor under certain frequency of operation, if WV V _DDToo high; Delayed test signal can pass through lag line, and the power switch pipe of then managing to turn-off the power switch pipe of external power transducer or adopting a gate control signal conducting external power transducer of being realized by state machine with less dutycycle is to reduce WV; When delayed test signal can not pass through lag line; Then adopt one by having of realizing of state machine than the power switch pipe of the gate control signal conducting external power transducer of big space rate to improve WV; Final realization proof load processor WV under given working clock frequency is minimum, thereby reduces the power consumption of load processor effectively.

Detailed technology scheme of the present invention is:

A kind of based on the adaptive electro voltage regulator of optimizing the PSM modulating mode, as shown in Figure 1, comprise a clock signal generator CLKG, one section lag line, two trigger D0 and D1, a state machine and a digital pwm signal generation circuit.External clock source provides reference clock signal CLK_REF for clock signal generator CLKG; Clock signal generator CLKG produces three clock signals according to the control signal CLKG_Ctrl of the frequency of operation of external loading processor request: load processor clock signal clk _ CPU, lag line reset signal RST and delayed test signal TCLK; Said lag line reset signal RST and delayed test signal TCLK are the Fractional-N frequency signal of load processor clock signal clk _ CPU; N is the integer more than or equal to 2, and lag line reset signal RST rising edge is than the clock period of the load processor clock signal clk _ CPU of rising edge hysteresis of delayed test signal TCLK; Wherein, lag line reset signal RST is input to the edge trigger end of lag line reset terminal, trigger D0 and the edge trigger end of trigger D1 simultaneously; Delayed test signal TCLK is input to the delay test end of lag line; Load processor clock signal clk _ CPU is input to the clock signal input terminal of load processor.The output voltage V of external power transducer _DDBe the power supply of external loading processor and lag line simultaneously; The output signal OX of lag line is divided into two-way: the one tunnel is input to the data input pin of trigger D1, and another road is input to the data input pin of trigger D0 after through a delay cell; The inhibit signal E1 that inhibit signal E0 that trigger D0 latchs and trigger D1 latch is input to state machine respectively, and state machine produces the digital signal d of a M position _M-1d _M-2D ₁d ₀And being input to the digital PWM signal generating circuit, the pwm signal that the digital PWM signal generating circuit produces different duty is used for controlling the conducting of external power transducer main switch or ending.

In the such scheme, said delay line length surpasses external loading processor critical path depth L, and overage Δ L is length nargin (Δ L be external loading processor critical path depth L 5%～25%).

Of the present invention based on the adaptive electro voltage regulator of optimizing the PSM modulating mode, have the following advantages:

1, efficient adopts the adaptive electro voltage regulator of PWM modulating mode high when underload.

When power converter was in underload or holding state, because load upper reaches excess current is less, the power switch pipe conduction loss can be ignored, and switching loss becomes the main power consumption source of system.During underloading, optimizing the PSM modulating mode (is D through skipping the clock period ₀=0), the switch number of times of power tube is reduced, thereby reduce switching loss, reached the purpose that improves power conversion efficiency.

2, loop does not need compensation, and circuit structure is simple, is easy to realize.

Traditional adaptive electro voltage regulator adopts the PWM modulating mode, needs to confirm compensating parameter through complicated loop modeling; One of biggest advantage of using optimization PSM modulating mode is exactly not need loop compensation.Simultaneously, can be found out by Fig. 1 that the adaptive voltage controller structure that the present invention proposes is extremely simple, circuit is realized convenient.And can digitally realize that it is integrated to be easy to small size technology.

3, output voltage ripple is less.

Adopt and optimize the PSM modulating mode, at maximum available duty cycle D ₂With minimum duty cycle D ₀Between insert transition dutycycle D ₁, output voltage ripple is littler.

Shown in Figure 1 can realize with the standard block in the digital Design based on the adaptive electro voltage regulator of optimizing the PSM modulating mode fully, can be integrated under littler process, be easy to the transplanting and the modification of circuit, and complied with the integrated circuit Development Trend.

The present invention is particularly suitable for the power management chip of portable product.With the clock signal of CPU input signal as this circuit, the adaptive electro voltage regulator automatically with the CPU voltage-regulation to the minimum that guarantees the circuit operate as normal, can effectively lower the energy consumption of CPU.

Description of drawings

Fig. 1 is provided by the invention based on the adaptive voltage adjuster circuit structural representation of optimizing the PSM modulating mode.

Fig. 2 is the circuit structure diagram based on lag line in the adaptive electro voltage regulator of optimizing the PSM modulating mode provided by the invention.

Fig. 3 is provided by the invention based on state machine duty conversion synoptic diagram in the adaptive electro voltage regulator of optimizing the PSM modulating mode.

Fig. 4 is the sequential chart based on the adaptive electro voltage regulator operate as normal of optimizing the PSM modulating mode provided by the invention.

Specific embodiments

A kind of based on the adaptive electro voltage regulator of optimizing the PSM modulating mode, as shown in Figure 1, comprise a clock signal generator CLKG, one section lag line, two trigger D0 and D1, a state machine and a digital pwm signal generation circuit.External clock source provides reference clock signal CLK_REF for clock signal generator CLKG; Clock signal generator CLKG produces three clock signals according to the control signal CLKG_Ctrl of the frequency of operation of external loading processor request: load processor clock signal clk _ CPU, lag line reset signal RST and delayed test signal TCLK; Said lag line reset signal RST and delayed test signal TCLK are the Fractional-N frequency signal of load processor clock signal clk _ CPU; N is the integer more than or equal to 2, and lag line reset signal RST rising edge is than the clock period of the load processor clock signal clk _ CPU of rising edge hysteresis of delayed test signal TCLK; Wherein, lag line reset signal RST is input to the edge trigger end of lag line reset terminal, trigger D0 and the edge trigger end of trigger D1 simultaneously; Delayed test signal TCLK is input to the delay test end of lag line; Load processor clock signal clk _ CPU is input to the clock signal input terminal of load processor.The output voltage V of external power transducer _DDBe the power supply of external loading processor and lag line simultaneously; The output signal OX of lag line is divided into two-way: the one tunnel is input to the data input pin of trigger D1, and another road is input to the data input pin of trigger D0 after through a delay cell; The inhibit signal E1 that inhibit signal E0 that trigger D0 latchs and trigger D1 latch is input to state machine respectively, and state machine produces the digital signal d of a M position _M-1d _M-2D ₁d ₀And being input to the digital PWM signal generating circuit, the pwm signal that the digital PWM signal generating circuit produces different duty is used for controlling the conducting of external power transducer main switch or ending.

In the such scheme, said delay line length surpasses external loading processor critical path depth L, and overage Δ L is length nargin (Δ L be external loading processor critical path depth L 5%～25%).

Below in conjunction with accompanying drawing the present invention is further specified.

Provided by the invention its external loading processor can be CPU, DSP or other digital processing unit based on the adaptive electro voltage regulator of optimizing the PSM modulating mode, and power converter can be the power converter of Boost, Buck or other topological structure.Below be that CPU, power converter are that the power converter of Buck topological structure is that example is explained the course of work of the present invention with the load processor.

The output terminal V of Buck power converter _DDSupply power for CPU and lag line simultaneously; External clock source provides reference clock signal CLK_REF for clock signal generator CLKG; Clock signal generator CLKG produces three clock signals according to the control signal CLKG_Ctrl of the frequency of operation of external loading processor request: load processor clock signal clk _ CPU, lag line reset signal RST and delayed test signal TCLK; Said lag line reset signal RST and delayed test signal TCLK are the Fractional-N frequency signal of load processor clock signal clk _ CPU; N is the integer more than or equal to 2, and lag line reset signal RST rising edge is than the clock period of the load processor clock signal clk _ CPU of rising edge hysteresis of delayed test signal TCLK.Judge according to the transmission situation of delayed test signal TCLK in lag line whether the output voltage of power converter can make the critical path operate as normal of CPU; And regulate the output voltage of power converter according to the result who detects; Guarantee CPU ability operate as normal when the needs Processing tasks, reduce load C PU energy consumption to greatest extent through reducing its supply voltage simultaneously.

If load processor clock signal clk _ cpu frequency is f, the cycle is T _S=1/f works as V _DDWhen higher, test signal TCLK will be at a clock period T _SIn be transferred to the data input pin of two triggers, CPU can operate as normal; Otherwise, work as V _DDWhen low, test signal TCLK is at a clock period T _SThe interior data input pin that can not be transferred to two triggers, then CPU cisco unity malfunction; When at a clock period T _SWhen interior TCLK just was transferred to the data input pin of two triggers, the critical path delay among the CPU was T _SL/ (L+ Δ L) doubly, then this moment CPU supply voltage V _DDGuarantee to leave under the prerequisite of certain nargin minimum.

Under the control of adaptive electro voltage regulator, the Buck power converter is that cpu load provides power supply, and delayed test signal TCLK is that the Fractional-N frequency clock of load processor clock signal clk _ CPU is (every through N clock period T _SCarry out the time lag of first order test, establish N=2 in the following narration process); Lag line reset signal RST is identical with delayed test signal TCLK frequency, but lag line reset signal RST rising edge is than the clock period of the load processor clock signal clk _ CPU of rising edge hysteresis of delayed test signal TCLK.The concrete sequential of system's course of normal operation was as shown in Figure 4 after voltage and frequency adjustment were accomplished.

Work as V _DDCross (this moment, lag line was in under-voltage condition) when hanging down, at a clock period T _SIn, the high level of delayed test signal TCLK can not be transferred to the output terminal of lag line, and lag line output this moment signal OX is a low level, and lag line output signal OX also is a low level through the signal OY after the delay cell.Because lag line reset signal RST is than clock period T of delayed test signal TCLK hysteresis _S, when the RST rising edge occurred, trigger D1 exported signal OY with lag line and latchs, and trigger D0 exports signal OY with delay cell and latchs.The signal E1 of the signal E0 of trigger D0 output and trigger D1 output is low level signal, i.e. { E ₁, E ₀}=00 is if the state machine current state is S _i(i=0 or 1), then the state machine NextState is S _I+1It is D that (i=0 or 1) and digital PWM signal generating circuit produce dutycycle _I+1The signal of (i=0 or 1); If the state machine current state is S ₂, then the state machine NextState still is S ₂, power tube conducting dutycycle is constant.Output voltage V _DDBegin to rise, because transition dutycycle D ₁Existence, make output voltage ripple littler.

Work as V _DDWhen too high (this moment, lag line was in overvoltage condition), at a clock period T _SIn, the high level of delayed test signal TCLK can be transferred to the output terminal of lag line, and lag line output this moment signal OX is a high level, and lag line output signal OX also is a low level through the signal OY after the delay cell.Because lag line reset signal RST is than clock period T of delayed test signal TCLK hysteresis _S, when the RST rising edge occurred, trigger D1 exported signal OY with lag line and latchs, and trigger D0 exports signal OY with delay cell and latchs.The signal E1 of the signal E0 of trigger D0 output and trigger D1 output is high level signal, i.e. { E ₁, E ₀}=11 are if the state machine current state is S _i(i=1 or 2), then the state machine NextState is S _I-1It is D that (i=1 or 2) and digital PWM signal generating circuit produce dutycycle _I-1The signal of (i=1 or 2); If the state machine current state is S ₀, then the state machine NextState still is S ₀, power tube conducting dutycycle is constant.Output voltage V _DDBegin to descend, because transition dutycycle D ₁Existence, make output voltage ripple littler.When OX is high level, if OY is low, i.e. { E ₁, E ₀}=10 explain that then output voltage is not high not low yet, if this moment, the state machine current state was S _i(i=0,1 or 2), then the state machine NextState still is S _i(i=0,1 or 2) are constant.

Above-mentioned makes when critical path delay is excessive among the CPU based on the adaptive electro voltage regulator of optimizing the PSM modulating mode, thereby clock period of conducting is improved V _DDVoltage reduces critical path delay; When critical path delay is too small among the CPU, thereby skipping a clock period makes V _DDVoltage reduces, and reduces the energy consumption of CPU.The length of lag line is decided to be L+ Δ L, make the CPU critical path delayed adaptation be adjusted to T _SL/ (L+ Δ L) doubly, guaranteeing that retardation leaves under the situation of certain nargin V _DDBe adjusted to minimumly, reduce the energy consumption of load C PU to greatest extent.Suppose that its output voltage ripple is Δ V behind the power converter output voltage stabilization, the existence of voltage ripple Δ V can not influence the operate as normal of CPU.The critical delay time of load C PU is T _SL/ (L+ Δ L) doubly, the desirable L/ of representative value (L+ Δ L) is 80%, this moment Δ L length be L 25% (Δ L is too small, receives the influence of the ripple of process deviation or output voltage, and the output voltage of power converter may not the proof load operate as normal; Δ L is excessive, can cause under given frequency of operation, and load voltage is too high, can not save energy to greatest extent).

Sequential chart when Fig. 4 is system's operate as normal, CLK_CPU, TCLK, RST are three clock signals that produced by CLKG.Wherein TCLK and RST are Fractional-N frequency (N clock period T of every process of CLK_CPU _SCarry out the time lag of first order test), N=2 in Fig. 2.RST is than T of TCLK hysteresis _SClock period.

Lag line is that two parts of L and Δ L constitute by length, and as shown in Figure 4, every part is all formed by the rejection gate cascade that has an inverting input.Length is that the part of L is duplicating of CPU critical path, and length is that the part of Δ L is the nargin of delay line length.

If use V _INThe input voltage of expression Buck power converter, V _DDThe expression output voltage, D representes open pipe (conducting) dutycycle of power tube, L representes energy storage inductor value, T _PThe clock period of expression CLK_Power, D _MAXThe expression power converter works in maximum duty cycle available under the DCM pattern.If further require power converter to be operated in the DCM pattern, then have

$\frac{\frac{V_{\mathrm{IN}}-V_{\mathrm{DD}}}{L}}{\frac{V_{\mathrm{DD}}}{L}}=\frac{(1-D)T_P}{D{\·T}_P}$

$D=\frac{V_{\mathrm{DD}}}{V_{\mathrm{IN}}}$

The input and output voltage of adaptive electro voltage regulator changes in a definite scope, guarantee all to be operated in the DCM pattern at whole input and output voltage range inner conversion device, requires the maximum duty cycle D2 that optimizes the PSM modulation signal to be:

$D2=D_{\mathrm{MAX}}=\frac{V_{D{D}_{\mathrm{MIN}}}}{V_{{\mathrm{IN}}_{\mathrm{MAX}}}}$

Wherein

The minimum value of expression external power transducer output voltage,

The maximal value of expression external power transducer input voltage; Minimum duty cycle D0 is zero; Middle dutycycle D1=D _MAX/ 2 or D1 be (0, D _MAX) between other value.

Provided by the invention based on the adaptive electro voltage regulator of optimizing the PSM modulating mode, can be whole with external loading processor and the integrated same chip of power converter in.This adaptive electro voltage regulator is applicable to various Switching Power Supplies topology, comprises circuit such as isolated, non-isolated, Boost, Buck, Buck-Boost, Flyback, Forward, Cuk.The basic delay cell of wherein said lag line also can be made up of rejection gate, also can be made up of other basic logical gate, also can combined to constitute by basic logical gate and electric capacity.

Claims (4)

1. one kind based on the adaptive electro voltage regulator of optimizing the PSM modulating mode, comprises a clock signal generator CLKG, one section lag line, two trigger D0 and D1, a state machine and a digital pwm signal generation circuit;

External clock source provides reference clock signal CLK_REF for clock signal generator CLKG; Clock signal generator CLKG produces three clock signals according to the control signal CLKG_Ctrl of the frequency of operation of external loading processor request: load processor clock signal clk _ CPU, lag line reset signal RST and delayed test signal TCLK; Said lag line reset signal RST and delayed test signal TCLK are the Fractional-N frequency signal of load processor clock signal clk _ CPU; N is the integer more than or equal to 2, and lag line reset signal RST rising edge is than the clock period of the load processor clock signal clk _ CPU of rising edge hysteresis of delayed test signal TCLK; Wherein, lag line reset signal RST is input to the edge trigger end of lag line reset terminal, trigger D0 and the edge trigger end of trigger D1 simultaneously; Delayed test signal TCLK is input to the delay test end of lag line; Load processor clock signal clk _ CPU is input to the clock signal input terminal of load processor;

The output voltage V of external power transducer _DDBe the power supply of external loading processor and lag line simultaneously; The output signal OX of lag line is divided into two-way: the one tunnel is input to the data input pin of trigger D1, and another road is input to the data input pin of trigger D0 after through a delay cell; The inhibit signal E1 that inhibit signal E0 that trigger D0 latchs and trigger D1 latch is input to state machine respectively, and state machine produces the digital signal d of a M position _M-1d _M-2D ₁d ₀And being input to the digital PWM signal generating circuit, the pwm signal that the digital PWM signal generating circuit produces different duty is used for controlling the conducting of external power transducer main switch or ending.

2. according to claim 1 a kind of based on the adaptive electro voltage regulator of optimizing the PSM modulating mode, it is characterized in that the length nargin Δ L of said lag line is 5%～30% of external loading processor critical path depth L.

3. according to claim 1 and 2 a kind of based on the adaptive electro voltage regulator of optimizing the PSM modulating mode, it is characterized in that said lag line is formed by the rejection gate cascade with an inverting input.

4. a kind of adaptive electro voltage regulator based on the PSM modulating mode according to claim 1 and 2 is characterized in that, the maximum duty cycle D2 of the optimization PSM modulation signal that said digital PWM signal generating circuit produces is:

$D2=D_{\mathrm{MAX}}=\frac{V_{{\mathrm{DD}}_{\mathrm{MIN}}}}{V_{{\mathrm{IN}}_{\mathrm{MAX}}}}$

Wherein

The minimum value of expression external power transducer output voltage,

The maximal value of expression external power transducer input voltage; Minimum duty cycle D0 is zero; Middle dutycycle D1=D _MAX/ 2 or D1 be (0, D _MAX) between other value.

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