CN202135115U

CN202135115U - Stochastic time-digital converter

Info

Publication number: CN202135115U
Application number: CN201120240173U
Authority: CN
Inventors: 吴建辉; 王子轩; 张萌; 黄成�; 陈超; 黄福青; 吉新村; 江平
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2011-07-08
Filing date: 2011-07-08
Publication date: 2012-02-01
Anticipated expiration: 2021-07-08

Abstract

The utility model discloses a stochastic time-digital converter (STDC), which comprises an input switching circuit, an STDC array and an encoder, wherein a clock circuit inputs two clock signals into the two input ends of the input switching circuit respectively, the input switching circuit transmits the two clock signals input by the clock circuit to the two input ends of the STDC array via an intersection transposition form and outputs a trigger control signal to the encoder at the same time, each comparator in the STDC array carries out determination to the speed of the two clock signals independently and transmits a determination result to the encoder for summarizing processing, and the encoder outputs the value and sign of the phase difference of the two clock signals. The stochastic time-digital converter employs the stochastic characteristic of the STDC, thereby doubling equivalent comparators in the STDC array, eliminating influences of part mismatch, technology, power supply voltage, and temperature on the circuit to a maximum extent, and has the characteristics of hardware saving, low power dissipation, and small area compared with a conventional STDC circuit.

Description

A kind of random time-digital quantizer

Technical field

The utility model relates to a kind of random time-digital quantizer that contains input-switching circuit, belongs to integrated circuit converter technology field.

Background technology

TDC (Time-Digital Converter, time-digital quantizer) has a wide range of applications in integrated circuit, mainly is used for differentiating for digital phase-locked loop provides phase place.In addition, at nucleus medical image, lasers range is surveyed, and many application scenarios such as half-life of detecting particle in the high-energy physics all rely on TDC and differentiate that the small time (phase place) is poor.TDC adopts digital technology to realize, along with process dwindles gradually, has portable good advantage.In addition, digital TDC circuit has better noise immunological characteristic, and power consumption is also lower.Because TDC turns to numeral output with time (phase place) residual quantity, with respect to traditional phase frequency detector, is all to have improved greatly identification precision or locking time.

TDC is a kind of circuit that replaces discriminating time (phase place) difference of traditional phase discriminator.In digital phase-locked loop, the time difference that the digital control word of TDC output has reflected two input signal rising edges, and directly driving oscillator is adjusted frequency, therefore very high for the evaluation required precision of TDC.First kind of common structural is delay line TDC; The inverter series connection very little through a string delay constitutes delay line; Let one of them input signal transmit through delay line, every through comparing with another input signal after the one-level delay, identify the time difference of two signal rising edges with this.The resolution of the TDC of this structure equals the time of delay of each grade delayer, and is therefore very serious for the dependence of technology, and deviation is very big simultaneously, and the further improvement of resolution also is restricted.

Another kind of implementation structure is random time-digital quantizer (STDC).When two signal phases were approaching, because the influence of PVT and the mismatch of device, the judgement of comparator can produce uncertainty.And the error agrees Gaussian distribution that causes by this uncertainty.Use the identical comparator of some to form array, gather their output and analyze, and then can obtain the information of signal phase difference.This structure can reach very meticulous resolution, and better to the tolerance of PVT.But because accessible resolution is directly related with the number of comparators of use, therefore, the improvement of resolution needs more number of comparators, and power consumption, area and hardware consumption all will inevitably increase.

Summary of the invention

The utility model technical problem to be solved is the defective to background technology, and a kind of use input automatic switchover technology is provided, and comprises the STDC of input-switching circuit.

The utility model adopts following technical scheme for solving the problems of the technologies described above:

A kind of random time-digital quantizer; Comprise STDC array and encoder; Also comprise input-switching circuit; Wherein clock circuit inputs to two inputs of input-switching circuit respectively with two clock signals, and input-switching circuit flows to two inputs of STDC array with two clock signals of clock circuit input with the form of coordinated transposition by turns, and output simultaneously triggers and controls signal to encoder; Each comparator is all independently judged the speed of two clock signals in the STDC array, and judged result is sent into the encoder aggregation process, the phase place extent of two clock signals of encoder output and positive and negative.

Further, the random time-digital quantizer of the utility model, said input-switching circuit comprise a d type flip flop, four and door and two or; Wherein,

First clock signal connect respectively d type flip flop clock end, second and the door and the 3rd with the door second input; The triggering signal output of d type flip flop connect respectively first with door, the 3rd with first input end and the first input end of encoder of door, the triggering signal of d type flip flop output through the D input that connects d type flip flop after the one-level anti-phase respectively, second with door and the 4th with first input end;

The second clock signal connect respectively first with the door with the 4th with second input;

First with the door with second with the door output termination first or the door input, the 3rd with the door with the 4th and output termination second or input; First or door, second or the output of door respectively as first output and second output of input-switching circuit.

Further, the random time-digital quantizer of the utility model, said STDC array is made up of 64 identical comparator unit, and said comparator unit adopts the structure of traditional differential comparator cascade RS latch.

Further, the random time-digital quantizer of the utility model, said encoder adopt 64 inputs-7 output coders.

The utility model adopts above technical scheme compared with prior art, has following technique effect:

The utility model has added input-switching circuit through the input at STDC; The rising edge of two input signals is realized alternately handover operation; And drive STDC, make two input signals alternately connect the input of comparator, thereby farthest abatement device mismatch and technology, supply voltage, temperature (PVT) are to the influence of circuit; And made full use of the stochastic behaviour of comparator, the equivalent number of comparators among the STDC is doubled.Reach at STDC under the condition of same resolution, the number of comparators of use reduces by half, thereby makes hardware consumption, power consumption, area all reach the purpose that reduces by half.

Description of drawings

Fig. 1 is the STDC main body circuit block diagram of the utility model.

Fig. 2 is the gate level circuit schematic diagram of the input-switching circuit of the utility model.

Fig. 3 is the behavior analogous diagram of the input-switching circuit of the utility model.

Fig. 4 is the STDC of the utility model and traditional STDC transmission characteristic comparison diagram; Wherein Fig. 4-a is traditional STDC transmission characteristic figure, and Fig. 4-b is the STDC transmission characteristic figure of the utility model.

Fig. 5 is the linear zone transmission characteristic figure of the STDC of the utility model; Wherein solid line is the actual transmission curve of STDC, and dotted line is desirable transmission curve.

Label among the figure: clk1: first clock signal, clk2: second clock signal, sw: triggering signal; Out1: first output of input-switching circuit, out2: second output of input-switching circuit, AND1: first with the door; AND2: second with the door, AND3: the 3rd with the door, AND4: the 4th with the door; OR1: first or the door, OR2: second or the door.

Embodiment

Below in conjunction with accompanying drawing the technical scheme of the utility model is done further detailed description:

As shown in Figure 1; This random time-digital quantizer comprises input-switching circuit, STDC array and three parts of encoder; Input-switching circuit is realized that by Digital Logical Circuits the STDC array is made up of 64 identical comparator unit, and encoder is the 64-7 encoder by the sw signal controlling.Two clock input signal clk1, clk2 receive the input of input-switching circuit; The output out1 of input-switching circuit, out2 connect the input of each comparator in the STDC array respectively; Output signal sw connects encoder as control signal, is the two divided-frequency signal by the trailing edge triggering of clk1.64 court verdicts that STDC produces connect encoder, and encoder produces 7bit output.

As shown in Figure 2, input-switching circuit realized by Digital Logical Circuits, comprises the d type flip flop that a trailing edge triggers, four with door, two or.The STDC array is made up of 64 identical comparator unit, and comparator unit adopts the structure of classical differential comparator cascade RS latch.

The d type flip flop that the main part of input-switching circuit is triggered by trailing edge, four with a door AND1, AND2, AND3, AND4, two or an OR1, OR2 form.Clk1 connects the clock end of d type flip flop, and output sw connects an input with door AND1 and AND3 respectively, and through the input D that connects d type flip flop after the one-level inverter, with the input of an AND2 and AND4.Clock signal clk1 connects another input with door AND2 and AND3, and clk2 connects another input with door AND1 and AND4.Connect with the output of door AND1 and AND2 or the input of door OR1, connect with the output of door AND3 and AND4 or the input of an OR2.The output of OR1 and OR2 is respectively as the output out2 and the out1 of whole input-switching circuit.

Fig. 3 is the behavior analogous diagram of the input-switching circuit of the utility model.As can be seen from the figure, when sw was 1, the rising edge of output out1 alignd with the rising edge of input clk1, and the rising edge of output out2 aligns with the rising edge of input clk2; And when sw was 0, the rising edge of output out1 alignd with the rising edge of input clk2, and the rising edge of output out2 aligns with the rising edge of input clk1, had realized alternately switching of input rising edge.

Fig. 4 is the STDC of the utility model and traditional STDC transmission characteristic comparison diagram; Wherein Fig. 4-a is traditional STDC transmission characteristic figure, and Fig. 4-b is the STDC transmission characteristic figure of the utility model.Can find out that from the contrast of Fig. 4-a and Fig. 4-b two kinds of circuit have identical effective evaluation scope; But for 8 * 8 comparator array, traditional STDC has only 6 outputs equally, and the STDC of the utility model can have 7 outputs.Under same hardware consumption condition, the STDC of the utility model obviously has higher precision.Equally, if realize the output accuracy of 7bit, the STDC of the utility model only needs 64 comparators, and traditional STDC needs 128 comparators.

Fig. 5 is the linear zone transmission characteristic figure of the STDC of the utility model; Wherein solid line is the actual transmission curve of STDC, and dotted line is desirable transmission curve.As can be seen from the figure, in linear zone, transmission characteristic is linear character basically.

In sum; The utility model is through input-switching circuit of cascade before STDC; Two input signals of circuit are flowed to two inputs of STDC with the form of coordinated transposition by turns; Each comparator is all independently judged the speed of two signals among the STDC, and the result is sent into the encoder aggregation process, and the output result of coding has just reflected two phase of input signals extents and positive and negative.

According to the operation principle of STDC, its raising of differentiating resolution need realize through the quantity that increases comparator, has so just inevitably increased the burden of power consumption and area.Before STDC after input-switching circuit of cascade, two input signal clk1 and clk2 can that is: go up one-period alternately by two output out1 and out2 output, and out1 exports clk1, and out2 exports clk2; Next cycle, out1 exports clk2, and out2 exports clk1.Through after such input hand-off process, the mismatch of device and PVT have been suppressed the influence of circuit to a great extent, have improved the discriminating precision.For every two adjacent cycles, non-ideal factor is all different fully to the interference that each comparator produces.From statistical angle, this way has equaled to increase a new independently sample.So the quantity of equivalent comparator is double among the STDC, when using half the number of comparators, the resolution of STDC does not reduce, but actual hardware consumption has significantly reduced.

The above is merely the preferred embodiments of the utility model; The protection range of the utility model does not exceed with above-mentioned execution mode; As long as the equivalence that those of ordinary skills do according to the utility model institute disclosure is modified or changed, all should include in the protection range of the utility model record.

Claims

1. random time-digital quantizer; Comprise STDC array and encoder; It is characterized in that: also comprise input-switching circuit; Wherein clock circuit inputs to two inputs of input-switching circuit respectively with two clock signals, and input-switching circuit flows to two inputs of STDC array with two clock signals of clock circuit input with the form of coordinated transposition by turns, and output simultaneously triggers and controls signal to encoder; Each comparator is all independently judged the speed of two clock signals in the STDC array, and judged result is sent into the encoder aggregation process, the phase place extent of two clock signals of encoder output and positive and negative.

2. a kind of random time-digital quantizer according to claim 1 is characterized in that: said input-switching circuit comprise a d type flip flop, four and door, two or, wherein,

3. a kind of random time-digital quantizer according to claim 1 is characterized in that: said STDC array is made up of 64 identical comparator unit, and said comparator unit adopts the structure of traditional differential comparator cascade RS latch.

4. a kind of random time-digital quantizer according to claim 1 is characterized in that: said encoder adopts 64 inputs-7 output coders.