CN201965746U - Remote control encoding circuit based on FPGA (Field Programmable Gate Array) - Google Patents
Remote control encoding circuit based on FPGA (Field Programmable Gate Array) Download PDFInfo
- Publication number
- CN201965746U CN201965746U CN2010206670288U CN201020667028U CN201965746U CN 201965746 U CN201965746 U CN 201965746U CN 2010206670288 U CN2010206670288 U CN 2010206670288U CN 201020667028 U CN201020667028 U CN 201020667028U CN 201965746 U CN201965746 U CN 201965746U
- Authority
- CN
- China
- Prior art keywords
- circuit
- input
- remote control
- fpga
- frequency dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The utility model discloses a remote control encoding circuit based on FPGA (Field Programmable Gate Array), which comprises an encoding input circuit combined by a plurality of press keys, a memory, an RC (remote control) oscillation circuit, a frequency division circuit, a synchronous circuit, a control circuit, a sampling circuit, an address parallel-serial conversion circuit, an encoding pulse generator and an output control circuit, wherein the output end of the RC oscillation circuit is connected with the frequency division circuit, the synchronous circuit, the control circuit and the memory respectively; the encoding input circuit is connected with the input end of the address parallel-serial conversion circuit through the memory; the output ends of the synchronous circuit and the control circuit are both connected with the input end of the control circuit; a path of the frequency division output end of the frequency division circuit is directly connected with the address parallel-serial conversion circuit, and the other path is connected with the address parallel-serial conversion circuit through the sampling circuit; two different serial output ends of the frequency division circuit are respectively connected with the two corresponding input ends of the encoding pulse generator; and the output end of the address parallel-serial conversion circuit is connected with the input end of the encoding pulse generator. With the adoption of the encoding circuit, a remote control command can be effectively and reliably transferred, so that air catching and scanning tracking are avoided, and intersymbol conflict among users is reduced.
Description
Technical field
The utility model belongs to the telecontrol engineering field, has to relate to a kind of remote control coding circuit based on FPGA.
Background technology
For telechirics, core devices wherein encode exactly input circuit and decoding circuit.The output of coding input circuit is used to produce different coded pulse signals, and coded pulse signal is used for representing different telecommands, and no matter the how many kinds of command content is arranged, and all sends from a port, and the coded signal that is to say telecommand is serial.Most of now telepilots all are to adopt fixing coded signal output, and the regular coding signal is based on the security system of one-way transmission, and limited protection can only be provided.Because the confidentiality of this system is to realize by the length that improves code, and the length of code is limited, thereby can only obtain limited code combination, and just be easy to obtain code with the aerial way of catching and scan tracking, so just used without authorization by the disabled user.Thereby brought potential safety hazard.In a single day this hidden danger originates from the setting of system's " address encoding and decoding " port, just can be discerned by " detector of encoding in the air " or " coded scanning device " easily so grasp this coding, and be usurped by others." detector of encoding in the air " includes a HF receiver, recorder analyser or micro computer, the channel that the operator only need be fit to the HF receiver modulation during use, in case there is signal to occur, just moment is obtained " identity code " of validated user.And " coded scanning device " is a kind of type equipment that makes an initiative sally, and during use, the scrambler under microcomputer that equipment contains or the sequential circuit control can be compiled out whole codings, and go out by radio transmission automatically successively, until till the response of former receiver.Because the address setting number of regular coding input circuit is limited, so scanner just can crack in the short time at the utmost point, this cracks the time generally can be above 2 hours.
Summary of the invention
Technical problem to be solved in the utility model provides a kind of remote control coding circuit based on FPGA, and this coding input circuit can make guidance command transmit effectively reliably, avoids aerial and catches and the scanning tracking, reduces the intersymbol conflict between each user.
For addressing the above problem, a kind of remote control coding circuit based on FPGA that the utility model is designed comprises the coding input circuit, storer, RC oscillatory circuit, frequency dividing circuit, synchronizing circuit, control circuit, sample circuit, address parallel-to-serial converter, coded pulse generator and the output control circuit that are formed by a plurality of key combination; Wherein the output terminal of RC oscillatory circuit connects frequency dividing circuit, synchronizing circuit, control circuit and storer respectively; The coding input circuit links to each other with the input end of address parallel-to-serial converter through storer; The output terminal of synchronizing circuit and control circuit all is connected with the input end of output control circuit; In the frequency division output terminal of frequency dividing circuit a road directly links to each other with the address parallel-to-serial converter, and another Lu Zejing sample circuit is connected with the address parallel-to-serial converter; 2 different serial output terminals of frequency dividing circuit are connected on 2 corresponding input ends of coded pulse generator; The output terminal of address parallel-to-serial converter links to each other with the input end of coded pulse generator.
The described memory built-in of such scheme has decoding scheme.
The described frequency dividing circuit of such scheme is the divide by four circuit that 2 d type flip flops constitute.
The shift register that the described sample circuit of such scheme is made of n level d type flip flop, wherein n is the figure place that frequency dividing circuit inputs to the input signal of sample circuit.
The moving of the described sample circuit of such scheme deposit pulsed frequency equal sample circuit the sampling pulse frequency n doubly, wherein n is the figure place that frequency dividing circuit inputs to the input signal of sample circuit.
The described frequency dividing circuit of such scheme inputs to the span of figure place n of input signal of sample circuit preferably between 3～6, is preferably 4.
Compared with prior art, the utlity model has following characteristics:
1, coding circuit adopts width modulation (PWM) technology to encode, got rid of the phase mutual interference of using this coding input circuit between the different remote control user and producing, and under wireless transmission method, coded signal can be realized reliable transmission and reception, makes this coding input circuit have high reliability;
2, have 20 (20 addresses) ISNs, but 1,000,000 groups of (220) interior code combinations of pre-burning have reduced the repetition rate of coding.Reduced the intersymbol conflict between each user simultaneously, avoided aerial seizure and scanning to follow the tracks of and, had characteristics such as extremely strong confidentiality, intelligent, low-power consumption, low cost by the possibility that the disabled user uses without authorization;
3, coding circuit has only 9 pins, promptly 4 button input ends, voltage (Vcc), (Vss), two input ends of RC oscillator (OSC1 and OSC2) and an output terminal TXD, thereby lack than isocoding circuit number of pins;
4, do not need special-purpose decoding circuit, only need to decode, decoding program is directly embedded in the single-chip microcomputer, as long as study mutually to just using immediately behind the sign indicating number, greatly facilitates like this and produces and use, thereby reduce cost with software program;
5, as long as change the input (the all-zero signal input is not as telecommand generally speaking) of 4 buttons of coding input circuit, just can make coding export 15 tunnel different signals, rather than a road single signal, the input circuit of encoding so just possesses 15 kinds of different control function is arranged.This coding input circuit can be widely used in domestic automobile security system, garage control, remote control fighter robot, remote control panzer and the pilotless fighter.
Description of drawings
Fig. 1 is the circuit theory diagrams of a kind of remote control coding circuit based on FPGA of the utility model.
Embodiment
Fig. 1 is a kind of remote control coding circuit based on FPGA of the utility model, comprises the coding input circuit, storer, RC oscillatory circuit, frequency dividing circuit, synchronizing circuit, control circuit, sample circuit, address parallel-to-serial converter, coded pulse generator and the output control circuit that are formed by a plurality of key combination; Wherein the output terminal of RC oscillatory circuit connects frequency dividing circuit, synchronizing circuit, control circuit and storer respectively; Coding input circuit process storer links to each other with the address parallel-to-serial converter; The output terminal of synchronizing circuit and control circuit all is connected with the input end of output control circuit; In the frequency division output terminal of frequency dividing circuit a road directly links to each other with the address parallel-to-serial converter, and another Lu Zejing sample circuit is connected with the address parallel-to-serial converter; 2 different serial output terminals of frequency dividing circuit are connected on 2 corresponding input ends of coded pulse generator; The output terminal of address parallel-to-serial converter links to each other with the input end of coded pulse generator.
The RC oscillatory circuit is as the clock signal of entire circuit, and synchronizing circuit is as the distinguishing mark of remote control coding circuit.In order to make signal avoid phase mutual interference and intersymbol conflict, the output terminal d of location, old place parallel-to-serial converter adds that at output terminal c a not gate obtains, and the address parallel-to-serial converter has just obtained two outputs like this.When being output as c, with this output and the output Z1110 of frequency dividing circuit with; When being output as d, with this output and the output Z1000 of frequency dividing circuit with, two with after output through one or, or the door output just obtained f, the f of generation obtains coded signal TXD by output control circuit and has avoided crosstalking mutually, having reduced the repetition rate of coding.0,1 of each address bit is represented by serial " 1000 " and " 1110 " respectively.The external oscillation resistance of RC oscillatory circuit, the TXD end is the output terminal of coded signal (just often being low level), k4, k3, k2, k1 are four button input ends of coding circuit, the coded signal of output is formed a complete frame signal by synchronous code, address code and numeric data code, this coding circuit just can make coding export 15 tunnel different signals as long as change the input of combination button k4, k3, k2, k1 (the all-zero signal input is not as telecommand generally speaking).
The coding input circuit is used to produce different coded pulse signals and represents different telecommands, and each coding input circuit all has a kind of specific coded format.We the time of transmitting 1 bit 0,1 as a T of chronomere, the frequency of coded signal is f=1/T, each frame is made up of synchronous code, address code and numeric data code, synchronous code is used in the beginning of a frame, width is 8T, is the distinguishing mark of a frame; (A0～A19), width is 20T to 20 of address codes, is used to distinguish the serial code signal that different remote control transmitters send, and 20 bit address sign indicating numbers can be combined into 2
201048576 different remote control transmitters also just can be distinguished in=1048576 different addresses, greatly reduce the possibility that serial code signal that different remote control transmitters send is crosstalked mutually; (D0～D3), width is 4T to 4 of numeric data codes, is used to produce different telecommands; Time of occupying of a frame is 32T altogether.What the utility model adopted is PWM (pulse-length modulation) technology.Promptly corresponding to each state, coding input circuit inside can generate a kind of special coding, this coding also is made up of " 1 " and " 0 ", but be not simply with high level representative " 1 ", with low level representative " 0 ", but with different distinguish " 1 " and " 0 " of high level with the low level width ratio, just so-called dutycycle.In order to improve the reliability of this coding input circuit transmission serial signal, the interference of security and serial signal, so it is that 1/4 (1000) pulse represents 0 that the coding input circuit adopts the dutycycle of one-period, dutycycle is that 3/4 (1110) pulse represents 1, synchronizing signal is that 1/32 pulse is represented with a dutycycle, 4h=T among the figure, is time span among the figure that the high-low level of h is respectively as binary one and 0, synchronizing signal is expressed as 11 31 0 of adding sequential serial of serial so, and 0 and 1 of address or data bit represented with 1110 of 1000 and serial of serial respectively.
The RC oscillatory circuit provides global clock for the coding input circuit.It is made of CMOS not gate and RC element, and the input impedance of CMOS gate circuit is very high, so need not use jumbo capacitor, just can obtain bigger time constant, is particularly useful for the not too strict low-frequency clock oscillatory circuit of frequency stability and accuracy requirement.The oscillation frequency of RC oscillatory circuit depends on the value of RC, and approximate estimated sum is T=2.2RC.When " En=0 ", output terminal clk is fixed as " 0 "; Do not produce vibration; When " En=1 ", can discharge and recharge by RC, produce vibration at output terminal clk.The output terminal clk of this RC oscillatory circuit is as the input end of clock of entire circuit.
Memory built-in of the present utility model has decoding scheme.Decoding is the inverse process of coding, and the process of the represented information of each binary code of input being translated into the high and low level signal of corresponding output is called decoding, realizes that the circuit of decoding function is called decoding scheme.What the utility model was designed is 4-16 line decoding scheme, it is made of the address of decoding scheme four button k1, k2, k3, k4 of coding input circuit, 16 output terminals are Y0, Y1 ... Y15, wherein Y1, Y2 ... Y15 connects the word line of a not gate as storer respectively.By button k1, k2, k3, the k4 of coding input circuit address signal, constitute 4-16 line decoding scheme by address signal, output Y1, the Y2 of 4-16 line decoding scheme earlier as storer ... Y15 is as the word line of storer.The effect of address decoding circuitry is the information of correct sensing element array among the storer ROM.4 data output of storer is respectively as the input of 4 d type flip flops, the clock of each d type flip flop is clk, these 4 d type flip flops mainly play buffer action, and the output of 4 d type flip flop data is respectively as the D[4 of address parallel-to-serial converter], D[3], D[2], D[1] input signal.The function of this storer just can be exported 15 kinds of data bit signals as long as change the Input Address of 4-16 line decoding scheme.
The utility model frequency dividing circuit has two functions: one is simple frequency dividing circuit, and purpose is the clock signal reduction frequency with high frequency; It two is used for producing " 0 " and " 1 " that address bit and data bit are represented in 1000 and 1110,1000 and 1110 of serial respectively, simultaneously as a control signal of entire circuit.Can realize that above-mentioned 2 purpose frequency dividing circuits mainly adopt 2 d type flip flop primordials divide by four circuit originally; The effect of the output terminal a of this divide by four circuit mainly is the clock signal as sample circuit and address parallel-to-serial converter.This moment, the frequency of a was 1/4 times of whole coding input circuit global clock signal c1k frequency.The another one module is used for producing " 0 " and " 1 " that address bit and data bit are represented in 1000 and 1110,1000 and 1110 of serial respectively.While is as a control signal of entire circuit.In the utility model preferred embodiment, described frequency dividing circuit mainly by 2 d type flip flops, 2 not gates, 2 or and 3 formed with door institute.
In the coding input circuit, frame synchronization (ad-hoc location at every frame all sends out synchronizing signal) is the pith in the digital synchronous multiple connection equipment.The effect of synchronizing circuit is to produce the synchronizing signal with certain feature, and in decoding scheme, the effect of synchronizing circuit is that synchronizing signal is differentiated out.Synchronizing signal is generally represented with difform pulse.Synchronizing pulse is had following requirement: synchronizing pulse is stronger than the antijamming capability of command pulse, can improve the antijamming capability of remote control equipment like this; Synchronizing pulse should have the feature that is different from command pulse, so that decoding scheme can be differentiated out with it; The generation circuit of synchronizing pulse and discriminator circuit should be simple and reliable as far as possible.The speed of synchronizing circuit is meant the speed of synchronous clock, and synchronous clock is fast more, and the time interval of circuit treatmenting data is short more, and the data volume that circuit was handled in the unit interval is just big more.So this synchronizing circuit is made up of five d type flip flops and some gate circuits, have only a clock input signal clk, an output signal e, when the rising edge of input signal clk arrived, each d type flip flop just changed simultaneously.Have only after clock signal clk imports 32 clocks continuously, e just exports synchronizing signal 10000000000000000000000000000000.
Control circuit of the present utility model is made up of 7 d type flip flops and some gate circuits.Clock signal is provided by the output clk of RC oscillatory circuit, and two output signals are respectively as two input signals of output control circuit.
Sample circuit is the pulse signal that is written in parallel to as the control address parallel-to-serial converter.Have certain relation between parallel sampling pulse and the address parallel-to-serial converter, this relation is inputed to the figure place decision of the input signal of sample circuit by frequency dividing circuit.If the figure place of input signal is the n position, the shift register that is constituted by n level d type flip flop then, wherein n is the figure place that frequency dividing circuit inputs to the input signal of sample circuit.The moving of sample circuit deposit pulsed frequency equal sample circuit the sampling pulse frequency n doubly, wherein n is the figure place that frequency dividing circuit inputs to the input signal of sample circuit.Above-mentioned frequency dividing circuit inputs to the span of figure place n of input signal of sample circuit preferably between 3～6, and in the utility model preferred embodiment, the value of its n then is 4.Be that moving of sample circuit deposited pulsed frequency f
CpBe f
Cp=nf
Sa, f
SaBe parallel sampling pulse frequency, the width of parallel sampling pulse should be greater than moving the width of depositing pulse.The clock signal of sample circuit is the output a of frequency dividing circuit, and output signal b is as the parallel sampled signal of address parallel-to-serial converter.
The circuit that parallel digital signal can be converted to serial digital signal is called the address parallel-to-serial converter.So-called parallel signal be exactly the n signal line when transmission, must be that everybody transmits simultaneously.And serial signal transmits in order by turn from low level to a high position or from a high position to the low level.This address parallel-to-serial converter adopts 31 d type flip flops and some gate circuits to constitute.Clock signal is provided by the output a of frequency dividing circuit, and the frequency of a is 1/4 times of input clock signal clk frequency; Parallel sampled signal is provided by sample circuit, 41 and 124 0 of sample circuit output, and the frequency of parallel sampled signal is 1/128 times of clock signal clk frequency.The address parallel-to-serial converter at first constitutes the address parallel-to-serial converter by 24 d type flip flops, wherein address code is 20 addresses fixing, four data bit are by the output D[4 of storer], D[3], D[2], D[1] provide, they are respectively as the parallel input end of this address parallel-to-serial converter.There is the time-delay of a clock in the output of address parallel-to-serial converter, and the time-delay of a clock is 1/4 times of clock signal clk frequency.Location, old place parallel-to-serial converter has only after 100 clock signals of input output is just arranged.Because entire circuit is after 128 clock signals of input output to be arranged, thus 7 d type flip flops increased at the output terminal of address parallel-to-serial converter, as the time delayed signal of this circuit.Because the clock signal of address parallel-to-serial converter is a, these 7 d type flip flops 28 input clock signal clk that are equivalent to delay time so.The output terminal c of address parallel-to-serial converter and d are respectively as the input end of coded pulse generator.
Claims (6)
1. based on the remote control coding circuit of FPGA, it is characterized in that: comprise the coding input circuit, storer, RC oscillatory circuit, frequency dividing circuit, synchronizing circuit, control circuit, sample circuit, address parallel-to-serial converter, coded pulse generator and the output control circuit that form by a plurality of key combination; Wherein the output terminal of RC oscillatory circuit connects frequency dividing circuit, synchronizing circuit, control circuit and storer respectively; The coding input circuit links to each other with the input end of address parallel-to-serial converter through storer; The output terminal of synchronizing circuit and control circuit all is connected with the input end of output control circuit; In the frequency division output terminal of frequency dividing circuit a road directly links to each other with the address parallel-to-serial converter, and another Lu Zejing sample circuit is connected with the address parallel-to-serial converter; 2 different serial output terminals of frequency dividing circuit are connected on 2 corresponding input ends of coded pulse generator; The output terminal of address parallel-to-serial converter links to each other with the input end of coded pulse generator.
2. according to the described remote control coding circuit based on FPGA of claim 1, it is characterized in that: described memory built-in has decoding scheme.
3. according to the described remote control coding circuit based on FPGA of claim 1, it is characterized in that: described frequency dividing circuit is the divide by four circuit that 2 d type flip flops constitute.
4. according to the described remote control coding circuit based on FPGA of claim 1, it is characterized in that: the shift register of described sample circuit for being made of n level d type flip flop, wherein n is the figure place that frequency dividing circuit inputs to the input signal of sample circuit.
5. according to the described remote control coding circuit of claim 4, it is characterized in that based on FPGA: the moving of described sample circuit deposit pulsed frequency equal sample circuit the sampling pulse frequency n doubly, wherein n is the figure place that frequency dividing circuit inputs to the input signal of sample circuit.
6. according to claim 4 or 5 described remote control coding circuit based on FPGA, it is characterized in that: the figure place n that described frequency dividing circuit inputs to the input signal of sample circuit is 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206670288U CN201965746U (en) | 2010-12-17 | 2010-12-17 | Remote control encoding circuit based on FPGA (Field Programmable Gate Array) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206670288U CN201965746U (en) | 2010-12-17 | 2010-12-17 | Remote control encoding circuit based on FPGA (Field Programmable Gate Array) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201965746U true CN201965746U (en) | 2011-09-07 |
Family
ID=44528295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010206670288U Expired - Fee Related CN201965746U (en) | 2010-12-17 | 2010-12-17 | Remote control encoding circuit based on FPGA (Field Programmable Gate Array) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201965746U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104484992A (en) * | 2014-12-31 | 2015-04-01 | 广州科技贸易职业学院 | Infrared remote control decoder based on programmable logic device |
| CN105262565B (en) * | 2015-09-11 | 2018-10-09 | 烽火通信科技股份有限公司 | A kind of coding method and system for transmitting clock and data based on phase-modulation |
| CN109830098A (en) * | 2019-03-11 | 2019-05-31 | 攀枝花学院 | Infrared encoder and infrared communication device based on FPGA |
-
2010
- 2010-12-17 CN CN2010206670288U patent/CN201965746U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104484992A (en) * | 2014-12-31 | 2015-04-01 | 广州科技贸易职业学院 | Infrared remote control decoder based on programmable logic device |
| CN105262565B (en) * | 2015-09-11 | 2018-10-09 | 烽火通信科技股份有限公司 | A kind of coding method and system for transmitting clock and data based on phase-modulation |
| CN109830098A (en) * | 2019-03-11 | 2019-05-31 | 攀枝花学院 | Infrared encoder and infrared communication device based on FPGA |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103745590B (en) | A kind of infrared remote coding method | |
| CN103957056A (en) | Visible light communication system compatible with intelligent cell phone | |
| CN201965746U (en) | Remote control encoding circuit based on FPGA (Field Programmable Gate Array) | |
| CN101201970A (en) | Self-adaptive decoding method for wireless remote control receiving chip | |
| CN106063181A (en) | Clock recovery circuit for multiple wire data signals | |
| CN204482042U (en) | Based on the car crane monitoring system of MHL technology | |
| CN103147745A (en) | Three dimensional sonic logging data high-speed transmission device based on LVDS technology | |
| CN108429582A (en) | A kind of information sends, reception device and its maintaining method, system | |
| CN103700238A (en) | Four-way wireless remote control switch | |
| CN103793979B (en) | Method for upgrading photon receiving end | |
| CN105471788B (en) | A kind of low time delay decomposition method and device to DVBS2 signals | |
| CN106027196B (en) | A kind of data transmission method and system | |
| CN108599844A (en) | A kind of synchronous translation apparatus and its working method based on visible light communication technology | |
| CN104598946B (en) | A kind of method of testing of the minimum triggering power of the RFID label tag based on virtual instrument | |
| CN103731241A (en) | Encoding system and method for improving spectrum efficiency of communication system | |
| CN101465047B (en) | Intelligent remote controller and control method thereof | |
| CN104639287A (en) | Ultrasonic communication coding method and system | |
| CN110189509A (en) | A kind of wireless long-distance meter-reading system | |
| CN202500555U (en) | Data transmission system in petroleum logger | |
| CN104320754A (en) | MHL technology based vehicle machine monitoring system | |
| CN204790677U (en) | Anti -jamming clock and data recovery integrated circuit design | |
| CN103346860A (en) | Decoding unit of wireless transmission system and decoding method thereof | |
| CN104348468A (en) | Pulse width self-adaptive single-bus receiver | |
| CN102594400B (en) | Novel time hopping-pulse position keying and telemetering method | |
| CN202856782U (en) | Automatic receiving/transmitting and converting device for HART communication signals |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110907 Termination date: 20111217 |