CN109830098A - Infrared encoder and infrared communication device based on FPGA - Google Patents
Infrared encoder and infrared communication device based on FPGA Download PDFInfo
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Abstract
The present invention relates to infrared communication technique, it is low, at high cost to solve existing infrared communication device integrated level, and the problem that treatment effeciency is low.Technical solution is summarized are as follows: infrared communication device, FPGA is integrated in its microprocessor, infrared encoder is realized based on the FPGA in microprocessor, microprocessor provides order, data and clock signal to infrared encoder, infrared encoder completes data encoding and is output to infrared emission head transmitting signal, by FPGA realize control register, data register, frequency divider one, frequency divider two, PWM code converter, shift register and with the correlation function of door, and then combine realize the infrared encoder based on FPGA.Beneficial effect is: the present invention realizes the function of infrared encoder by FPGA, has saved processor resource, so that equipment overall treatment efficiency improves, and does not need to weld dedicated infrared coding chip and carry out corresponding wiring line, integrated level is improved.The present invention is especially suitable for household fields.
Description
Technical field
The present invention relates to infrared communication techniques, in particular to infrared coding technology.
Background technique
Existing infrared communication device executes program by dedicated infrared coding chip or processor and carries out data encoding with reality
Existing infrared communication.It is realized according to dedicated infrared coding chip, need to weld special chip on circuit boards and carries out phase
It should be routed, cause to research and develop cost, component increased costs, and be not easy to integrate, circuit board volume is big；It is held according to processor
Line program is realized, then needs processor to complete correlative coding work, can occupy a large amount of calculation processing resource in this way, so that
In the treatment effeciency for influencing equipment entirety.
Summary of the invention
The present invention is low, at high cost to solve existing infrared communication device integrated level, and the problem that treatment effeciency is low, provides
A kind of infrared encoder and infrared communication device based on FPGA.
To solve the above problems, the technical solution adopted by the present invention is that:
Based on the infrared encoder of FPGA (Field Programmable Gate Array), including control register, number
According to register, frequency divider one, frequency divider two, PWM code converter, shift register and with door, the input terminal of the frequency divider one
As original clock signal input interface, the input terminal of register is controlled as infrared emission command input interface, data register
The input terminal of device as infrared emission Data Input Interface, the input terminal of the frequency divider two and the input terminal of frequency divider one and
The clock signal input terminal of PWM code converter connects, the output end of frequency divider one and the clock signal input terminal of shift register
The enabled control terminal of connection, the output end and shift register that control register connects, the output end and PWM code of data register
The data input pin of converter connects, and the data output end of PWM code converter and the data input pin of shift register connect, with
Two input terminals of door are connect with the data output end of the output end of frequency divider two and shift register respectively, the output end with door
As infrared encoded signal output interface；
The frequency divider one generates clock signal one for being divided to original clock signal, and by clock signal one
It is output to shift register, the clock signal one clock signal required when working normally as shift register；
The frequency divider two generates clock signal two for being divided to original clock signal, and by clock signal two
It is output to and door, the clock signal two is used as modulated signal；
The infrared emission order received is sent to displacement for receiving infrared emission order by the control register
Register；
The infrared emission data received are sent to PWM for receiving infrared emission data by the data register
Code converter；
The PWM code converter is used for according to infrared coding agreement and the infrared emission data received, and when original
By infrared emission data conversion at PWM (Pulse Width Modulation) code under the action of clock signal, and the PWM that will be obtained
Code is sequentially loaded into shift register；
The shift register is used for according to the PWM code and infrared emission order received, and in the work of clock signal one
Successively PWM code is output to and door under；
The PWM code for being used to receive with door and the progress of clock signal two and operation, obtain modulated infrared volume
Code signal simultaneously exports；
The control register, data register, frequency divider one, frequency divider two, PWM code converter and shift register are all
It is programmed and is realized based on FPGA.
As advanced optimizing, the period of the clock signal one uses 0.56 millisecond.
As advanced optimizing, the frequency of the clock signal two uses 38 kHz.
Infrared communication device, including microprocessor and infrared emission head, the microprocessor include processing unit and above-mentioned
The infrared encoder based on FPGA, the processing unit respectively with the input terminal of frequency divider one, control register input terminal
It is connected with the input terminal of data register, it is described to be connect with the output end of door with infrared emission head；
The processing unit is used to generate infrared emission order and send control register for infrared emission order, and
For generating infrared emission data and send data register for infrared emission data, and for sending out original clock signal
It is sent to frequency divider one；The infrared emission head is for emitting infrared encoded signal.
As advanced optimizing, pass through between the processing unit and control register, data register and frequency divider one
Bus connection communication.
As advanced optimizing, above-mentioned infrared communication device further includes infrared receiving terminal, and the microprocessor further includes base
In the IR decoder of FPGA, the IR decoder based on FPGA connect with processing unit and infrared receiving terminal logical respectively
Letter, the infrared receiving terminal demodulate the infrared encoded signal received for receiving infrared encoded signal, and will solution
Infrared encoded signal after tune is sent to the IR decoder based on FPGA, and the IR decoder based on FPGA is for docking
The infrared encoded signal received is decoded, and sends processing unit for the data that decoding obtains.
Beneficial effect is: the present invention realizes the function of infrared encoder by FPGA, carries out processor when infrared communication
Infrared encoder of the invention need to be called, specific coding process all transfers to FPGA to realize, has saved processor resource,
So that equipment overall treatment efficiency is improved；In addition, most of chip interiors are all integrated with FPGA at present, it will be of the invention
Infrared encoder apply on such chip after, it is no longer necessary to weld dedicated infrared coding chip and carry out corresponding wiring line,
Integrated level is also improved, and makes the volume-diminished of circuit board and equipment.The present invention is especially suitable for household fields.
Detailed description of the invention
Fig. 1 is the frame structure of the infrared encoded signal of the embodiment of the present invention.
Fig. 2 is the pattern of the infrared emission code of the embodiment of the present invention.
Fig. 3 is the structural block diagram of the infrared encoder based on FPGA of the embodiment of the present invention.
Fig. 4 is the structural block diagram of the infrared communication device of the embodiment of the present invention.
Specific embodiment
With reference to the accompanying drawings and examples, technical solution of the present invention is further illustrated.
The technical scheme is that
Infrared encoder based on FPGA, including control register, data register, frequency divider one, frequency divider two, PWM
Code converter, shift register and with door, the input terminal of frequency divider one controls register as original clock signal input interface
Input terminal as infrared emission command input interface, the input terminal of data register as infrared emission Data Input Interface,
The input terminal of frequency divider two is connect with the clock signal input terminal of the input terminal of frequency divider one and PWM code converter, frequency divider one
Output end and the clock signal input terminal of shift register connect, control register output end and shift register it is enabled
Control terminal connection, the output end of data register are connect with the data input pin of PWM code converter, the data of PWM code converter
The connection of the data input pin of output end and shift register, with two input terminals of door respectively with the output end of frequency divider two and shifting
The data output end of bit register connects, and the output end with door is as infrared encoded signal output interface；
Frequency divider one exports clock signal one for being divided to original clock signal to generate clock signal one
To shift register, the clock signal one clock signal required when being worked normally as shift register；
Frequency divider two exports clock signal two for being divided to original clock signal to generate clock signal two
To with door, the clock signal two be used as modulated signal；
The infrared emission order received is sent to shift LD for receiving infrared emission order by control register
Device；
The infrared emission data received are sent to PWM code and turned by data register for receiving infrared emission data
Parallel operation；
PWM code converter is used for according to infrared coding agreement and the infrared emission data received, and is believed in original clock
By infrared emission data conversion at PWM (Pulse Width Modulation) code under the action of number, and by obtained PWM code according to
Secondary loading shift register；
Shift register is used for according to the PWM code and infrared emission order received, and under the action of clock signal one
Successively PWM code is output to and door；
The progress of PWM code and clock signal two and operation for being used to receive with door obtain modulated infrared coding letter
Number and export；
Control register, data register, frequency divider one, frequency divider two, PWM code converter and shift register are all based on
FPGA programming is realized.
Above by FPGA realize control register, data register, frequency divider one, frequency divider two, PWM code converter,
Shift register and correlation function with door, and then combine and realize the infrared encoder based on FPGA, encoder receives original
The data and firing order that clock signal, needs emit, by modulating simultaneously output signal with door after the completion of processing.
Infrared communication device, including microprocessor and infrared emission head, microprocessor include processing unit and above-mentioned base
In the infrared encoder of FPGA, processing unit is posted with the input terminal of frequency divider one, the input terminal of control register and data respectively
The input terminal of storage connects, and connect with the output end of door with infrared emission head；Processing unit is for generating infrared emission order simultaneously
Control register is sent by infrared emission order, and for generating infrared emission data and sending infrared emission data to
Data register, and for sending frequency divider one for original clock signal；Infrared emission head is for emitting infrared coding letter
Number.
Above-mentioned infrared communication device is integrated with FPGA in microprocessor, and infrared encoder is based in microprocessor
FPGA realizes that microprocessor provides order, data and clock signal to infrared encoder, and infrared encoder completes data encoding simultaneously
It is output to infrared emission head transmitting signal.
The above-mentioned infrared encoder based on FPGA is advanced optimized, specifically may is that the period of clock signal one
0.56 millisecond can be used, in a manner of matching the pulse-position modulation of currently used NEC6122 coding protocol.The frequency of clock signal two
Rate can use 38 kHz, so that infrared communication process is more reliable and more stable.
Above-mentioned infrared communication device is advanced optimized, specifically may is that processing unit and control register, data
Its fortune can be made between register and frequency divider one with the connection relationship between each functional unit of simplification by bus connection communication
Row is more reliable and more stable.Above-mentioned infrared communication device can also include infrared receiving terminal, and microprocessor can also include being based on
The IR decoder of FPGA, the IR decoder based on FPGA are infrared respectively with processing unit and infrared receiving terminal connection communication
Head is received for receiving infrared encoded signal, and the infrared encoded signal received is demodulated, and will be infrared after demodulation
Encoded signal is sent to the IR decoder based on FPGA, and the IR decoder based on FPGA is used for the infrared coding received
Signal is decoded, and sends processing unit for the data that decoding obtains, and utilizes the existing IR decoder based on FPGA
The data received are handled, the FPGA resource of microprocessor is made full use of, realizes higher integrated level.
Embodiment
With reference to the accompanying drawings and examples, the technical solution that the present invention will be described in detail.
In this example, microprocessor uses the ZYNQ7000 chip of Xilinx company, which is ARM+FPGA framework；It is infrared
Communication protocol uses NEC6122 coding protocol, and coding mode uses the serial code mode of pulse-position modulation.
Firstly, in this example infrared encoded signal frame structure as shown in Figure 1, each frame by guidance code, user code and data
Code composition, start-up portion is guidance code, is made of the high level of 9ms and the low level of 4.5ms, to remind reception circuit information
The beginning of transmission, followed by 8 bit User codes, 8 bit User radix-minus-one complements, 8 bit data codes and 8 bit data radix-minus-one complements.Arteries and veins position
The serial code mode of modulation is spaced 0.56 millisecond, the combination that the period is 1.12 milliseconds as shown in Fig. 2, with pulsewidth for 0.56 millisecond
Indicate binary " 0 "；It is 0.56 millisecond with pulsewidth, 1.68 milliseconds of interval, the combination that the period is 2.24 milliseconds indicate binary system
" 1 ", 32 infrared emission information is constituted by above-mentioned " 0 " and " 1 " code.
As shown in figure 4, the infrared communication device of this example, including ZYNQ7000 chip, infrared emission head and infrared receiving terminal,
ZYNQ7000 chip includes ARM processing unit, the infrared encoder based on FPGA and the IR decoder based on FPGA.Wherein,
Infrared encoder based on FPGA is as shown in figure 3, include control register, data register, frequency divider one, frequency divider two, PWM
Code converter, shift register and with door, the input terminal of frequency divider one passes through AXI as original clock signal input interface
Bus is connect with ARM processing unit, controls the input terminal of register as infrared emission command input interface, and total by AXI
Line is connect with ARM processing unit, and the input terminal of data register passes through AXI bus as infrared emission Data Input Interface
It is connect with ARM processing unit, the input terminal of frequency divider two and the clock signal of the input terminal of frequency divider one and PWM code converter are defeated
Enter end connection, the output end of frequency divider one and the clock signal input terminal of shift register connect, and control the output end of register
It being connect with the enabled control terminal of shift register, the output end of data register is connect with the data input pin of PWM code converter,
The data input pin of the data output end of PWM code converter and shift register connects, with two input terminals of door respectively with point
The output end of frequency device two is connected with the data output end of shift register, is connect with the output end of door as infrared encoded signal output
Mouthful, it is connect with infrared emission head.IR decoder based on FPGA connect with ARM processing unit and infrared receiving terminal logical respectively
Letter.
Control register, data register, frequency divider one, frequency divider two, the PWM code of infrared encoder based on FPGA turn
The corresponding function of parallel operation and shift register is programmed real using FPGA portion of the Verilog HDL language to ZYNQ7000 chip
It is existing.
When needing to emit infrared data, infrared emission order and infrared emission data are handled by the ARM of ZYNQ7000 chip
Unit generates, and original clock signal is generated by the clock circuit that ZYNQ7000 chip interior integrates, and ARM processing unit passes through AXI
Original clock signal is sent into frequency divider one, frequency divider two and PWM code converter by bus, and control is sent into infrared emission order and is posted
Infrared emission data are sent into data register by storage.PWM code converter is under the action of original clock signal, according to infrared
Binary code (i.e. infrared emission data) in data register is successively converted into PWM code by coding protocol, that is, by two into
System " 1 " is converted into " 1000 ", and binary zero is converted into " 10 ", and is sequentially loaded into since the 25th of shift register, moves
The 1st of bit register then fixes to the 24th and is packed into " 111111111111111100000000 ", i.e. and 16 " 1 " and 8 " 0 "
As guidance code, the data in the above shift register constitute data frame when transmitting.Frequency divider a pair of original clock letter
It number is divided, generates the clock signal that a cycle is 0.56 millisecond and be used to drive displacement bit register, shift register exists
Every 0.56 millisecond of mobile 1 data under the action of the infrared emission order sent of control register, output data to and door.
Frequency divider two divides original clock signal, the clock signal for generating 38 kHz be output to as modulated signal and
Door.With the PWM code of goalkeeper's input and the progress of clock signal two and operation, the modulation of infrared encoded signal is realized, then by infrared
Emitting head launches modulated infrared encoded signal.
When needing to receive infrared data, infrared receiving terminal receives infrared encoded signal, and believes the infrared coding received
It number amplifies, detection, shaping, the processing such as demodulation, then by treated, infrared encoded signal is sent to based on the red of FPGA
Outer decoder is decoded the infrared encoded signal received based on the IR decoder of FPGA, and the number that decoding is obtained
According to being sent to processing unit.Wherein the IR decoder based on FPGA is the prior art, and this example is no longer described in detail.
Claims (6)
1. the infrared encoder based on FPGA, which is characterized in that including control register, data register, frequency divider one, frequency dividing
Device two, PWM code converter, shift register and with door, the input terminal of the frequency divider one connects as original clock signal input
Mouthful, the input terminal of register is controlled as infrared emission command input interface, and the input terminal of data register is as infrared emission
Data Input Interface, the input terminal of the frequency divider two and the clock signal of the input terminal of frequency divider one and PWM code converter are defeated
Enter end connection, the output end of frequency divider one and the clock signal input terminal of shift register connect, and control the output end of register
It being connect with the enabled control terminal of shift register, the output end of data register is connect with the data input pin of PWM code converter,
The data input pin of the data output end of PWM code converter and shift register connects, with two input terminals of door respectively with point
The output end of frequency device two is connected with the data output end of shift register, is connect with the output end of door as infrared encoded signal output
Mouthful；
The frequency divider one exports clock signal one for being divided to original clock signal to generate clock signal one
To shift register, the clock signal one clock signal required when being worked normally as shift register；
The frequency divider two exports clock signal two for being divided to original clock signal to generate clock signal two
To with door, the clock signal two be used as modulated signal；
The infrared emission order received is sent to shift LD for receiving infrared emission order by the control register
Device；
The infrared emission data received are sent to PWM code and turned by the data register for receiving infrared emission data
Parallel operation；
The PWM code converter is used for according to infrared coding agreement and the infrared emission data received, and is believed in original clock
By infrared emission data conversion at PWM code under the action of number, and obtained PWM code is sequentially loaded into shift register；
The shift register is used for according to the PWM code and infrared emission order received, and under the action of clock signal one
Successively PWM code is output to and door；
The PWM code for being used to receive with door and the progress of clock signal two and operation, obtain modulated infrared coding letter
Number and export；
The control register, data register, frequency divider one, frequency divider two, PWM code converter and shift register are all based on
FPGA programming is realized.
2. as described in claim 1 based on the infrared encoder of FPGA, which is characterized in that the period of the clock signal one adopts
With 0.56 millisecond.
3. as described in claim 1 based on the infrared encoder of FPGA, which is characterized in that the frequency of the clock signal two is adopted
With 38 kHz.
4. infrared communication device, including microprocessor and infrared emission head, which is characterized in that the microprocessor includes that processing is single
Member and the described in any item infrared encoders based on FPGA of claim 1-3, the processing unit respectively with frequency divider one
Input terminal, the input terminal for controlling register are connected with the input terminal of data register, the output end and infrared emission with door
Head connection；
The processing unit is used to generate infrared emission order and send control register for infrared emission order, and is used for
It generates infrared emission data and sends data register for infrared emission data, and for sending original clock signal to
Frequency divider one；The infrared emission head is for emitting infrared encoded signal.
5. infrared communication device as claimed in claim 4, which is characterized in that the processing unit and control register, data
Pass through bus connection communication between register and frequency divider one.
6. infrared communication device as claimed in claim 4, which is characterized in that it further include infrared receiving terminal, the microprocessor
Further include the IR decoder based on FPGA, the IR decoder based on FPGA respectively with processing unit and infrared receiving terminal
Connection communication, the infrared receiving terminal demodulate the infrared encoded signal received for receiving infrared encoded signal,
And the IR decoder based on FPGA is sent by the infrared encoded signal after demodulation, the IR decoder based on FPGA is used
It is decoded in the infrared encoded signal received, and sends processing unit for the data that decoding obtains.
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