CN201956987U - High-speed and low-consumption DPWM used in adjustable output NC power supply - Google Patents

Abstract

A high-speed and low-consumption DPWM (Digital Pulse-Width Modulator) used in an adjustable output NC (Numerical Control) power supply comprises a pre-regulating logic circuit, a gated clock logic circuit, a counting comparison/delay hybrid circuit, and an output logic circuit. The two input ends of the pre-regulating logic circuit are respectively connected with pre-regulating fixed duty cycle command signals and input clock signals; and the three output ends of the pre-regulating logic circuit are connected with the gated clock logic circuit, the counting comparison/delay hybrid circuit and the output logic circuit. The three input ends of the gated clock logic circuit are connected with the input clock signals and the two output ends of the pre-regulating logic circuit; and the output end of the gated clock logic circuit is connected with the counting comparison/delay hybrid circuit. The three input ends of the counting comparison/delay hybrid circuit are respectively connected with input duty cycle low-position control commands, the pre-regulating logic circuit and the one output end of the gated clock logic circuit. And the input end of the output logic circuit is connected with the pre-regulating logic circuit, the gated clock logic circuit and the counting comparison/delay hybrid circuit; and the output end of the output logic circuit is used for generating duty cycle control signals.

Description

The high speed low consumption digital pulse-width modulator that is used for adjustable output DCPS digitally controlled power source

Technical field

The utility model relates to digital pulse width modulation circuit (DPWM), especially is applied to a kind of high-speed low-power-consumption digital pulse-width modulator in the digital control switching power circuit of output voltage Adjustable real-time, relates to the design of integrated circuit, belongs to electronic technology field.

Background technology

Adopt the Switching Power Supply of digital feedback control, can show the performance that improves system,, can realize complicated control algolithm, and the susceptibility that external condition is changed is lower because digital control method is flexible and changeable.Therefore digital control Switching Power Supply more and more is applied in the SoC system, and colory supply voltage is provided, and this also has higher requirement to power supply conversely.

Require power supply ripple more and more littler, mean that the quantified precision of quantizer is more and more higher in the control loop, promptly quantizer has high-resolution.And it is distinctive because the output limit ring oscillation that quantization resolution does not match and brings also requires the DPWM quantizer to have high-resolution in order to eliminate in the digital control loop.In addition, usually adopt dynamic electric voltage modulation (DVS, Dynamic Voltage Scale) technology in the SoC system, can change required supply voltage and operating frequency value according to different loading conditions, thus the total power consumption of reduction system.And for Switching Power Supply, being can be according to the size of the instant conversion output voltage values of external control order.This transient response speed to power supply has also proposed higher requirement.

In the existing digital pulse-width modulator scheme, high-resolution requirement tends to cause circuit area or clock work frequency too high, adopts the DPWM of counting comparison-delay line mixed structure usually, compromises between circuit area and clock frequency.Mixed type DPWM circuit is that the duty cycle command signal that needs are modulated is divided into coarse adjustment part and accurate adjustment part, and acting in conjunction is controlled the size of final duty cycle signals in the rest-set flip-flop of output.Under or the situation that the resolution scope is bigger higher at resolving accuracy, also more in the resolution figure place that this modulation system need be handled, can make that equally power consumption increases in the circuit.And when requiring the output voltage steady-state value to change, this structure can only slowly be regulated step by step according to the state of current voltage and expectation voltage.Therefore, for satisfying SoC for the supply voltage performance demands, need improve Switching Power Supply, particularly the DPWM circuit is optimized, guaranteeing to reduce loss under the constant situation of effective resolving accuracy, output voltage is followed the speed of variation when improving the control signal variation simultaneously.

The utility model content

The utility model provides a kind of high speed low consumption digital pulse-width modulator that is used for adjustable output DCPS digitally controlled power source, on the basis that keeps advantages such as existing counting comparison-delay line mixed structure DPWM scheme chips area, power loss, adopt the premodulated mode, guaranteeing to have reduced the resolution figure place under the constant situation of effective resolving accuracy, fundamentally guarantee low operating frequency and little circuit area, reduced circuit power consumption.And can rapidly the output duty cycle value be adjusted near the desired value, shorten regulating cycle, improve the response speed of system.

The utility model detailed technology scheme is:

The high speed low consumption digital pulse-width modulator that is used for adjustable output DCPS digitally controlled power source described in the utility model, comprise: counting comparison-delay hybrid circuit and output logic circuit, described output logic circuit comprises second comparator, rest-set flip-flop, first selector and second selector, an input of described first selector compares output with the counting of described counting comparison-delay hybrid circuit and is connected, the output of first selector is connected with the reset terminal R of rest-set flip-flop, the set end S of rest-set flip-flop is connected with the inhibit signal output of described counting comparison-delay hybrid circuit, the output of rest-set flip-flop is connected with an input of second selector, be connected with the preconditioning logical circuit on another input of second selector, described preconditioning logical circuit comprises frequency divider, gate, second counter and the 3rd comparator, the input of described frequency divider is used for input clock signal (clk), the output of frequency divider is connected with the input of second counter, the output of second counter is connected with the B end of the 3rd comparator, and the input of described gate is used to import preset fixed duty cycle command signal (V _Ref), the output of gate is connected with the A end of the 3rd comparator, another input of second selector in first output of the 3rd comparator and the output logic circuit is connected, second output of the 3rd comparator is connected with the gated clock logical circuit, when the numerical value of the 3rd comparator A end numerical value greater than the B end, then first output of the 3rd comparator is exported high level, the second output output low level of the 3rd comparator, otherwise, the first output output low level of the 3rd comparator, second output output high level of the 3rd comparator, the B end of described second comparator is used for the high-order control command of input duty cycle, the output of the gate in the A of described second comparator end and the preconditioning logical circuit is connected, when the numerical value of second comparator A end numerical value greater than the B end, then second comparator is exported high level, otherwise, the second comparator output low level, and, described second comparator output signal is as the control signal of second selector, when second comparator output high level, second selector is exported first output end signal of the 3rd comparator, when the second comparator output low level, the output signal of second selector output rest-set flip-flop, another input of described first selector is connected with first output of the 3rd comparator in the described preconditioning logical circuit, the control end of first selector is connected with the output of gate in the described preconditioning logical circuit, when gate is output as complete zero the time, the counting that first selector is exported described counting comparison-delay hybrid circuit compares the fan-out certificate, when gate is output as non-full zero, first selector is exported the data of first output of the 3rd comparator in the described preconditioning logical circuit, the first input end of described gated clock logical circuit is connected with first output of the 3rd comparator, second input of gated clock logical circuit is connected with second output of the 3rd comparator, the 3rd input of gated clock logical circuit is used for input clock signal (clk), and be connected with the input of described frequency divider, the clock end of first counter in the output of gated clock logical circuit and the described counting comparison-delay hybrid circuit is connected.Described counting comparison-delay hybrid circuit comprises first counter, first comparator, groups of delay cells and MUX, the reset terminal of described first counter links to each other with first output of the 3rd comparator of described preconditioning logical circuit, the A input of first comparator links to each other with the output of described first counter, the B input of first comparator is used for input duty cycle low level control command, when the numerical value of first comparator A end numerical value greater than the B end, then first comparator is exported high level, otherwise, the first comparator output low level, the output of described first comparator compares output for the counting of counting comparison-delay hybrid circuit and is connected with the input of described groups of delay cells, the multichannel output of groups of delay cells is as the multichannel input of described MUX, the selecting side of described MUX is used for input duty cycle lowest order control command, and MUX is output as the inhibit signal output of counting comparison-delay hybrid circuit.

For a Switching Power Supply, when input and output voltage was determined, the dutyfactor value Dn size during its stable state was a fixed value.When practical adjustments, except dutyfactor value in the circuit start process can change on a large scale, in most cases dutyfactor value just carries out adjusting change among a small circle near steady-state value.And the purpose that duty ratio changes significantly when starting also is the dutyfactor value size that obtains stable state in order to adjust.Therefore, can think that dutyfactor value maintains on the fixing horizontal the most at last for a definite switch power supply system of input and output voltage relation.According to this thinking, the duty cycle signals separated into two parts of finally exporting can be considered: first is the dutyfactor value dn of fixed size _Fix, the size of the dutyfactor value Dn of the size of its value during with stable state is relevant; Second portion is actual required duty ratio dn and the fixed duty cycle dn that has generated _FixBetween difference dn _Diff, its size is relevant with instant actual output voltage value constantly.Fixed duty cycle dn _FixCan fast output duty cycle be transferred to final needs and stablize near the dutyfactor value, shorten modulating time, improve response speed; And difference duty ratio dn _DiffBe a relative a small amount of, it can reach higher resolving accuracy with limited resolution figure place, has promptly reduced the resolution figure place that the accurate adjustment part will realize, thereby has reduced the hardware resource occupancy.

In order to increase the versatility of circuit, can modulate fast and effectively for different output voltages, partly increase by one in preconditioning and judge Compare Logic, possible output voltage is divided into several intervals, the different preset dutyfactor value of difference output according to interval of living in, guaranteed that promptly preset duty ratio and actual value are comparatively approaching, made the dynamic adjustments part unlikely excessive again.

For the N-bit DPWM of routine, suppose that the scope of corresponding adjustable voltage is [0%, 100%V], so the degree of regulation of the output duty cycle minimum of DPWM is V/2 ^NDPWM preconditioning in the utility model partly supposes to have divided n interval, the scope of total adjustable voltage still is [0%, 100%V], then the size of the adjustable voltage of each interval correspondence all is Δ V=V/n, use the DPWM of m-bit counting comparison-delay mixed structure, if will reach the resolving accuracy same, then have with the DPWM of top conventional N-bit:

$\frac{V/n}{2^m}=\frac{V}{2^N}\⇒2^m\·n=2^N\⇒m=N-{\log }_{2}n$

Following formula is the interval number n of preconditioning logical circuit division and the relational expression between the counting comparison-delay hybrid circuit resolution figure place m.Number n is many more between preconditioning logical circuit dividing regions, and then the resolution figure place that need regulate of counting comparison-delay hybrid circuit is just more little.If the clock frequency fs with the final duty cycle signals that generates of DPWM is a benchmark, adopt the mode of counter and comparator combination to generate the preset duty ratio, the counting clock of preconditioning part counter is nf _s, interval number n is many more, means that then the counting clock of counter doubly increases exponentially; But interval number n is too small, means that the resolution figure place m of counting comparison-delay hybrid circuit is bigger, and the counting clock frequency that it comprised or the area of MUX also must increase.Therefore the selection of interval number n of preconditioning logical circuit and counting comparison-delay hybrid circuit resolution figure place m need be got compromise between area and power consumption.N can get arbitrary value in theory, but it is convenient to be generally hardware circuit design, and interval number n is chosen for 2 index doubly, and then counting comparison-delay hybrid circuit resolution figure place m also can correspondingly determine.

The interval at duty cycle signals place when the preconditioning logical circuit is at first chosen stable state according to the value of outside preset fixed duty cycle command signal, produce the corresponding preset fixed duty cycle in this interval, and judge that current input duty cycle command signal requires the magnitude relationship of the duty ratio size that generates and the fixed duty cycle of preconditioning generation.If the duty ratio that the dutyfactor value that current requirement produces produces less than preconditioning, then the duty cycle signals of final output is the fixed duty cycle of preconditioning logical circuit generation; If the duty ratio that the dutyfactor value that current requirement produces produces greater than preconditioning, then counting comparison-the delays hybrid circuit of back level is started working, pairing dutyfactor value behind the fixed duty cycle that its duty ratio that will produce size partly produces for current outside input duty cycle command signal value removal preconditioning.The pulse signal acting in conjunction that duty cycle signals that the preconditioning logical circuit produces and counting comparison-delay hybrid circuit produce produces final duty cycle signals in output logic.

The utility model is compared with the DPWM circuit arrangement of routine, regulates the precision of DPWM in a small range, is therefore reaching under the situation of same resolving accuracy, can reduce the resolution figure place that needs adjusting.The preregulated mode of duty ratio also can reduce modulating time simultaneously, improves transient response speed.

Advantage of the present utility model and useful achievement:

1), realizes higher resolving accuracy, resource utilization height with less resource;

2) obtain required duty ratio, fast, transient response performance is better;

3), the high frequency clock time-sharing work, reduced the circuit dynamic power dissipation;

4), circuit structure is simple, is made up of the standard gate circuit, be easy to realize and preparation technology simple.

Description of drawings

Fig. 1 is basic counting comparison-delay line mixed type digital pulse width modulation circuit structured flowchart

Fig. 2 is basic counting comparison-delay line mixed type digital pulse width modulation circuit key signal sequential chart

Fig. 3 is a digital pulse width modulation circuit structured flowchart of the present utility model

Fig. 4 is digital pulse width modulation circuit main modular signal relation figure of the present utility model

Fig. 5 is a key signal sequential chart in the digital pulse width modulation circuit of the present utility model

Fig. 6 is digital pulse width modulation circuit preset piecewise interval of the present utility model and resolving accuracy schematic diagram

Fig. 7 is a segment logic schematic diagram in the preconditioning logic of digital pulse width modulation circuit of the present utility model

Fig. 8 is a gated clock logical circuitry in the digital pulse width modulation circuit of the present utility model

Embodiment

The high speed low consumption digital pulse-width modulator that is used for adjustable output DCPS digitally controlled power source, comprise: counting comparison-delay hybrid circuit 1 and output logic circuit 2, described output logic circuit 2 comprises second comparator 21, rest-set flip-flop 22, first selector 23 and second selector 24, an input of described first selector 23 compares output with the counting of described counting comparison-delay hybrid circuit 1 and is connected, the output of first selector 23 is connected with the reset terminal R of rest-set flip-flop 22, the set end S of rest-set flip-flop 22 is connected with the inhibit signal output of described counting comparison-delay hybrid circuit 1, the output of rest-set flip-flop 22 is connected with an input of second selector 24, be connected with preconditioning logical circuit 3 on another input of second selector 24, described preconditioning logical circuit 3 comprises frequency divider 31, gate 32, second counter 33 and the 3rd comparator 34, the input of described frequency divider 31 is used for input clock signal (clk), the output of frequency divider 31 is connected with the input of second counter 33, the output of second counter 33 is connected with the B end of the 3rd comparator 34, and the input of described gate 32 is used to import preset fixed duty cycle command signal (V _Ref), the output of gate 32 is connected with the A end of the 3rd comparator 34, another input of second selector 24 in first output of the 3rd comparator 34 and the output logic circuit 2 is connected, second output of the 3rd comparator 34 is connected with gated clock logical circuit 4, when the numerical value of the 3rd comparator 34A end numerical value greater than the B end, then first output of the 3rd comparator 34 is exported high level, the second output output low level of the 3rd comparator 34, otherwise, the first output output low level of the 3rd comparator 34, second output output high level of the 3rd comparator 34, the B end of described second comparator 21 is used for the high-order control command of input duty cycle, the output of the gate 32 in the A of described second comparator 21 end and the preconditioning logical circuit 3 is connected, when the numerical value of second comparator 21A end numerical value greater than the B end, then second comparator 21 is exported high level, otherwise, second comparator, 21 output low levels, and, described second comparator, 21 output signals are as the control signal of second selector 24, when second comparator, 21 output high level, first output end signal of second selector 24 outputs the 3rd comparator 34, when second comparator, 21 output low levels, the output signal of second selector 24 output rest-set flip-flops 22, another input of described first selector 23 is connected with first output of the 3rd comparator 34 in the described preconditioning logical circuit 3, the control end of first selector 23 is connected with the output of gate 32 in the described preconditioning logical circuit 3, when gate 32 is output as complete zero the time, the counting of the described counting comparison-delay hybrid circuit 1 of first selector 23 outputs is the fan-out certificate relatively, when gate 32 is output as non-full zero, the data of first output of the 3rd comparator 34 in the described preconditioning logical circuit 3 of first selector 23 outputs, the first input end of described gated clock logical circuit 4 is connected with first output of the 3rd comparator 34, second input of gated clock logical circuit 4 is connected with second output of the 3rd comparator 34, the 3rd input of gated clock logical circuit 4 is used for input clock signal (clk), and be connected with the input of described frequency divider 31, the clock end of first counter 11 in the output of gated clock logical circuit 4 and the described counting comparison-delay hybrid circuit 1 is connected.Described counting comparison-delay hybrid circuit 1 comprises first counter 11, first comparator 12, groups of delay cells 13 and MUX 14, the reset terminal of described first counter 11 links to each other with first output of the 3rd comparator 34 of described preconditioning logical circuit 3, the A input of first comparator 12 links to each other with the output of described first counter 11, the B input of first comparator 12 is used for input duty cycle low level control command, when the numerical value of first comparator 12A end numerical value greater than the B end, then first comparator 12 is exported high level, otherwise, first comparator, 12 output low levels, the output of described first comparator 12 compares output for the counting of counting comparison-delay hybrid circuit 1 and is connected with the input of described groups of delay cells 13, the multichannel output of groups of delay cells 13 is as the multichannel input of described MUX 14, the selecting side of described MUX 14 is used for input duty cycle lowest order control command, and MUX 14 is output as the inhibit signal output of counting comparison-delay hybrid circuit 1.

Below in conjunction with accompanying drawing and example circuit structure of the present utility model, operation principle and process are described further.

Referring to Fig. 3, Fig. 4, the high-speed low-power-consumption digital pulse-width modulator that is used for digital control Switching Power Supply of the present utility model has adopted segmentation preconditioning and mixed type DPWM associating modulated structure.The fixed duty signal dn that utilizes the preconditioning logic to produce _FixWith the accurate difference duty cycle signals dn that mixes the DPWM generation _DiffLogical combination, obtain final required duty cycle signals dn.

Suppose a N=9bits, output duty cycle signal frequency f _sThe routine counting comparison-delay mixed type DPWM of=1MHz utilizes structure of the present utility model to design.External control signal V _Ref[N-1:0] and duty ratio control command signal dn[N-1:0] all be the binary code input of 9bits, with V _Ref[8:0] and dn[8:0] expression, input range is [9 ' b000000000,9 ' b 111111111].

Differentiate figure place m according to interval number n, counting comparison-delay hybrid circuit that the preconditioning logical circuit is divided, and the relational expression between the DPWM equivalence resolution, N: m=N-log ₂N, preconditioning module piecewise interval is got n=2 ³, mix DPWM resolution figure place and get m=6bits.With external control signal V _RefPossible value be divided into 8 sections, all corresponding fixing minimum duty cycle value dn of each section _Fixx, the minimum duty cycle value dn of piecewise interval n and respective fixation _FixxBetween corresponding relation see shown in Figure 6.Table 1 has provided the corresponding relation of gate input and output in the preconditioning logical circuit.

The corresponding relation of table 1, fixed duty cycle value and input reference

Case of external control signal V _Ref[8:0]=9 ' b 010100000, affiliated interval be [25%V, 37.5%V), fixedly minimum duty cycle dn that this is interval corresponding _Fix3Value is 0.25, obtains output interval position signalling dn by the gate of being made up of 8 alternative selectors shown in Figure 7 _Situation=3 ' b 010.Interval position signalling dn _SituationThe count signal count2 that generates with second counter is as the input signal of the 3rd comparator in the pre-regulating circuit.The counting clock clk of second counter _Count2Be to obtain by the frequency divider frequency division, size is nf _s=8MHz.The 3rd comparator is judged dn _SituationWith the size of count2, work as dn _SituationDuring＞count2, first output output high level, otherwise output low level is preset duty cycle signals dn _FixWork as dn _SituationDuring＜count2, second output output high level, otherwise output low level, this signal is sent in the gated clock logical circuit as one tunnel control signal en2 of clock latching logic.

The major function of clock latching logic is according to latch control signal dn _FixWith the state of en2, when needed high frequency input clock clk to be sent in the counting comparison-delay hybrid circuit, when not needing this clock, with the high frequency clock blockade of input, the first counter count1 in the counting comparison-time-delay hybrid circuit stops counting.That is to say fixed duty signal dn in the output of preconditioning logical circuit _FixKeep during the level, the first counter clock end of counting comparison-delay hybrid circuit is blocked, and counting comparison-delay hybrid circuit is not worked, and can effectively reduce the dynamic power dissipation in the circuit.In addition, the reset signal of first counter is also by dn _FixTake on, work as dn _FixDuring for low level, first counter is resetted.The circuit diagram of clock latching logic as shown in Figure 8.

The duty ratio Dn size that needs when supposing the system is stablized is 0.32, and pre-regulating circuit has generated 0.25 duty ratio, and 0.07 of remainder dutyfactor value then will be produced by the counting comparison-delay hybrid circuit of back level so.This moment, the clock latching logic was delivered to the clock end of first counter with high frequency clock, and counting comparison-delay hybrid circuit is started working.The course of work of counting comparison-delay line hybrid circuit is consistent with conventional counting comparison-delay mixed type DPWM.According to interval position signalling dn in the table 1 _SituationWith external control signal V _RefThe wayside signaling at [8:0] place as can be seen, the interval position signalling dn in each interval _SituationBe this interval and comprise the high position of wayside signaling value, be high 3 in this example, that is to say, when stablizing duty ratio Dn and also using the 9bits numeric representation, the duty ratio size of high 3bits correspondence is produced by pre-regulating circuit, and therefore the data of counting comparison-delay line hybrid circuit processing are low 6.

But in fact counting comparison-delay line hybrid circuit to produce the size of duty ratio be by duty ratio control command dn[8:0] numerical value definite.Duty ratio control command dn[8:0] size of value is relevant with the system real-time status, is not to equal to stablize duty ratio always.Therefore for dn[8:0] processing be divided into two kinds of situations.A kind of situation is dn[8:6]＜dn _SituationThe time, representing the given dn[8:0 of current system] value is less than when stablizing the dutyfactor value that needs, the also fixed duty cycle dn that is promptly produced by the preconditioning logical circuit _FixGreater than the duty ratio dn[8:0 of present stage system requirements], do not need counting comparison-delay line hybrid circuit to continue to adjust, this moment, the clock end of first counter was blocked, counter is not worked, guarantee to count comparison-delay line hybrid circuit and do not work, the size of the duty cycle signals of the final output of circuit only produces preset fixed duty cycle dn by the preconditioning logical circuit _FixSize decision.Second kind of situation is dn[8:6] 〉=dn _SituationThe time, the duty ratio size dn[8:0 that is representing current system requirements to produce] be greater than the fixed duty cycle dn that produces by the preconditioning logical circuit _FixThis moment, counting comparison-delay line hybrid circuit was started working, low 5 dn[5:0 to the duty ratio control command of input] handle the preset fixed duty cycle that the size of the duty cycle signals of the final output of circuit is generated by the preconditioning logical circuit and counting comparison signal (coarse adjustment signal) dn of counting comparison-delay line hybrid circuit generation _High, inhibit signal (accurate adjustment signal) dn _LowCommon definite.Of particular note, dn[8:6]=dn _SituationThe time, the duty cycle signals of final output is the duty ratio size of the actual requirement of current system, and dn[8:6]＞dn _SituationThe time, represent the dutyfactor value of duty ratio size that current system requirements produces needs when stablize, the preset fixed duty cycle has obtained near the dutyfactor value the stable duty ratio, if by actual dn[8:0] produce, system may overregulate phenomenon, therefore only regulate with the status of input duty cycle control command this moment, the duty ratio that makes circuit export maintains to be stablized near the duty ratio.

According to last surface analysis, the size of the duty cycle signals of the final output of output logic circuit is that the preconditioning logical circuit produces preset fixed duty cycle dn _FixCounting comparison signal dn with the generation of counting comparison-delay line hybrid circuit _High, inhibit signal dn _LowLogical combination, mainly be that two kinds of output duty cycle signals are in particular cases handled:

1), as preset duty ratio output dn _FixDuring for complete hanging down, promptly without the preset effect, directly produce accurate duty cycle signals by mixing DPWM, the reset terminal of rest-set flip-flop is by the coarse adjustment duty cycle signals dn that mixes counting Compare Logic generation among the DPWM at this moment _HighControl; Otherwise the reset terminal of rest-set flip-flop is by preset duty ratio output signal dn _FixControl.

2), in system's initial condition process, preset duty ratio output dn _FixCan turn-off the accurate modulation that mixes DPWM this moment greater than the duty cycle command signal that requires this moment, the duty cycle signals that produces with the preset module carries out rapid adjustment.

Logical relation between them is as shown in table 2.The sequential chart of key signal is referring to shown in the accompanying drawing 5 in the circuit.

Output duty cycle signal dn has two kinds of outputs: the preset fixed duty signal dn that the preconditioning logical circuit produces _FixThe perhaps dn that generates of rest-set flip-flop _RealSignal, alternative condition are to judge interval position signalling dn _SituationWith the input high 3 dn[8:6 of duty ratio control command] size, work as dn _Situation＞dn[8:6] time, output preset fixed duty signal dn _Fix, work as dn _Situation≤ dn[8:6] time, the dn that the output rest-set flip-flop generates _RealSignal.The inhibit signal output dn that the reset terminal of rest-set flip-flop is partly produced by delay line in the counting comparison-delay line hybrid circuit _LowTrigger, the set end of rest-set flip-flop is the output of first selector, as preset duty ratio output dn _FixIt is 0 o'clock, by counting comparison signal dn in the counting comparison-delay line hybrid circuit _HighAsserts signal as rest-set flip-flop; Otherwise by preset duty ratio output dn _FixAs asserts signal.

Table 2, output duty cycle dn and M signal dn _RealThe logic corresponding relation

Claims (2)

1. high speed low consumption digital pulse-width modulator that is used for adjustable output DCPS digitally controlled power source, comprise: counting comparison-delay hybrid circuit (1) and output logic circuit (2), it is characterized in that, described output logic circuit (2) comprises second comparator (21), rest-set flip-flop (22), first selector (23) and second selector (24), an input of described first selector (23) compares output with the counting of described counting comparison-delay hybrid circuit (1) and is connected, the output of first selector (23) is connected with the reset terminal R of rest-set flip-flop (22), the set end S of rest-set flip-flop (22) is connected with the inhibit signal output of described counting comparison-delay hybrid circuit (1), the output of rest-set flip-flop (22) is connected with an input of second selector (24), be connected with preconditioning logical circuit (3) on another input of second selector (24), described preconditioning logical circuit (3) comprises frequency divider (31), gate (32), second counter (33) and the 3rd comparator (34), the input of described frequency divider (31) is used for input clock signal (clk), the output of frequency divider (31) is connected with the input of second counter (33), the output of second counter (33) is connected with the B end of the 3rd comparator (34), and the input of described gate (32) is used to import preset fixed duty cycle command signal (V _Ref), the output of gate (32) is connected with the A end of the 3rd comparator (34), an input of the second selector (24) in first output of the 3rd comparator (34) and the output logic circuit (2) is connected, second output of the 3rd comparator (34) is connected with gated clock logical circuit (4), when the numerical value of the 3rd comparator (34) A end numerical value greater than the B end, then first output of the 3rd comparator (34) is exported high level, the second output output low level of the 3rd comparator (34), otherwise, the first output output low level of the 3rd comparator (34), second output output high level of the 3rd comparator (34), the B end of described second comparator (21) is used for the high-order control command of input duty cycle, the output of the gate (32) in the A of described second comparator (21) end and the preconditioning logical circuit (3) is connected, when the numerical value of second comparator (21) A end numerical value greater than the B end, then second comparator (21) is exported high level, otherwise, second comparator (21) output low level, and, described second comparator (21) output signal is as the control signal of second selector (24), when second comparator (21) output high level, first output end signal of second selector (24) output the 3rd comparator (34), when second comparator (21) output low level, the output signal of second selector (24) output rest-set flip-flop (22), another input of described first selector (23) is connected with first output of the 3rd comparator (34) in the described preconditioning logical circuit (3), the control end of first selector (23) is connected with the output of gate (32) in the described preconditioning logical circuit (3), when gate (32) is output as complete zero the time, the counting of first selector (23) the described counting comparison-delay hybrid circuit of output (1) is the fan-out certificate relatively, when gate (32) when being output as non-full zero, the data of first output of the 3rd comparator (34) in first selector (23) the described preconditioning logical circuit of output (3), the first input end of described gated clock logical circuit (4) is connected with first output of the 3rd comparator (34), second input of gated clock logical circuit (4) is connected with second output of the 3rd comparator (34), the 3rd input of gated clock logical circuit (4) is used for input clock signal (clk), and be connected with the input of described frequency divider (31), the clock end of first counter (11) in the output of gated clock logical circuit (4) and the described counting comparison-delay hybrid circuit (1) is connected.

2. the high speed low consumption digital pulse-width modulator that is used for adjustable output DCPS digitally controlled power source according to claim 1, it is characterized in that, described counting comparison-delay hybrid circuit (1) comprises first counter (11), first comparator (12), groups of delay cells (13) and MUX (14), the reset terminal of described first counter (11) links to each other with first output of the 3rd comparator (34) of described preconditioning logical circuit (3), the A input of first comparator (12) links to each other with the output of described first counter (11), the B input of first comparator (12) is used for input duty cycle low level control command, when the numerical value of first comparator (12) A end numerical value greater than the B end, then first comparator (12) is exported high level, otherwise, first comparator (12) output low level, the output of described first comparator (12) compares output for the counting of counting comparison-delay hybrid circuit (1) and is connected with the input of described groups of delay cells (13), the multichannel output signal of groups of delay cells (13) is as the multichannel input of described MUX (14), the selecting side of described MUX (14) is used for input duty cycle lowest order control command, and MUX (14) is output as the inhibit signal output of counting comparison-delay hybrid circuit (1).

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