CN106230408A - Digital pulse width modulator based on digital delay - Google Patents
Digital pulse width modulator based on digital delay Download PDFInfo
- Publication number
- CN106230408A CN106230408A CN201610602607.6A CN201610602607A CN106230408A CN 106230408 A CN106230408 A CN 106230408A CN 201610602607 A CN201610602607 A CN 201610602607A CN 106230408 A CN106230408 A CN 106230408A
- Authority
- CN
- China
- Prior art keywords
- delay
- control signal
- signal
- module
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims abstract description 15
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 13
- 230000000630 rising effect Effects 0.000 claims description 15
- 230000036316 preload Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 2
- 229910002056 binary alloy Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 101100328360 Schizosaccharomyces pombe (strain 972 / ATCC 24843) clr1 gene Proteins 0.000 description 1
- 101100328361 Schizosaccharomyces pombe (strain 972 / ATCC 24843) clr2 gene Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002085 persistent effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
Landscapes
- Pulse Circuits (AREA)
Abstract
The invention discloses a kind of digital pulse width modulator based on digital delay, be made up of clock generating module, synchronous counting module, digital delay module and asynchronous signal generation module.Wherein clock generating module is input to synchronous counting module to generation fundamental clock signal after input clock signal frequency multiplication.Synchronous counting module produces coarse adjustment control signal and initial control signal is separately input to digital delay module and asynchronous signal generation module.Digital delay module realizes producing coarse adjustment control signal time delay 32 road termination control signals, is then selected termination control signal corresponding to a road by selector, and is entered into asynchronous signal generation module.In asynchronous signal generation module, termination control signal and initial control signal export final digital pulsewidth modulation (DPWM) signal by rest-set flip-flop.The present invention carries out precise delay by digital delay module to coarse adjustment control signal can realize the digital pulsewidth modulation (DPWM) of higher precision, has stronger accuracy, versatility and the suitability.
Description
Technical field
The invention belongs to electronic technology field, be specifically related to a kind of digital pulsewidth modulation circuit.
Background
In the system structure using digital pulsewidth modulation (Digital Pulse Width Modulation, DPWM),
The mode currently mainly used, one is mixed type DPWM(Hybrid DPWM), two use Dither mode to realize
DPWM.The thinking that the DPWM using Dither mode to realize mainly have employed realizes, and this design can use low precision high frequency
The DPWM of rate realizes higher effective output accuracy, decreases power consumption and the area of DPWM the most accordingly.But Dither side
The DPWM that formula realizes can produce cycle time delay when pattern switches, unfavorable to the high-speed response of DPWM.The design of mixed type DPWM
Then there is no unwanted time delay.
Mixed type DPWM combines traditional counter-type structure and time delay chain structure, generally by coarse adjustment module and fine tuning
Module forms.Assuming that input is a string binary system array dc (N:0), a high position is dc (N:m), and low level is dc (m:0).Coarse adjustment module
Use traditional counter structure, a high position determine the pulse duty factor of coarse adjustment.And the fine tuning module being made up of time delay chain structure
Use by the low level fine tuning dutycycle of binary system array, reach higher resolution.
The implementation of mixed type DPWM has two kinds: numerical model analysis mode and Digital Way, and the difference of the two mainly exists
Design in time delay chain.Numerical model analysis mode uses simulation time delay chain, by delay phase-locked loop (Delay Locked Loop,
DLL) delay time by each delay unit of charge and discharge control of the electric charge pump in so that the power consumption of circuit is bigger,
And DLL power up is likely to occur the situation of losing lock, analog circuit control method is easily disturbed by external environment condition, and robustness is not so good as
Digital control method is strong.Therefore, Digital Way on overall performance advantageously.
Digital dock manager (Digital Clock Manager, DCM) is integrated special in more senior FPGA product
Door is comprehensive for clock, eliminate clock skew and carry out the firmware resource of clock phase adjustment, utilize DCM complete clock multiplier,
Frequency dividing, phase shift very convenient
In patent " a kind of digital pulsewidth modulation circuit " (Patent No.: CN 102832914 A), the one proposed
In digital pulsewidth modulation circuit, it uses coarse adjustment module and fine tuning module to complete the design of digital pulse width modulator,
Wherein coarse adjustment module mainly includes enumerator and comparator, and fine tuning module includes delay chain, multiplexer and digital logic
Control module, fundamental clock signal, after coarse adjustment module coarse adjustment, is delivered to fine tuning module and is completed fine tuning, thus improve digit pulse
The modulation accuracy of width modulation circuit.But the fundamental clock frequency that the method has the disadvantage in that the method can only achieve
1MHz, along with the raising of fundamental clock frequency, the method can not meet requirement, and when fundamental clock frequency is constant, adjusts
Precision processed is relatively low.Additionally its structure composition complexity, manufacturing process is complex, and cost is the highest.
Summary of the invention
It is an object of the invention to provide a kind of high-resolution digital pulse width modulator, in Base clock resolution not
During change, frequency modulation precision is improved 32 times.
Technical scheme is as follows: a kind of digital pulse width modulator, synchronous counting module realize signal
Coarse adjustment, and export initial control signal and coarse adjustment control signal；When coarse adjustment control signal being carried out difference by digital delay module
Between time delay, improve modulation resolution, and selected termination control signal corresponding to a road by selector；Mould is produced at asynchronous signal
In block, termination control signal and initial control signal export final DPWM signal by rest-set flip-flop；Synchronous counting module
Fundamental clock signal is generated by clock generating module.
Clock generating module is made up of doubler, doubler input clock signal is carried out frequency multiplication obtain required basic time
Clock signal；
Synchronous counting module is by preloading enumerator and 2 d type flip flops form.Preload enumerator fundamental clock signal is completed accurately
Synchronous counting, high 6 dc (10:5) of input array control the periodicity of fundamental clock signal.Produce when counting starts
The pulse signal of one high level, i.e. generates initial control signal, the most again through dc(10:5) produce after individual basic clock period
A raw high level pulse signal, i.e. counting terminate to generate coarse adjustment control signal, the final coarse adjustment control signal arrived relative to
The delay time of initial control signal is dc(10:6) * T(assumes that the cycle of fundamental clock signal is T), thus realize pulsewidth
Coarse adjustment
Digital delay module is made up of 32 basic delay circuits and 1 selector；Each basic delay circuit is basic by 5 again
Delay unit cascade forms, and basic delay unit can be realized time delay merit by FPGA internal searching table (LUT, Look-up-Table)
Energy.Input signal, can the minimum delay time T/(32*5 of time delay one often through a basic delay unit) (assume Base clock
Signal period is T), after therefore continuing through 5 basic delay units, delay time is T/32, the most each basic delay circuit
Delay time is T/32, and thus 32 basic delay circuits can produce 32 road termination control signals, and the termination of adjacent two-way
The delay time of control signal differs T/32 successively, it is achieved thereby that 32 frequency dividings of fundamental clock signal, simultaneously by this manipulator
Modulation accuracy improve 32 times.Then in selector, by low 5 dc(4:0 of input array) control selector on 32 tunnels
Termination control signal selects a corresponding termination control signal in road, the final termination control signal selected relative to slightly
The delay time adjusting control signal is (dc(4:0) * T)/32.
Asynchronous signal generation module is made up of rest-set flip-flop.The effect of rest-set flip-flop is by the rising edge of initial control signal
Export required digital pulsewidth modulation (DPWM) signal after latching with termination control signal rising edge, the most initially control
The rising edge of signal is as the rising edge of DPWM signal, and the rising edge of termination control signal is as the trailing edge of DPWM signal,
Obtain the DPWM signal of a high level eventually.
The present invention, compared with traditional digital pulsewidth modulation (DPWM) device, can incite somebody to action on the premise of Base clock is constant
The resolution of manipulator improves 32 times, and has that area is little, structure is the simplest, precision high and low cost and other advantages,
Invention can realize finer resolution, and fundamental clock frequency can reach 200MHz, and not by technological temperature, voltage influence, and
And under the conditions of identical high accuracy, compared to other DPWM manipulators, there is the simplest manufacturing process.
Accompanying drawing explanation
Fig. 1 is digital pulsewidth modulation (DPWM) device population structure based on digital delay.
Fig. 2 is clock generating module.
Fig. 3 is synchronous counting module.
Fig. 4 is digital delay module.
Fig. 5 is asynchronous signal generation module.
Fig. 6 is basic delay circuit.
Fig. 7 is synchronous counting module output waveform.
Tu8Shi 32 road termination control signal waveform.
Fig. 9 is DPWM output signal schematic diagram.
Detailed description of the invention
With reference to the accompanying drawings the present invention is described in further detail.
The present invention provides a kind of high-precision digital pulse width modulator, as it is shown in figure 1, this manipulator is generated by clock
Module, synchronous counting module, digital delay module and asynchronous signal generation module composition.The circuit diagram such as figure that four modules are concrete
Shown in 2 to Fig. 5.
First 11 bit array dc(10:0 will be inputted) it is divided into high 6 dc(10:5) and low 5 dc(4:0).
In the clock generating module shown in Fig. 2, DCM × 5 are the frequency doubler of 5 times, and CLK signal is input clock letter
Number, its frequency is 50MHz.CLK clock signal, after DCM × 5 doubler spreads, obtains the Base clock that frequency is 250MHz
Signal CK, the CK signal clock cycle is T=4ns, and fundamental clock signal is sent to synchronous counting module.
In synchronous counting module as shown in Figure 3, preload enumerator and the Base clock CK signal of input counted,
Counting starts (i.e. count=0) hour counter load end output signal and will export a high level pulse through two d type flip flops
Initial control signal (as shown in Figure 7) to the SET signal end of asynchronous signal generation module.When counting completes (i.e. count=dc
(10:5), after), the coarse adjustment exporting a high level pulse is controlled letter through two d type flip flops by carry_out end output signal
Number (as shown in Figure 7) is delivered in digital delay module, i.e. coarse adjustment control signal relative to the delay time of initial control signal is
Dc(10:5) * T(assumes that the cycle of fundamental clock signal is T), so far complete the coarse adjustment of pulsewidth.
In digital delay module as shown in Figure 4, digital delay module is by 32 basic delay circuits (as shown in Figure 6)
Form with selector.Each basic delay circuit is made up of 5 basic delay units again, and wherein basic delay unit can be by searching
Table (LUT, Look-up-Table) realizes delay function, and its programming is made the input of A0, A1, A2 end is 0, and signal inputs from A3 end,
The delay time of each basic delay unit is T/ (5*32) (i.e. 0.025ns), therefore Input signal is through 5 basic time delays
The Output signal lag obtained after unit T/32 (i.e. 0.125ns), thus the delay time of each basic delay circuit is
T/32, will carry out 32 frequency dividings by delay clock substantially.Finally give CLR0, CLR1, CLR2 ... CLR31 32 tunnel terminates control
Signal processed, and the phase place of adjacent two-way termination control signal differs 11.25 ° (as shown in Figure 8) successively, it is achieved thereby that to basis
30 two divided-frequencies of clock signal, improve 32 times by the precision of this manipulator.Then by low 5 dc(4:0 in selector)
Selecting the termination control signal (as shown in Figure 9) that a road is corresponding, i.e. termination control signal is relative to the time delay of coarse adjustment control signal
Time is (dc(4:0) * T)/32, and this termination control signal is input to the RESET port of asynchronous signal generation circuit.
In asynchronous signal generation module as shown in Figure 5, the effect of rest-set flip-flop is by the rising of initial control signal
Edge and termination control signal rising edge export required digital pulsewidth modulation (DPWM) signal after latching, the most initially control
The rising edge of signal processed as the rising edge of DPWM signal, the rising edge of termination control signal as the trailing edge of DPWM signal,
Finally giving the DPWM signal (as shown in Figure 9) of a high level, the persistent period of the DPWM signal high level finally given is
(dc(10:5) * T+(dc(4:0) * T)/32), thus the modulation accuracy of this manipulator is improve 32 times.
Claims (6)
1. a digital pulse width modulator based on digital delay, it is characterised in that: include clock generating module, synchrometer
Digital-to-analogue block, digital delay module and asynchronous signal generation module；Wherein, clock generating module is produced after input clock signal frequency multiplication
Raw fundamental clock signal is input to synchronous counting module；In synchronous counting module, preload enumerator and fundamental clock signal is entered
Row counting, thus realize pulsewidth coarse adjustment, produce coarse adjustment control signal and initial control signal simultaneously, be separately input to digital delay
Module and asynchronous signal generation module；Digital delay module includes 32 basic delay circuits and 1 selector, each substantially prolongs
Time the circuit realiration identical delay time to coarse adjustment control signal, 32 basic delay circuits produce 32 tunnels and terminate controlling letter
Number, then selected termination control signal corresponding to a road by selector, this termination control signal is input to asynchronous signal and produces
Module；In asynchronous signal generation module, termination control signal and initial control signal export final number by rest-set flip-flop
Word pulse bandwidth modulation signals.
DC/DC controller based on digital delay the most according to claim 1, it is characterised in that: in digital delay module,
Digital delay module is formed by 32 basic delay circuit cascades, and each basic delay circuit is cascaded by 5 basic delay units
Forming, basic delay unit is realized delay function by FPGA internal searching table (LUT, Look-up-Table)；Input signal often warp
Cross a basic delay unit, can the minimum delay time T/(32*5 of time delay one), it is assumed that the fundamental clock signal cycle is T, because of
After this continues through 5 basic delay units, delay time is T/32, and the delay time of the most each basic delay circuit is T/32,
Thus 32 basic delay circuits are sequentially generated 32 road termination control signals, and the time delay of the termination control signal of adjacent two-way
Time differs T/32 successively, it is achieved thereby that 32 frequency dividings of fundamental clock signal, it is achieved that coarse adjustment control signal delay time
Accuracy.
Digital pulse width modulator based on time delay phase modulation circuit the most according to claim 1, it is characterised in that: counting
In word time delay module, input array low 5 dc(4:0) control selector in 32 road termination control signals, select a road therewith
Corresponding termination control signal, the termination control signal of selection is (dc(4:0) * relative to the delay time of coarse adjustment control signal
T)/32, it is achieved that the accurate time delay of coarse adjustment control signal.
Digital pulse width modulator based on time delay phase modulation circuit the most according to claim 1, it is characterised in that: synchronize
Counting module uses a preloading enumerator that fundamental clock signal completes accurate synchronous counting, by inputting the high 6 of array
Dc (10:5) controls the periodicity of fundamental clock signal；A high level pulse signal is produced, at the beginning of i.e. generating when counting starts
Beginning control signal, the most again through dc(10:5) produce a high level pulse signal after individual basic clock period, i.e. count knot
Shu Shengcheng coarse adjustment control signal, the coarse adjustment control signal finally given is dc(10 relative to the delay time of initial control signal:
6) * T, it is assumed that the cycle of fundamental clock signal is T, thus realize the coarse adjustment of pulsewidth.
Digital pulse width modulator based on IODELAY firmware the most according to claim 1, it is characterised in that: clock
Generation module is made up of doubler, and input signal is carried out frequency multiplication and obtains required fundamental clock signal by doubler, it is achieved input
The accurate frequency multiplication of clock signal.
Digital pulse width modulator based on time delay phase modulation circuit the most according to claim 1, it is characterised in that: asynchronous
Signal generator module is made up of rest-set flip-flop, and rest-set flip-flop is by the rising edge of initial control signal and termination control signal rising edge
The rising edge of required digital Pulse Wide Modulator, i.e. initial control signal is exported as DPWM signal after latching
Rising edge, the rising edge of termination control signal, as the trailing edge of DPWM signal, finally gives the DPWM signal of a high level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610602607.6A CN106230408A (en) | 2016-07-27 | 2016-07-27 | Digital pulse width modulator based on digital delay |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610602607.6A CN106230408A (en) | 2016-07-27 | 2016-07-27 | Digital pulse width modulator based on digital delay |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106230408A true CN106230408A (en) | 2016-12-14 |
Family
ID=57534556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610602607.6A Pending CN106230408A (en) | 2016-07-27 | 2016-07-27 | Digital pulse width modulator based on digital delay |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106230408A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108183701A (en) * | 2017-12-28 | 2018-06-19 | 南京理工大学 | DPWM generators based on firmware |
| CN109660302A (en) * | 2018-12-05 | 2019-04-19 | 中国人民解放军国防科技大学 | Radio frequency pulse width modulator based on digital delay line unit and modulation method |
| CN109932995A (en) * | 2017-12-18 | 2019-06-25 | 鸿富锦精密电子(天津)有限公司 | Electronic device |
| CN112305487A (en) * | 2020-09-21 | 2021-02-02 | 中国南方电网有限责任公司超高压输电公司检修试验中心 | Laboratory error calibration system and method for digital direct current electric energy meter |
| CN112362928A (en) * | 2020-09-16 | 2021-02-12 | 天津大学 | High-precision programmable pulse generation system and method capable of realizing synchronous measurement |
| CN114283857A (en) * | 2021-12-16 | 2022-04-05 | 上海艾为电子技术股份有限公司 | Delay compensation of frequency division signal, frequency division method, system and frequency divider |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064805A (en) * | 2010-12-24 | 2011-05-18 | 东南大学 | High-speed low-consumption digital pulse width modulator used in output-adjustable numerical control power supply |
| US20160118967A1 (en) * | 2013-06-28 | 2016-04-28 | Intel Corporation | Pulse width modulator for high speed digitally controlled voltage regulator |
-
2016
- 2016-07-27 CN CN201610602607.6A patent/CN106230408A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064805A (en) * | 2010-12-24 | 2011-05-18 | 东南大学 | High-speed low-consumption digital pulse width modulator used in output-adjustable numerical control power supply |
| US20160118967A1 (en) * | 2013-06-28 | 2016-04-28 | Intel Corporation | Pulse width modulator for high speed digitally controlled voltage regulator |
Non-Patent Citations (1)
| Title |
|---|
| 曾令勇: "高精度脉冲产生模块设计与实现", 《中国优秀硕士论文全文数据库》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109932995A (en) * | 2017-12-18 | 2019-06-25 | 鸿富锦精密电子(天津)有限公司 | Electronic device |
| CN109932995B (en) * | 2017-12-18 | 2021-06-15 | 鸿富锦精密电子(天津)有限公司 | Electronic device |
| CN108183701A (en) * | 2017-12-28 | 2018-06-19 | 南京理工大学 | DPWM generators based on firmware |
| CN109660302A (en) * | 2018-12-05 | 2019-04-19 | 中国人民解放军国防科技大学 | Radio frequency pulse width modulator based on digital delay line unit and modulation method |
| CN109660302B (en) * | 2018-12-05 | 2021-08-03 | 中国人民解放军国防科技大学 | Radio frequency pulse width modulator based on digital delay line unit and modulation method |
| CN112362928A (en) * | 2020-09-16 | 2021-02-12 | 天津大学 | High-precision programmable pulse generation system and method capable of realizing synchronous measurement |
| CN112305487A (en) * | 2020-09-21 | 2021-02-02 | 中国南方电网有限责任公司超高压输电公司检修试验中心 | Laboratory error calibration system and method for digital direct current electric energy meter |
| CN114283857A (en) * | 2021-12-16 | 2022-04-05 | 上海艾为电子技术股份有限公司 | Delay compensation of frequency division signal, frequency division method, system and frequency divider |
| CN114283857B (en) * | 2021-12-16 | 2024-05-28 | 上海艾为电子技术股份有限公司 | Delay compensation of frequency division signal, frequency division method, system and frequency divider |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106230408A (en) | Digital pulse width modulator based on digital delay | |
| CN106209038A (en) | Digital pulse width modulator based on IODELAY firmware | |
| KR101972661B1 (en) | Method and apparatus for clock frequency multiplier | |
| CN106301301A (en) | Digital pulse width modulator based on time delay phase modulation | |
| CN101242184B (en) | Digital delay line based frequency synthesizer and related method | |
| CN102158208B (en) | Whole-course adjustable digital pulse width modulator based on oscillation ring circuit | |
| CN105577142A (en) | Clock duty cycle adjusting device and method | |
| CN103684465A (en) | Multiphase clock generating circuit for asynchronous successive approximation analog/digital converter | |
| CN107222189A (en) | A kind of digital pulse width modulator | |
| CN106452052A (en) | DC/DC control circuit based on DCM modulation | |
| CN106208676A (en) | DC/DC controller based on time delay phase modulation circuit | |
| CN102394643A (en) | Digital pulse width modulator based on digital delayed-locked loop (DLL) | |
| CN101409553A (en) | Phase delay line structure | |
| CN106209037A (en) | Digital pulse width modulator based on DCM modulation | |
| CN104378089B (en) | Digital pulse width generator and generating method thereof | |
| CN112104342B (en) | High-precision digital pulse width modulator composed of counter and fast and slow delay chain | |
| CN103427798A (en) | Multiphase clock generation circuit | |
| CN110838845A (en) | TDC based on multiphase ring oscillator and annular pulse contraction delay chain | |
| US9602115B1 (en) | Method and apparatus for multi-rate clock generation | |
| CN106208675B (en) | DC/DC controller based on digital delay circuit | |
| CN106712490A (en) | DC/DC control circuit based on IODELAY firmware | |
| US20210242862A1 (en) | Systems and Methods for Generating a Controllable-Width Pulse Signal | |
| CN103956996A (en) | High-resolution digital pulse width modulator based on double-frequency and multi-phase clock | |
| CN202364200U (en) | Digital pulse width modulator based on digital delay phase-locked loop | |
| Shen et al. | Hybrid DPWM with analog delay locked loop |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161214 |
|
| RJ01 | Rejection of invention patent application after publication |