CN111555738A - Ultra-low power consumption pulse width modulation coding chip - Google Patents
Ultra-low power consumption pulse width modulation coding chip Download PDFInfo
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- CN111555738A CN111555738A CN202010476556.3A CN202010476556A CN111555738A CN 111555738 A CN111555738 A CN 111555738A CN 202010476556 A CN202010476556 A CN 202010476556A CN 111555738 A CN111555738 A CN 111555738A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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Abstract
The invention discloses a pulse width modulation coding chip with ultra-low power consumption, belonging to the technical field of chips, comprising two independent gate circuit counters, a 32KHz low-frequency counter and an integrated circuit; in the calibration mode of the gate circuit counter, the falling edge of a low-frequency pulse of 32KHz is used for exciting the gate circuit counter to start, the falling edge of the next pulse triggers the gate circuit counter to stop, the time delay of each gate circuit can be calculated by the value of the gate circuit counter and the pulse width of 32KHz, and then the preset value of the gate circuit is corrected according to the time delay; in the working mode, the initial state of level output needs to be set firstly, the initial state comprises four states, and low-power-consumption pulse output is realized based on gate circuit counting; 4-state output of high level, low level, high resistance and grounding can realize complex coding, low power consumption, strong driving output, a vibration elimination circuit and the like; the pulse phase and the pulse frequency can be edited.
Description
Technical Field
The invention relates to the technical field of chips, in particular to an ultra-low power consumption pulse width modulation coding chip.
Background
The coded modulation technique is a technique that has been developed in recent years and comprehensively designs coding and modulation as a whole. Through the research on the code modulation system, a novel code modulation system with higher information transmission rate and stronger anti-noise performance is designed.
Satellite communication has become an important means for international and domestic telecommunications due to its large coverage area, large channel capacity, multiple access, and other advantages.
The existing code modulation chip has high power consumption, is difficult to realize low power consumption, strong drive output, a vibration elimination circuit and the like, has pulse phase and pulse frequency which are difficult to edit, is inconvenient to operate, and influences the use effect.
Disclosure of Invention
The invention aims to provide an ultra-low power consumption pulse width modulation coding chip to solve the problems that the existing coding modulation chip in the background art is high in power consumption, low in power consumption and difficult to realize, strong in driving output, a vibration eliminating circuit and the like, pulse phases and pulse frequencies are not easy to edit, operation is inconvenient, and the using effect is influenced.
In order to achieve the purpose, the invention provides the following technical scheme: an ultra-low power consumption pulse width modulation coding chip comprises two independent gate circuit counters, a 32KHz low-frequency counter and an integrated circuit;
in the calibration mode of the gate circuit counter, the falling edge of a low-frequency pulse of 32KHz is used for exciting the gate circuit counter to start, the falling edge of the next pulse triggers the gate circuit counter to stop, the time delay of each gate circuit can be calculated by the value of the gate circuit counter and the pulse width of 32KHz, and then the preset value of the gate circuit is corrected according to the time delay;
in the working mode, the initial state of level output needs to be set firstly, the initial state comprises four states, the number of pulse output is set again, the maximum setting value is 32, the time value of each pulse section is prefabricated (the time value of less than 32.768KHz pulse width (30uS) is completely completed by a gate circuit, the time value of more than 30uS is completed by counting +32.768KHz pulses), the state of each pulse time period is preset at the same time, the length of each pulse prefabricated time value is that the minimum resolution is between 22nS and 8mS, and after the time of each pulse overflows, the level state is decoded by a decoder to output push-pull output, so that the push-pull pulse output is realized;
the time value of each pulse is composed of the time delays of N gate circuits, and after each calibration, the module refreshes the actual time delay number of the gate circuits;
the push-pull output has four states:
the high level is that the left upper bridge arm is connected, the left lower bridge arm end is disconnected, the right upper bridge arm is disconnected, and the right lower bridge arm is connected;
the low level is that the left upper bridge arm is disconnected, the left lower bridge arm end is conducted, the right upper bridge arm is conducted, and the right lower bridge arm section is connected;
the high resistance means that the left upper bridge arm is disconnected, the left lower bridge arm end is disconnected, the right upper bridge arm is disconnected, and the right lower bridge arm is disconnected;
and the grounding is that the left upper bridge arm is disconnected, the left lower bridge arm end is connected, the right upper bridge arm is disconnected, the right lower bridge arm is connected, and the complex coding is realized through four states.
Compared with the prior art, the invention has the beneficial effects that:
1) based on gate circuit counting, low-power consumption pulse output is realized;
2) 4-state output of high level, low level, high resistance and grounding can realize complex coding, low power consumption, strong driving output, a vibration elimination circuit and the like;
3) the pulse phase can be edited, and the pulse frequency can be edited.
Drawings
FIG. 1 is a schematic diagram of a calibration mode of the present invention;
fig. 2 is a schematic diagram of the working mode of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
Example (b):
referring to fig. 1-2, the present invention provides a technical solution: an ultra-low power consumption pulse width modulation coding chip comprises two independent gate circuit counters, a 32KHz low-frequency counter and an integrated circuit to realize the control of pulse output, and an ultrasonic sensor or a laser sensor is driven by the pulse;
referring to fig. 1, in the calibration mode of the gate circuit counter, a falling edge of a low-frequency pulse of 32KHz is used to excite the gate circuit counter to start, a falling edge of a next pulse triggers the gate circuit counter to stop, the time delay of each gate circuit can be calculated according to the value of the gate circuit counter and the pulse width of 32KHz, and then the preset value of the gate circuit is corrected according to the time delay;
referring to fig. 2, in a working mode, an initial state of level output needs to be set first, the initial state includes four states, the number of pulse outputs is set, the maximum setting value is 32, a time value of each pulse segment is prefabricated, a state of each pulse time period is preset, the length of each pulse prefabricated time value is that the minimum resolution is between 22nS and 8mS, and after the time of each pulse overflows, the level state is decoded and output by a decoder to output push-pull output, so that push-pull pulse output is realized;
the time value of each pulse is composed of the time delays of N gate circuits, and after each calibration, the module refreshes the actual time delay number of the gate circuits;
the push-pull output has four states:
the high level is that the left upper bridge arm is connected, the left lower bridge arm end is disconnected, the right upper bridge arm is disconnected, and the right lower bridge arm is connected;
the low level is that the left upper bridge arm is disconnected, the left lower bridge arm end is conducted, the right upper bridge arm is conducted, and the right lower bridge arm section is connected;
the high resistance means that the left upper bridge arm is disconnected, the left lower bridge arm end is disconnected, the right upper bridge arm is disconnected, and the right lower bridge arm is disconnected;
and the grounding is that the left upper bridge arm is disconnected, the left lower bridge arm end is connected, the right upper bridge arm is disconnected, the right lower bridge arm is connected, and the complex coding is realized through four states.
32 pulses, which can be set according to the completion phase, if each pulse time is a 90 item, the total number of pulses set is reduced.
Based on gate circuit counting, low-power consumption pulse output is realized; 4-state output of high level, low level, high resistance and grounding can realize complex coding, low power consumption, strong driving output, a vibration elimination circuit and the like; the pulse phase and frequency can be edited
While there have been shown and described the fundamental principles and essential features of the invention and advantages thereof, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing exemplary embodiments, but is capable of other specific forms without departing from the spirit or essential characteristics thereof; the present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein, and any reference signs in the claims are not intended to be construed as limiting the claim concerned.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (1)
1. An ultra-low power consumption pulse width modulation coding chip, characterized in that: the ultra-low power consumption pulse width modulation coding chip comprises two independent gate circuit counters, a 32KHz low-frequency counter and a comprehensive circuit;
in the calibration mode of the gate circuit counter, the falling edge of a low-frequency pulse of 32KHz is used for exciting the gate circuit counter to start, the falling edge of the next pulse triggers the gate circuit counter to stop, the time delay of each gate circuit can be calculated by the value of the gate circuit counter and the pulse width of 32KHz, and then the preset value of the gate circuit is corrected according to the time delay;
under the working mode, the initial state of level output needs to be set firstly, the initial state comprises four states, the number of pulse output is set again, the maximum setting value is 32, the time value of each pulse segment is prefabricated, the state of each pulse time period is preset at the same time, the length of each pulse prefabricated time value is that the minimum resolution ratio is between 22nS and 30uS, the pulse exceeding 30uS needs to be formed by counting the gate circuit plus the complete pulse number of 32.768KHz plus the counting of the gate circuit, the maximum pulse width can reach 8ms, and after the time of each pulse overflows, the level state is decoded by a decoder to output push-pull output, so that the push-pull pulse output is realized;
the time value of each pulse is composed of the time delays of N gate circuits, and after each calibration, the module refreshes the actual time delay number of the gate circuits;
the push-pull output has four states:
the high level is that the left upper bridge arm is connected, the left lower bridge arm end is disconnected, the right upper bridge arm is disconnected, and the right lower bridge arm is connected;
the low level is that the left upper bridge arm is disconnected, the left lower bridge arm end is conducted, the right upper bridge arm is conducted, and the right lower bridge arm section is connected;
the high resistance means that the left upper bridge arm is disconnected, the left lower bridge arm end is disconnected, the right upper bridge arm is disconnected, and the right lower bridge arm is disconnected;
and the grounding is that the left upper bridge arm is disconnected, the left lower bridge arm end is connected, the right upper bridge arm is disconnected, the right lower bridge arm is connected, and the complex coding is realized through four states.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010476556.3A CN111555738B (en) | 2020-05-29 | 2020-05-29 | Ultra-low power consumption pulse width modulation coding chip |
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| CN202010476556.3A CN111555738B (en) | 2020-05-29 | 2020-05-29 | Ultra-low power consumption pulse width modulation coding chip |
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| CN111555738B CN111555738B (en) | 2021-05-28 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201956987U (en) * | 2010-12-24 | 2011-08-31 | 东南大学 | High-speed and low-consumption DPWM used in adjustable output NC power supply |
| CN102832914A (en) * | 2012-09-17 | 2012-12-19 | 电子科技大学 | Digital pulse width modulator circuit |
| CN103956996A (en) * | 2014-04-29 | 2014-07-30 | 西北工业大学 | High-resolution digital pulse width modulator based on double-frequency and multi-phase clock |
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2020
- 2020-05-29 CN CN202010476556.3A patent/CN111555738B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201956987U (en) * | 2010-12-24 | 2011-08-31 | 东南大学 | High-speed and low-consumption DPWM used in adjustable output NC power supply |
| CN102832914A (en) * | 2012-09-17 | 2012-12-19 | 电子科技大学 | Digital pulse width modulator circuit |
| CN103956996A (en) * | 2014-04-29 | 2014-07-30 | 西北工业大学 | High-resolution digital pulse width modulator based on double-frequency and multi-phase clock |
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Address after: Room 107, building 15, 396 Guilin road, Xuhui District, Shanghai 200030 Patentee after: Shanghai Zhonghe Weisi Instrument Co.,Ltd. Address before: Room 107, building 15, 396 Guilin road, Xuhui District, Shanghai 200030 Patentee before: SHANGHAI CHINA NUCLEAR WEISI INSTRUMENT Co.,Ltd. |
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