CN201359612Y

CN201359612Y - Wafer test carrier

Info

Publication number: CN201359612Y
Application number: CN 200920104868
Authority: CN
Inventors: 胡德良; 薛毓虎; 周云青; 张正栋
Original assignee: JIANGYIN AIDUO PV TECHNOLOGY Co Ltd
Current assignee: JIANGYIN AIDUO PV TECHNOLOGY Co Ltd
Priority date: 2009-01-09
Filing date: 2009-01-09
Publication date: 2009-12-09
Anticipated expiration: 2019-01-09

Abstract

Disclosed is a wafer test carrier, which at least comprises a base, a base frame and an upper cover, wherein the central part of the base is provided with a space; the side edge of the space is at least provided with a positioning concave groove; the base frame is sleeved at the side edge of the space arranged at the central part of the base; the side edge of the base frame is at least provided with a positioning convex groove so as to connect the positioning concave groove; at least one side edge at the bottom of the base frame is extended with a base plate towards the central part; and the upper cover is covered at the upper end of the base. As the extension degree of the base plate from the side edge of the bottom of the base frame is different, test wafers with different sizes can be carried; meanwhile, according to different sizes of the common test wafers, a plurality of same base frames can be designed, wherein each base frame is provided with the base plate with different extension degrees, so as to be beneficial for convenient replacement of the wafer test carrier structure and achieve the effect that each pin of the wafer to be tested can be easily electrically connected with each pin of a test circuit board below a contact panel through a soft and conductive contact panel.

Description

Carrier for testing chip

Technical field

The utility model relates to a kind of carrier for testing chip.

Background technology

As depicted in figs. 1 and 2, conventional wafer test carrier structure 100 is to comprise a loam cake 101, a pedestal 102, several probes 103 at least.Loam cake 101 is to be articulated in pedestal 102.The pin 105 of 103 correspondence wafers 104 to be measured of several probes accurately inserts on the base plate 106 of pedestal 102.When loam cake 101 pressings, wafer 104 to be measured is to snap in pedestal 102 special custom-made by size to meet in the middle of the draw-in groove 109 of wafer 104 to be measured, to avoid rocking of wafer 104 to be measured.In addition, base plate 106 on pedestal 102 also need be complied with the spacing or pin 105 quantity of each pin 105 of wafer 104 to be measured, special its corresponding jack of custom-made by size is so that each pin 105 of wafer to be measured 104 also needs precisely to contact each probe 103 on the base plate 106 that inserts in pedestal 102.Moreover, place pedestal 102 times by a testing circuit board 107, by the pin 108 on several probe 103 engaged test circuit boards 107 under the base plate 106 of pedestal 102, finish the functional test of each pin 105 of wafer 104 to be measured again by testing circuit board 107.

In above-mentioned carrier for testing chip structure 100, the size change or the change of pin 105 spacings of wafer to be measured 104 or pin 105 quantity along with wafer 104 to be measured, in the prior art, also promptly change or the change of pin 105 spacings of wafer to be measured 104 or pin 105 quantity comes in addition custom-made by size with the size of its wafer 104 to be measured, wafer sort with satisfied correspondence is required, thereby causes the waste of cost and resource.

The utility model content

The utility model is intended to provide a kind of carrier for testing chip, and it has the wafer to be measured that is applicable to the virtually any size size, and is applicable to the pin spacing of wafer to be measured of virtually any size size or the change of pin count.

Technical solution adopted in the utility model is: a kind of carrier for testing chip is characterized in that: it includes a pedestal, and this pedestal centre is offered a space, and this space side is provided with a location groove at least; One pedestal, it is placed in the side that described pedestal centre is offered the space, and the side of this pedestal is provided with a location tongue at least, and being connected in described detent, this at least one side in pedestal bottom extends a substrate to centre; And a loam cake, be covered on the upper end of this pedestal.

Further feature of the present utility model also is: it also comprises a base plate, and it is located at the lower end of pedestal, and these base plate central authorities also establish an opening.

It also comprises one and has touch panel soft and conduction, is covered on this opening by the lower end of this base plate.

It also comprises a T type cage knob, and its upper end by this loam cake is through to the lower end of this loam cake, and connects a main pressing plate in the lower end of this loam cake.

It also comprises an auxiliary pressing plate, and it is located at this main pressing plate and this pedestal upper end, with the wafer of pressing one test.

Advantage of the present utility model and beneficial effect are, because the degree difference of the pedestal bottom substrate that side extended, thereby can carrier the testing wafer of different size dimensions, simultaneously, also according to the size difference of using testing wafer always, design several identical pedestals, and each pedestal gives the substrate of extension in various degree, replace in order to the carrier for testing chip structure is convenient; The utility model is given up the base plate on the pedestal in the prior art by above technical scheme need give up each probe on the base plate that inserts in pedestal one by one simultaneously according to the spacing of each pin of wafer to be measured or pin count the institute jack of custom-made by size especially; And the lower end of adopting a touch panel soft and conduction to be located at the base plate in the utility model is covered on opening, because the surface of the touch panel of this soft and conduction all electrically connects point with several up and down, therefore, having reached each pin of wafer to be measured can be soft thus easily and the touch panel of conduction, is electrically connected at the effect of each pin of the testing circuit board under the touch panel.

Further specify the utility model below in conjunction with drawings and Examples.

Description of drawings

Fig. 1 is the stereographic map of carrier for testing chip structure of the prior art;

Fig. 2 is the synoptic diagram of carrier for testing chip structure of the prior art;

Fig. 3 is a system diagram of the present utility model;

Fig. 4 is a constitutional diagram of the present utility model.

Embodiment

Below in conjunction with drawings and Examples, embodiment of the present utility model is further described.Following examples only are used for the technical solution of the utility model more clearly is described, and can not limit protection domain of the present utility model with this.

See also Fig. 3 and shown in Figure 4, the utility model comprises one at least and has the touch panel 201, a base plate 202, a pedestal 203, a pedestal 204 of soft and conduction, auxiliary pressing plate 205, an and loam cake 206.Loam cake 206 is the catching grooves 217 that are buckled in pedestal 203 both sides correspondences by the bolt button 216 of both sides, to use the upper end that closely covers pedestal 203, in addition be through to behind the lower end of loam cake 206 by the upper end of loam cake 206 and connect a main pressing plate 215 by a T type cage knob 207, therefore, to press as shown in fig. 1 testing wafer 104 in the middle of pedestal 204 and pedestal 203.The centre of pedestal 203 is then offered a space 208, and the side 209 in this space 208 is provided with a location groove 210 at least.204 of pedestals are placed in the side 209 in this space 208, and the side 211 of this pedestal 204 is provided with a location tongue 212 at least, to be connected in above-mentioned detent 210, in addition, at least one side in pedestal 204 bottoms extends a substrate 213 to centre, the extension degree difference of substrate 213 thus is with the testing wafer 104 of the different size dimensions of carrier.In other words, when substrate 213 extension degree are big more, then the space 208 of pedestal 203 centre is more little, also is that wafer 104 volumes tested are more little.202 of base plates are located under the pedestal 203 end, and base plate 202 central authorities also establish an opening, the touch panel 201 of soft and conduction, and then the lower end by base plate 202 is covered on opening.Auxiliary pressing plate 205 then can be located at main pressing plate 215 and pedestal 204 upper ends, to strengthen its testing wafer 104 of pressing again.

The above only is a preferred implementation of the present utility model; should be understood that; for those skilled in the art; under the prerequisite that does not break away from the utility model know-why; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.

Claims

1, a kind of carrier for testing chip is characterized in that: it includes a pedestal (203), and this pedestal (203) centre is offered a space (208), and this space (208) side (209) is provided with a location groove (210) at least; One pedestal (204), it is placed in the side (209) in the space (208) that described pedestal (203) centre offers, and the side (211) of this pedestal (204) is provided with a location tongue (212) at least, be connected in described detent (210), at least one side in this pedestal (204) bottom extends a substrate (213) to centre; And a loam cake (206), be covered on the upper end of this pedestal (203).

2, carrier for testing chip as claimed in claim 1 is characterized in that, it also comprises the lower end that a base plate (202) is located at pedestal (203), and this base plate (202) central authorities also establish an opening.

3, carrier for testing chip as claimed in claim 2 is characterized in that, it also comprises a touch panel (201) soft and conduction and is covered on this opening by the lower end of this base plate (202).

4, carrier for testing chip as claimed in claim 1 is characterized in that, it also comprises a T type cage knob (207) and is through to the lower end of this loam cake (206) by the upper end of this loam cake (206), and connects a main pressing plate (215) in the lower end of this loam cake (206).

5, carrier for testing chip as claimed in claim 4 is characterized in that, it also comprises an auxiliary pressing plate (205), and it is located at main pressing plate (215) and pedestal (204) upper end.