CN205595310U - Semiconductor device is with test seat - Google Patents
Semiconductor device is with test seat Download PDFInfo
- Publication number
- CN205595310U CN205595310U CN201521097715.XU CN201521097715U CN205595310U CN 205595310 U CN205595310 U CN 205595310U CN 201521097715 U CN201521097715 U CN 201521097715U CN 205595310 U CN205595310 U CN 205595310U
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- test
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- sheet
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- 238000012360 testing method Methods 0.000 title claims abstract description 149
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 5
- 238000001514 detection method Methods 0.000 abstract description 6
- 230000005611 electricity Effects 0.000 abstract 1
- 230000002349 favourable effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
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- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The utility model discloses a semiconductor device is with test seat, include: PCB base plate, at least a set of left side test group piece, at least a set of right side test group piece, left mount pad and right mount pad, left side test group piece, right side test group piece are constituteed by first test piece, the second test piece of parallel and vertical setting, and have the insulating layer between the first test piece, second test piece, and this is first tests piece, second test piece by central section, the first pin that is located central section both ends, second pin with be located the third pin constitution of central section lower extreme, the third pin of first test piece and the third pin of second test piece are symmetry setting in left side test group piece, the right side test group piece. The utility model discloses electricity performance detection device has strengthened the pin of test group piece and semiconductor chip to be tested's contact pressure, is favorable to improving the pin of test group piece and the reliability of semiconductor chip to be tested electrical contact, has also improved life.
Description
Technical field
This utility model relates to a kind of electric property detection device, particularly relates to a kind of semiconductor device test bench.
Background technology
In research and development, large-scale production and the Product checking of semiconductor chip, being required to test all kinds of performances of chip, chip test base is the critical component in test device.The function of test bench is that its function quality directly affects reliability and the accuracy of chip testing by electric signal and the transmission of electric current between chip positioning clamping and wiring board.Along with the speed of service of chip improves and the minimizing of electronic product size day by day, the requirement to electric property detection device performance improves the most day by day.Therefore, how to design a kind of more superior electric property detection device, become the direction that those skilled in the art make great efforts.
Summary of the invention
This utility model provides a kind of semiconductor device test bench, this semiconductor device test bench enhances the pin of test pack and the footprint pressure of semiconductor chip to be measured, be conducive to the pin improving test pack and the reliability of semiconductor chip to be measured electrical contact, also improve service life.
For reaching above-mentioned purpose, the technical solution adopted in the utility model is: a kind of semiconductor device test bench, including: test on the left of PCB substrate, least one set and on the right side of pack, least one set, test pack, left mounting seat and right mounting seat, described left side test pack, right side test pack are flush-mounted in left mounting seat and right mounting seat respectively, and one for placing the object stage of chip to be measured between left mounting seat and right mounting seat；
Described left side test pack, test pack in right side is by the first test sheet that is parallel and that be vertically arranged, second test sheet composition, and first test sheet, between second test sheet, there is insulating barrier, this the first test sheet, second test sheet is by central authorities section, first pin at two ends, centrally located section, second pin and the 3rd pin composition of lower end, centrally located section, described first test sheet, second test respective 3rd pin of sheet is for electrically connecting with PCB substrate, described first test sheet, second test respective first pin of sheet, second pin is for electrically connecting with chip to be measured；In described left side test pack, right side test pack, the 3rd pin of the first test sheet and the 3rd pin of the second test sheet are symmetrical set；Described first test sheet, second test the first pin of sheet, the second pin are symmetrical set.
Technique scheme is further improved technical scheme as follows:
1. in such scheme, described object stage includes lifting steady arm and spring, and this lifting steady arm embeds in object stage, and lifting steady arm is set with described spring.
2., in such scheme, also include that left cover and right cover plate, this left cover and right cover plate are respectively arranged in left mounting seat and right mounting seat.
4., in such scheme, described left cover and right cover plate all have venthole towards the end of object stage.
Owing to technique scheme is used, this utility model compared with prior art has the advantage that
1. this utility model semiconductor device test bench, which increase the pin of test pack and the footprint pressure of semiconductor chip to be measured, be conducive to the reliability of pin and the semiconductor chip to be measured electrical contact improving test pack, and the 3rd pin of the first test sheet and the 3rd pin of the second test sheet are symmetrical set in left side test pack, right side test pack, first test sheet, second test the first pin of sheet, the second pin are symmetrical set, and also improve service life；Secondly, its left cover and right cover plate all have venthole towards the end of object stage, can effectively eliminate pin and the dust of semiconductor chip to be measured of test pack, improve electrical contact environment so that the pin of test pack is more preferable with what semiconductor chip to be measured contacted.
2. this utility model semiconductor device test bench, its chip to be measured is positioned over lifting steady arm upper surface, and under the pressure of depression bar, chip to be measured can move up and down, self-adaptative adjustment and the pressure of pin, thus improves accuracy of detection and reliability.
Accompanying drawing explanation
Accompanying drawing 1 is this utility model semiconductor device test bench structural representation；
Accompanying drawing 2 is this utility model semiconductor device test bench partial structurtes schematic diagram；
Accompanying drawing 3 is the partial structurtes schematic diagram of accompanying drawing 2；
Accompanying drawing 4 tests pack structural representation for this utility model；
Accompanying drawing 5 is partial structurtes schematic diagram at the A of accompanying drawing 4；
Accompanying drawing 6 is this utility model test bench partial structurtes schematic diagram.
In the figures above: 1, PCB substrate；2, left side test pack；3, right side test pack；4, left mounting seat；5, right mounting seat；6, object stage；7, the first test sheet；8, the second test sheet；9, insulating barrier；101, central authorities section；102, the first pin；103, the second pin；104, the 3rd pin；11, left cover；12, right cover plate；13, venthole；14, depression bar；15, lifting steady arm；16, spring.
Detailed description of the invention
Below in conjunction with the accompanying drawings and this utility model is further described by embodiment:
Embodiment 1: a kind of semiconductor device test bench, including: test on the left of PCB substrate 1, least one set and on the right side of pack 2, least one set, test pack 3, left mounting seat 4 and right mounting seat 5, described left side test pack 2, right side test pack 3 are flush-mounted in left mounting seat 4 and right mounting seat 5 respectively, and one for placing the object stage 6 of chip to be measured between left mounting seat 4 and right mounting seat 5；
Described left side test pack 2, test pack 3 in right side is by the first test sheet 7 that is parallel and that be vertically arranged, second test sheet 8 forms, and first test sheet 7, between second test sheet 8, there is insulating barrier 9, this the first test sheet 7, second test sheet 8 is by central authorities section 101, first pin 102 at two ends, centrally located section 101, 3rd pin 104 of the second pin 103 and lower end, centrally located section 101 forms, described first test sheet 7, second respective 3rd pin 104 of test sheet 8 is for electrically connecting with PCB substrate 1, described first test sheet 7, second test respective first pin 102 of sheet 8, second pin 103 is for electrically connecting with chip to be measured；In described left side test pack 2, right side test pack 3, the 3rd pin 104 of the first test sheet 7 and the 3rd pin 104 of the second test sheet 8 are symmetrical set；First pin the 102, second pin 103 that described first test sheet 7, second tests sheet 8 is symmetrical set.
Above-mentioned object stage 6 includes lifting steady arm 15 and spring 16, and this lifting steady arm 15 embeds in object stage 6, and lifting steady arm 15 is set with described spring 16.
Embodiment 2: a kind of semiconductor device test bench, including: test on the left of PCB substrate 1, least one set and on the right side of pack 2, least one set, test pack 3, left mounting seat 4 and right mounting seat 5, described left side test pack 2, right side test pack 3 are flush-mounted in left mounting seat 4 and right mounting seat 5 respectively, and one for placing the object stage 6 of chip to be measured between left mounting seat 4 and right mounting seat 5；
Described left side test pack 2, test pack 3 in right side is by the first test sheet 7 that is parallel and that be vertically arranged, second test sheet 8 forms, and first test sheet 7, between second test sheet 8, there is insulating barrier 9, this the first test sheet 7, second test sheet 8 is by central authorities section 101, first pin 102 at two ends, centrally located section 101, 3rd pin 104 of the second pin 103 and lower end, centrally located section 101 forms, described first test sheet 7, second respective 3rd pin 104 of test sheet 8 is for electrically connecting with PCB substrate 1, described first test sheet 7, second test respective first pin 102 of sheet 8, second pin 103 is for electrically connecting with chip to be measured；In described left side test pack 2, right side test pack 3, the 3rd pin 104 of the first test sheet 7 and the 3rd pin 104 of the second test sheet 8 are symmetrical set；First pin the 102, second pin 103 that described first test sheet 7, second tests sheet 8 is symmetrical set.
Also including left cover 11 and right cover plate 12, this left cover 11 and right cover plate 12 are respectively arranged in left mounting seat 4 and right mounting seat 5.
Above-mentioned left cover 11 and right cover plate 12 all have venthole 13 towards the end of object stage 6.
When using above-mentioned semiconductor device test bench, which increase the pin of test pack and the footprint pressure of semiconductor chip to be measured, be conducive to the pin improving test pack and the reliability of semiconductor chip to be measured electrical contact, also improve service life；Secondly, its left cover and right cover plate all have venthole towards the end of object stage, effectively eliminate pin and the dust of semiconductor chip to be measured of test pack, improve electrical contact environment so that the pin of test pack is more preferable with what semiconductor chip to be measured contacted；Again, its chip to be measured is positioned over lifting steady arm upper surface, and chip to be measured can move up and down, self-adaptative adjustment and the pressure of pin, thus improves accuracy of detection and reliability.
Above-described embodiment only for technology of the present utility model design and feature are described, its object is to allow person skilled in the art will appreciate that content of the present utility model and to implement according to this, can not limit protection domain of the present utility model with this.All equivalence changes made according to this utility model spirit or modification, all should contain within protection domain of the present utility model.
Claims (4)
1. a semiconductor device test bench, it is characterized in that: including: test on the left of PCB substrate (1), least one set and on the right side of pack (2), least one set, test pack (3), left mounting seat (4) and right mounting seat (5), described left side test pack (2), right side test pack (3) are flush-mounted in left mounting seat (4) and right mounting seat (5) respectively, and one is positioned between left mounting seat (4) and right mounting seat (5) for placing the object stage (6) of chip to be measured；
nullDescribed left side test pack (2)、Right side test pack (3) is by the first test sheet (7) that is parallel and that be vertically arranged、Second test sheet (8) composition，And first test sheet (7)、Between second test sheet (8), there is insulating barrier (9)，This first test sheet (7)、Second test sheet (8) is by central authorities section (101)、First pin (102) at centrally located section (101) two ends、Second pin (103) and the 3rd pin (104) composition of centrally located section (101) lower end，Described first test sheet (7)、Second test sheet (8) respective 3rd pin (104) is for electrically connecting with PCB substrate (1)，Described first test sheet (7)、Second test sheet (8) respective first pin (102)、Second pin (103) is for electrically connecting with chip to be measured；In described left side test pack (2), right side test pack (3), the 3rd pin (104) of the first test sheet (7) and the 3rd pin (104) of the second test sheet (8) are symmetrical set；Described first test sheet (7), first pin (102) of the second test sheet (8), the second pin (103) are symmetrical set.
Semiconductor device test bench the most according to claim 1, it is characterized in that: described object stage (6) includes lifting steady arm (15) and spring (16), this lifting steady arm (15) embeds in object stage (6), and lifting steady arm (15) is set with described spring (16).
Semiconductor device test bench the most according to claim 1, it is characterised in that: also include that left cover (11) and right cover plate (12), this left cover (11) and right cover plate (12) are respectively arranged in left mounting seat (4) and right mounting seat (5).
Semiconductor device test bench the most according to claim 3, it is characterised in that: described left cover (11) and right cover plate (12) all have venthole (13) towards the end of object stage (6).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521097715.XU CN205595310U (en) | 2015-12-25 | 2015-12-25 | Semiconductor device is with test seat |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521097715.XU CN205595310U (en) | 2015-12-25 | 2015-12-25 | Semiconductor device is with test seat |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205595310U true CN205595310U (en) | 2016-09-21 |
Family
ID=56927259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201521097715.XU Expired - Fee Related CN205595310U (en) | 2015-12-25 | 2015-12-25 | Semiconductor device is with test seat |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205595310U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112485647A (en) * | 2020-12-10 | 2021-03-12 | 深圳市奥伦德元器件有限公司 | Optocoupler high-voltage testing device with loop testing function and testing method thereof |
-
2015
- 2015-12-25 CN CN201521097715.XU patent/CN205595310U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112485647A (en) * | 2020-12-10 | 2021-03-12 | 深圳市奥伦德元器件有限公司 | Optocoupler high-voltage testing device with loop testing function and testing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160921 |