CN203287491U - Device and system for testing chip - Google Patents
Device and system for testing chip Download PDFInfo
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- CN203287491U CN203287491U CN2013203498734U CN201320349873U CN203287491U CN 203287491 U CN203287491 U CN 203287491U CN 2013203498734 U CN2013203498734 U CN 2013203498734U CN 201320349873 U CN201320349873 U CN 201320349873U CN 203287491 U CN203287491 U CN 203287491U
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- chip
- conduction opening
- circuit board
- testing chip
- substrate
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Abstract
A device and a system for testing a chip are provided. The device comprises a substrate, a boss, first conductive openings, second conductive openings and test points, wherein the substrate comprises a first surface and a second surface which are oppositely arranged, the boss is arranged on the first surface of the substrate, the first conductive openings are arranged in the second surface of the substrate and are corresponding to base pins of chips to be tested, the second conductive openings are arranged in the boss and are corresponding to the first conductive openings, the second conductive openings re electrically connected with the first conductive openings, and the test points are arranged on the second surface of the substrate and are electrically connected with the first conductive openings. By using the device and the system for testing the chip, the space of a circuit board can be reduced, and the manufacturing cost of the circuit board is lowered.
Description
Technical field
The utility model relates to the chip testing field, is specifically related to a kind of apparatus for testing chip and system.
Background technology
Chip refers to include the silicon chip of integrated circuit, and volume is very little, is usually the part of computing machine or other equipment.In recent years, the application of chip increases with surprising rapidity, supports the encapsulation technology of various chips also to continue to bring out out, for example BGA Package (Ball Grid Array, BGA), the encapsulation technology of the various new such as chip size packages (Chip Size Package, CSP).
Along with the microminiaturization of chip product, the pin densities of chip is more and more higher.Most high pin chip all adopts the BGA encapsulation technology now, and it has become the optimal selection of the high density such as south/north bridge chips, high-performance, many pin package on CPU, mainboard.Chip with the encapsulation of BGA technology is called bga chip.
In prior art, circuit board when designing and producing,, in order to facilitate the parts up to specification and weldability whether on testing circuit board, can be reserved some test points usually.Such as; if the up to specification and weldability whether of the resistance on the check circuit plate; usually can additionally draw a pair of test point at the two ends of resistance; can allow the probe of test use directly contact the test point of drawing; avoid the two ends of direct contact resistance to cause damage to resistance, promoted the fiduciary level of test.
Development along with science and technology, the size of circuit board is also more and more less, especially in the time will arranging a plurality of high pin chip as bga chip on circuit board, space on circuit board just has been subject to very large challenge, all reserve test point for all pins of bga chip and will take the very large space of circuit board, greatly increase the cost of manufacture of circuit board.Traditional method is on circuit board, and the part pin of the contour pin chip of bga chip is reserved some test points.But this way of reserving test point for the part pin, also need to take the space of circuit board, and can only to the part pin of bga chip whether up to specification and weldability test, the pin of not reserving test point whether up to specification and weldability is tested, reduced the fiduciary level of test, be unfavorable for fixing a breakdown smoothly.
The utility model content
The problem that the utility model solves is in prior art, and the test problem of chip is carried out in the space that need to take circuit board.
For addressing the above problem, the utility model provides a kind of apparatus for testing chip, and described device comprises: substrate, described substrate comprise the first surface that is oppositely arranged and second; Be arranged on the boss of described substrate first surface; Be arranged on second the first upper and corresponding with chip pin to be measured conduction opening of described substrate; Be arranged on described boss and the second conduction opening corresponding with described the first conduction opening, described the second conduction opening is electrically connected to described the first conduction opening; And being arranged on test point on second of described substrate, described test point and described the first conduction opening are electrically connected to.
Optionally, described the first conduction opening and described the second conduction opening formation conductive through hole that is interconnected, described the first conduction opening and described second conduct electricity opening and are respectively the opening at described conductive through hole two ends.
Optionally, described conductive through hole inwall adheres to the layer of metal conductive layer.
Optionally, be provided with the soldered ball that covers described the first conduction opening on described the first conduction opening, be provided with the soldered ball that covers described the second conduction opening on described the second conduction opening.
Optionally, described first the conduction opening and described second the conduction opening be arrayed.
Optionally, described substrate is printed circuit board (PCB).
Optionally, described test point and described the first conduction opening partly or entirely is connected.
Optionally, the height of described boss is between 0.5mm～2.5mm.
Optionally, the position along described boss and described substrate joint portion, be provided with through hole.
The utility model also provides a kind of chip test system, described system comprises test machine, circuit board and above-mentioned apparatus for testing chip, described apparatus for testing chip is welded on described circuit board, described chips welding is on described apparatus for testing chip, and the test point of described test machine and described apparatus for testing chip is accessibly connected.
Optionally, described apparatus for testing chip is welded on described chip corresponding position on described circuit board.
Optionally, described chips welding is on second of the substrate of described apparatus for testing chip, and the pin of described chip and described the first conduction opening are corresponding.
Optionally, described circuit board is printed circuit board (PCB) or flexible PCB.
Compared with prior art, the technical solution of the utility model has the following advantages:
Use the apparatus for testing chip described in the utility model embodiment, the signal end of described circuit board is connected with the pin of chip to be measured by the first conduction opening and the second conduction opening, described the first conduction opening and the second conduction opening are electrically connected to the test point on substrate, by the test point on the pointer contact substrate of test use, thereby can to chip to be measured whether up to specification and weldability test, need not to reserve test point in circuit board, therefore the space that can save circuit board, the cost of manufacture of reduction circuit board.
Further, when described test point and described first, conduct electricity opening one by one at once, can test all pins of chip, improve the fiduciary level of test.
Further, described the first conduction opening and described second conducts electricity the opening formation conductive through hole that is interconnected, can better the signal of chip be connected with the signal of circuit board, at the inwall of through hole, adhere to the layer of metal conductive layer, can strengthen the electric conductivity of described conductive through hole.
Further, by being arranged on the soldered ball on the first conduction opening, with described chips welding on described substrate, be arranged on the soldered ball on the second conduction opening, described boss is welded on described circuit board, make described apparatus for testing chip and chip and circuit board all be welded to connect, the interference that in the time of can reducing test chip, signal is produced.
Further, on the position along described boss and described substrate joint portion, through hole is set, can facilitates the operation of technician to the substrate both sides.
Description of drawings
Fig. 1 is the schematic cross-section of apparatus for testing chip described in the utility model embodiment one;
Fig. 2 is the upward view of Fig. 1;
Fig. 3 is the vertical view of Fig. 1;
Fig. 4 is the structural representation of chip test system described in the utility model embodiment two.
Embodiment
In prior art, for the up to specification and weldability whether of parts on testing circuit board, common way is to reserve some test points on circuit board.But along with the development of science and technology, the size of circuit board is more and more less, but the parts of arranging on circuit board are more and more.Carry out the test of parts on circuit board in reservation test point on circuit board, can seriously take the space of circuit board, while especially adopting the high pin chip on this way testing circuit board, can greatly increase the cost of manufacture of circuit board.
The apparatus for testing chip that the utility model embodiment provides, described boss is arranged on the first surface of described substrate, be provided with test point on second of described substrate, the first conduction opening on second of described test point and substrate and the second conduction opening on boss are electrically connected to.Like this, while using the described apparatus for testing chip of the utility model embodiment, boss is fixed on position corresponding to chip described in circuit board, just can be by the test point on contact substrate, realization is to the whether test of up to specification and weldability of chip pin, and need not take space on circuit board, greatly reduce the cost of manufacture of circuit board.
, for above-mentioned purpose of the present utility model, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiment of the utility model is described in detail.
Embodiment one
Referring to Fig. 1, the apparatus for testing chip in the present embodiment comprises: substrate 101, described substrate comprise the first surface that is oppositely arranged and second; Be arranged on the boss 102 of described substrate 101 first surfaces; Be arranged on 101 second of described substrates and the first conduction opening 103 corresponding with chip pin to be measured; Be arranged on described boss 102 and the second conduction opening 104 corresponding with described the first conduction opening, described the second conduction opening 104 is electrically connected to described the first conduction opening 103; And being arranged on test point (not shown) on 101 second of described substrates, described test point and described the first conduction opening 103 are electrically connected to.
In concrete enforcement, described boss 102 is fixed on position corresponding to the above chip of circuit board, test point on substrate 101 is electrically connected to the first conduction opening 103 and the second conduction opening 104, probe by test use contacts with described test point, and the first conduction opening and the second conduction opening by with described test point, being electrically connected to, just can to described chip whether up to specification and weldability test.
Need to prove, described circuit board can be that printed circuit board (PCB) (PCB) can be also flexible PCB, and after test was completed, described chip can be assemblied on described circuit board.
Wherein, described the first conduction opening 103 and described the second conduction opening 104 can be interconnected and form conductive through hole 105, the first conduction openings 103 and second and conduct electricity opening 104 and be respectively the opening at conductive through hole 105 two ends.Described conductive through hole 105 can be connected the pin of chip with the signal end on circuit board, like this, described chip is connected with described circuit board by described apparatus for testing chip, be that described chip indirectly is fixed on described circuit board, and to the test of chip pin, just can be undertaken by the test point that is connected with described conductive through hole.
For the electric conductivity that makes described conductive through hole better, those skilled in the art can also adhere to the layer of metal conductive layer on the inwall of described conductive through hole, the selection of described metal can be determined according to actual conditions, when meeting the enhancing electric conductivity, avoid the signal generation of described apparatus for testing chip both sides is disturbed and got final product.
Those skilled in the art can also fill with scolding tin or other metals in described conductive through hole, in order to the electric conductivity of the described conductive through hole of further enhancing.
Referring to Fig. 2 and Fig. 3, wherein Fig. 2 is the upward view of Fig. 1 chips proving installation, and Fig. 3 is the vertical view of Fig. 1 chips proving installation.
As shown in Figure 2, on the first surface of described substrate 101, be provided with the first conduction opening 103, and the test point 104 that is electrically connected to described the first conduction opening 103.
Wherein, described substrate 101 can be made into pcb board, and its shape can be set as required by those skilled in the art.In the present embodiment, described substrate 101 surface configurations can be rectangle.Described test point 104 can be connected one by one with described the first conduction opening 103, thereby can all test all pins of chip, described test point 104 also can be connected with partially conductive opening 103, only the part pin of chip is tested, namely the quantity of described test point 104 is set according to actual needs.
Described the first conduction opening 103 must be connected one by one with the pin of described chip, described the first conduction opening 103 has identical arrangement mode with the pin of described chip usually, for example when described chip was bga chip, described the first conduction opening was according to the BGA arrayed.
Described test point 104 can arbitrarily be set in the position of described substrate 101 first surfaces, as long as in the time of can guaranteeing that described chip is fixed on described substrate first surface, described test point can be used in test and gets final product.
As shown in Figure 3, be arranged on the boss 102 on 101 second of described substrates, on described boss 102 and the second conduction opening 104 corresponding with described the first conduction opening 103.Wherein, described boss 102 is used for described apparatus for testing chip is fixed on described circuit board, the shape of described boss 102 is not construed as limiting, as long as described boss 102 can be fixed on described apparatus for testing chip position corresponding to the above chip of circuit board, those skilled in the art can contact boss 102 according to actual needs with circuit board one side is arranged to the plane of square or rectangular.In the present embodiment, described boss is square.
In concrete enforcement, second of described substrate 101 generally is slightly larger than on described boss 102 one side with described substrate contacts, when described boss is square, and described substrate surface is while being shaped as rectangle, and the length of side of described square should be less than or equal to the shorter limit of the described rectangular length of side.
For avoiding affecting the assembling of other parts in circuit board, the height of described boss 102 can be set as required.In concrete enforcement, can be with the height setting of boss 102 between 0.5mm～2.5mm.
Described the second conduction opening 104 is corresponding one by one with described the first conduction opening, is also that pin, the described first conduction opening, described second of described chip conducts electricity opening 104 correspondence one by one mutually.During according to the BGA arrayed, described the second conduction opening is also according to same BGA arrayed when described the first conduction opening.
In order further to strengthen the electric conductivity of described the first conduction opening 103 and described the second conduction opening 104, can on described the first conduction opening 103, the soldered ball that covers described the first conduction opening 103 be set, on described the second conduction opening 104, the soldered ball that covers described the second conduction opening 104 be set.Like this, described chip can be welded on described substrate, and described apparatus for testing chip can be welded on described circuit board.The inventor finds, mode by welding connects chip and circuit board, interference to signal while making test chip is very little, improve the fiduciary level of test, especially when described chip is bga chip, the pin of bga chip can better be connected with the first conduction opening, is conducive to keep the stable transfer of chip signal.
Operation for convenient those skilled in the art, can also be on described substrate,, along the position of described boss 102 with described substrate 101 joint portions, some through hole 106(are set referring to Fig. 2 and Fig. 3), facilitate the operation of apparatus for testing chip both sides by described through hole 106.Wherein, the size of described through hole is not construed as limiting, those skilled in the art can rationally arrange according to the actual conditions of described substrate.
In concrete enforcement, can with the said chip proving installation as chip installation device, described chip be fixed on described circuit board.
Embodiment two
Referring to Fig. 4, the present embodiment also provides a kind of chip test system, described system comprises the apparatus for testing chip 10 described in test machine 40, circuit board 30 and embodiment one, described apparatus for testing chip 10 is welded on described circuit board 30, described chip 20 is welded on described apparatus for testing chip 10, and described test machine 40 is accessibly connected with the test point of described apparatus for testing chip 10.
Wherein, described test machine 40 can comprise for the probe 401 that contacts with test point, and described probe 401 is by with test point, contacting, and tests whether up to specification and weldability of the corresponding pin of described chip.
Need to prove, the test machine shown in Fig. 4 is an embodiment of the present utility model, and those skilled in the art can not assert with this shape of described test machine.
described chip 20 can be bga chip, the corresponding pin of described chip is connected with the first conduction opening on substrate 101 described in described apparatus for testing chip 10, because the pin of described chip and described the first conduction opening are one to one, to conduct electricity opening be also one to one and be arranged on second on described apparatus for testing chip boss 102 conduction opening and described first, like this, described chip 20 is connected with described circuit board 30 by described apparatus for testing chip 10, be the pin corresponding connection of signal end by described apparatus for testing chip 10 and described chip 20 on circuit board 30.
Test point on the substrate of described apparatus for testing chip 10, can be corresponding one by one with described the first conduction opening, thereby all pins that can test chip, described test point also can be corresponding with part the first conduction opening, part pin that correspondingly can test chip.
In concrete enforcement, the boss 102 of described apparatus for testing chip 10 is arranged on the position 301 of circuit board 30 the above chip 20 correspondence.
Described circuit board 30 can be PCB or flexible PCB.
The detailed process that the described system of application the present embodiment is tested is as follows:
1) pin of described chip 20 is welded on second of substrate 101 of described apparatus for testing chip 10;
2) boss of described apparatus for testing chip 10 102 is welded on the position 301 of described chip 20 correspondences in circuit board 30;
3) test point of the 401 described apparatus for testing chip 10 of contact of the probe by described test machine 40, test whether up to specification and weldability of pin corresponding to described chip.
Test macro described in the present embodiment, described apparatus for testing chip is with after described chip is connected, directly be fixed on described circuit board, if while according to said process, operating, specification or the weldability of finding the respective pin of described chip are not inconsistent, can be with the chip solution postwelding that is welded on described apparatus for testing chip, more again other alternative chips are welded on described apparatus for testing chip, and do not need to change apparatus for testing chip.
Compare with the chip detecting method of reserving test point in prior art, not only saved the space on the circuit board, and avoided repeatedly with circuit board and chip while tip-off, the damage to other parts on circuit board and circuit board that causes, and in the whole process that the test macro that adopts the present embodiment is tested, when the specification of the respective pin of finding described chip or weldability are not inconsistent, only need to be with the chip tip-off, will substitute chip and again be welded on described apparatus for testing chip and get final product.
Although the utility model discloses as above, the utility model not is defined in this.Any those skilled in the art, within not breaking away from spirit and scope of the present utility model, all can make various changes or modifications, and therefore protection domain of the present utility model should be as the criterion with the claim limited range.
Claims (13)
1. an apparatus for testing chip, is characterized in that, described device comprises: substrate, described substrate comprise the first surface that is oppositely arranged and second; Be arranged on the boss of described substrate first surface; Be arranged on second the first upper and corresponding with chip pin to be measured conduction opening of described substrate; Be arranged on described boss and the second conduction opening corresponding with described the first conduction opening, described the second conduction opening is electrically connected to described the first conduction opening; And being arranged on test point on second of described substrate, described test point and described the first conduction opening are electrically connected to.
2. apparatus for testing chip as claimed in claim 1, it is characterized in that, described the first conduction opening and described the second conduction opening formation conductive through hole that is interconnected, described the first conduction opening and described second conduct electricity opening and are respectively the opening at described conductive through hole two ends.
3. apparatus for testing chip as claimed in claim 2, is characterized in that, described conductive through hole inwall adheres to the layer of metal conductive layer.
4. apparatus for testing chip as claimed in claim 1, is characterized in that, is provided with the soldered ball that covers described the first conduction opening on described the first conduction opening, is provided with the soldered ball that covers described the second conduction opening on described the second conduction opening.
5. apparatus for testing chip as claimed in claim 1, is characterized in that, described the first conduction opening and described the second conduction opening are arrayed.
6. apparatus for testing chip as claimed in claim 1, is characterized in that, described substrate is printed circuit board (PCB).
7. apparatus for testing chip as claimed in claim 1, is characterized in that, described test point partly or entirely is connected with described the first conduction opening.
8. apparatus for testing chip as claimed in claim 1, is characterized in that, the height of described boss is between 0.5mm～2.5mm.
9. apparatus for testing chip as claimed in claim 1, is characterized in that, the position along described boss and described substrate joint portion, be provided with through hole.
10. chip test system, it is characterized in that, described system comprises test machine, circuit board and apparatus for testing chip as described in claim 1 to 9 any one, described apparatus for testing chip is welded on described circuit board, described chips welding is on described apparatus for testing chip, and the test point of described test machine and described apparatus for testing chip is accessibly connected.
11. system as claimed in claim 10, is characterized in that, described apparatus for testing chip is welded on the position of described chip correspondence on described circuit board.
12. system as claimed in claim 10, is characterized in that, described chips welding is on second of the substrate of described apparatus for testing chip, and the pin of described chip and described the first conduction opening are corresponding.
13., as claim 10 or the described system of 11 any one, it is characterized in that, described circuit board is printed circuit board (PCB) or flexible PCB.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203498734U CN203287491U (en) | 2013-06-18 | 2013-06-18 | Device and system for testing chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203498734U CN203287491U (en) | 2013-06-18 | 2013-06-18 | Device and system for testing chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203287491U true CN203287491U (en) | 2013-11-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013203498734U Expired - Lifetime CN203287491U (en) | 2013-06-18 | 2013-06-18 | Device and system for testing chip |
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| Country | Link |
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| CN (1) | CN203287491U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109031102A (en) * | 2018-09-20 | 2018-12-18 | 北方电子研究院安徽有限公司 | A kind of apparatus for testing chip |
| CN112904180A (en) * | 2021-01-22 | 2021-06-04 | 长鑫存储技术有限公司 | Chip test board and chip test method |
-
2013
- 2013-06-18 CN CN2013203498734U patent/CN203287491U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109031102A (en) * | 2018-09-20 | 2018-12-18 | 北方电子研究院安徽有限公司 | A kind of apparatus for testing chip |
| CN112904180A (en) * | 2021-01-22 | 2021-06-04 | 长鑫存储技术有限公司 | Chip test board and chip test method |
| CN112904180B (en) * | 2021-01-22 | 2022-04-19 | 长鑫存储技术有限公司 | Chip test board and chip test method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20131113 |
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| CX01 | Expiry of patent term |