CN112152596B - Circuit and method for generating pulse output - Google Patents
Circuit and method for generating pulse output Download PDFInfo
- Publication number
- CN112152596B CN112152596B CN202010587448.3A CN202010587448A CN112152596B CN 112152596 B CN112152596 B CN 112152596B CN 202010587448 A CN202010587448 A CN 202010587448A CN 112152596 B CN112152596 B CN 112152596B
- Authority
- CN
- China
- Prior art keywords
- delay
- delay line
- stage
- per
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000005070 sampling Methods 0.000 claims description 69
- 238000005259 measurement Methods 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 4
- 230000000737 periodic effect Effects 0.000 claims description 2
- 230000000630 rising effect Effects 0.000 description 9
- 239000008186 active pharmaceutical agent Substances 0.000 description 6
- 230000001934 delay Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011143 downstream manufacturing Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003362 replicative effect Effects 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
Landscapes
- Pulse Circuits (AREA)
Abstract
A system, method and apparatus for a circuit for generating a pulse output having a controllable pulse width is provided. Systems and methods may include a delay line having a plurality of stages. The delay-per-stage calculation circuit is configured to determine a delay per stage of the delay line using the first clock input. The pulse generation circuit is configured to generate a pulse output using the delay line based on each stage delay using a second clock input having a lower frequency than the first clock input.
Description
Technical Field
The techniques described in this disclosure relate generally to electronic systems, and more particularly to pulse signal generation.
Background
Pulse signals are a common mechanism in digital circuits for a variety of purposes, such as signaling storage read/write times, indicating the occurrence of an event, providing timing synchronization, and so forth. The correct function of the circuit generally indicates that the pulse signal has a specified width. Pulses that are not provided for a sufficient period of time may result in incomplete downstream processes or may not be detected at all. Pulses provided for an extended period of time may result in erroneous downstream circuit operation (e.g., an otherwise single pulse may be interpreted as multiple pulses). Thus, the exact pulse duration (i.e., width) ensures proper functioning of the digital circuit. As circuit sizes shrink and operating speeds increase, power and circuit area efficiency, including all aspects of pulse generation, become very important.
Disclosure of Invention
A circuit for generating a pulse output having a controllable pulse width includes a delay line, a per-stage delay calculation circuit, and a pulse generation circuit. The delay line has a plurality of stages. The delay-per-stage calculation circuit is configured to determine a delay-per-stage of the delay line using a first frequency input. The pulse generation circuit is configured to generate the pulse output based on the per-stage delay using the delay line. Wherein the delay line receives a second frequency input having a lower frequency than the first frequency input; wherein the pulse generation circuit selectively accesses a plurality of outputs of both of the plurality of stages of the delay line based on the per-stage delay and a selected pulse width to generate the pulse output.
A method of generating a pulse output having a controllable pulse width includes accessing a delay line having a plurality of stages; determining a per-stage delay of the delay line based on a first frequency input; generating the pulse output using the delay line by providing a second frequency input to the delay line based on the per-stage delay, the second frequency input having a lower frequency than the first frequency input; and generating the pulse output from the frequency of the second frequency input, wherein the frequency of the second frequency input is substantially lower than the frequency of the first frequency input used to determine the per-stage delay.
A circuit for generating a pulse output having a pulse width of a controllable duration includes a delay line, a replica delay line, a per-stage delay calculation circuit, and a pulse generation circuit. The delay line has a plurality of stages. The replica delay line has the same number of stages as the delay line, the stages of the replica delay line being of the same type as the plurality of stages of the delay line. The delay-per-stage calculation circuit is configured to determine a delay-per-stage of the delay line by using a first frequency input, wherein determining the delay-per-stage of the delay line is based on operation of the replica delay line. The pulse generating circuit is used for generating the pulse output by using the delay line and based on the delay of each stage, wherein the delay line receives a second frequency signal.
A circuit for generating a pulse output having a controllable pulse width includes a delay line, a replica delay line, a per-stage delay calculation circuit, and a pulse generation circuit. The delay line has a plurality of stages. The replica delay line has a plurality of stages substantially similar to the delay line. The delay-per-stage calculation circuit is configured to determine a delay per stage of the delay line using a first clock input and a sampling frequency input. The pulse generation circuit is used for generating the pulse output by using the delay line and based on the delay of each stage. Wherein the delay line receives a second frequency input. Wherein the per-stage delay calculation circuit determines the per-stage delay of the delay line based on operation of the replica delay line to receive the first frequency input.
A method of generating a pulse output having a controllable pulse width includes accessing a delay line having a plurality of stages; providing the first frequency input to a replica delay line having a plurality of stages substantially similar to the delay line; sampling an output of the replica delay line using a sampling frequency input; determining a per-stage delay of the delay line based on operation of the replica delay line; and generating the pulse output using the delay line by providing a second frequency input to the delay line based on the per-stage delay.
A circuit for generating a pulse output having a controllable pulse width includes a delay line, a per-stage delay calculation circuit, and a pulse generation circuit. The delay line has a plurality of stages. The delay-per-stage calculation circuit is configured to determine a delay-per-stage of the delay line using a sampling frequency input. The pulse generation circuit is used for generating the pulse output by using the delay line and based on the per-stage delay. Wherein the delay line receives a fast frequency input. Wherein the per-stage delay calculation circuit determines the per-stage delay of the delay line based on operation of the delay line to receive the fast frequency input.
A circuit for generating a pulse output having a controllable pulse width includes a delay line, a per-stage delay calculation circuit, and a pulse generation circuit. A delay line has a plurality of stages. A per-stage delay calculation circuit is used to determine a per-stage delay of the delay line. A pulse generation circuit is used to generate the pulse output based on the per-stage delay using the delay line. Wherein the pulse generation circuit selectively accesses outputs of two of the plurality of stages of the delay line based on the per-stage delay and a selected pulse width to generate the pulse output.
A method of generating a pulse output having a controllable pulse width, comprising determining a per-stage delay of a delay line based on a first frequency input; generating the pulse output using the delay line by providing a second frequency input to the delay line based on the per-stage delay, the second frequency input having a lower frequency than the first frequency input; and generating the pulse output from the frequency of the second frequency input, wherein the frequency of the second frequency input is substantially lower than the frequency of the first frequency input used to determine the per-stage delay.
A circuit for generating a pulse output having a pulse width of a controllable duration includes a delay line and a replica delay line, a per-stage delay calculation circuit, and a pulse generation circuit. The delay line and the replica delay line each have a plurality of stages. A per-stage delay calculation circuit is configured to determine a per-stage delay of the delay line using a first frequency input, wherein determining the per-stage delay of the delay line is based on operation of the replica delay line. And a pulse generating circuit for generating the pulse output based on the delay of each stage by using the delay line, wherein the delay line receives a second frequency signal.
Drawings
The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features are not drawn to scale in accordance with standard practices in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 illustrates an exemplary width controllable pulse generator according to various embodiments of the present disclosure;
FIG. 2 illustrates an exemplary circuit for generating a pulsed output based on the outputs of two selected stages of a delay line, in accordance with various embodiments of the present disclosure;
FIG. 3 illustrates an exemplary timing diagram of signals of a pulse generation circuit according to various embodiments of the present disclosure;
FIG. 4 illustrates an exemplary width controllable pulse generator utilizing replica delay lines to determine per-stage delays in accordance with various embodiments of the present disclosure;
FIG. 5 illustrates an exemplary width controllable pulse generator using a time-to-digital converter and a cycle stage calculator to determine per-stage delays in accordance with various embodiments of the present disclosure;
FIG. 6 illustrates an exemplary time-to-digital converter in accordance with various embodiments of the present disclosure;
FIG. 7 illustrates an exemplary sampling array generated by a time-to-digital converter in accordance with various embodiments of the present disclosure;
FIG. 8 illustrates different example definitions of loops of a sampling array according to various embodiments of the present disclosure;
FIG. 9 illustrates an exemplary circuit for generating a pulse output using a single delay line;
FIG. 10 is a flow chart of an exemplary method of generating a pulse output having a controllable width, the exemplary method including accessing a delay line having a plurality of stages.
[ symbolic description ]
102 Width controllable pulse generator
104 delay line
106 pulse output
108 pulse generating circuit
110 delay calculation circuit per stage
412 replica delay line
500 pulse generator
502 pulse generating circuit
504 delay line
506 phase selection circuit
508 pulse width limiter circuit
510 delay calculation circuit per stage
512 replica delay line
514 time to digital converter
516, cycle stage calculator
602 first sampling circuit
604 final sampling circuit
902 circuit
904 delay line
906 per-stage delay calculation circuit
908 pulse generating circuit
1002. 1004, 1006 square block
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, such are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Traditionally, high speed clocks have been used to provide accurate pulse generation, where the smallest pulse width that can be generated is determined by the clock frequency or by large area consumption solutions (such as charge pump control loops). Such conventional approaches are inefficient in one or both of power and circuit area. Some embodiments described herein utilize a delay line that includes multiple delay stages. A delay associated with one of the stages (per-stage delay) is measured. The outputs of two of the delay line stages are used to generate a pulse of a desired width, with the exact stage used to generate this pulse being determined based on the measured delay per stage. In this way, the smallest producible pulse width is based on the delay per stage of the delay line (rather than the input clock frequency), enabling the generation of accurately small pulse widths without the need for a fast input clock for power consumption.
Fig. 1 illustrates an exemplary width controllable pulse generator according to various embodiments of the present disclosure. The width controllable pulse generator 102 utilizes a delay line 104 to generate a pulse output 106 using a pulse generation circuit 108. In an embodiment, the pulse output width is always the same and is preprogrammed into the pulse generation circuit 108. In other embodiments, the desired pulse width is controllable (e.g., via input to the pulse generation circuitry 108) and may be controlled in operation during operation of the width controllable pulse generator 102.
The delay line 104 in the embodiment is constituted by a plurality of delay stages (e.g., buffer stages) connected in series. The outputs from each of the stages may be made available to the pulse generation circuit 108 via split lines. The outputs of two of the delay line 104 stages are selected to produce a pulse output 106 having a desired width, wherein selection of different stages results in pulses of different widths, wherein in some embodiments the pulse generation circuit 108 utilizes each stage delay determined by each stage delay calculation circuit 110.
Fig. 2 illustrates an exemplary circuit for generating a pulsed output based on the outputs of two selected stages of a delay line, according to various embodiments of the present disclosure. The delay line 104 is made up of a number of stages (e.g., buffer circuits represented in triangles, with each stage having an associated tap line from which the output of each stage can be accessed individually). The output of the selected stage is accessed via two multiplexers (MUX 1, MUX 2) and provided to an SR (set-reset) flip-flop (which in this example comprises two nor gates connected as illustrated) as inputs DR and DS in order to generate a pulsed output as illustrated in fig. 3.
By selecting outputs from different stages (e.g., outputs separated by 1 stage, outputs separated by 3 stages, outputs separated by 8 stages), pulse generation circuit 108 can selectively control the width of the generated pulses. Fig. 3 illustrates an exemplary timing diagram of signals of pulse generation circuit 108 in accordance with various embodiments of the present disclosure. In the example of fig. 3, the tap output of the first stage of the delay line is provided to the DR input of the SR flip-flop and the tap output of the second stage of the delay line is provided to the DS input of the SR flip-flop. Correspondingly, the SR flip-flop outputs a pulse (pwg_out) having a width associated with the time difference between the rising edges of the DR and DS inputs. By selecting tap lines of different stages for the DS input (e.g., using MUX2 illustrated in FIG. 2), pulses with different widths are output as PWG_OUT. For example, if the next stage is tapped and output to the DS, the time between the rising edges of DR and DS will be longer, resulting in a wider pulse output of PWG_OUT. In this manner, the width of the pulses generated by the pulse generation circuit 108 may vary in operation, such as based on control signals received by the pulse generation circuit 108.
The delay line used to generate the output pulse is controlled by the input clock (FREF). As further discussed herein, the clock signal (sometimes referred to herein as the second clock input) may be implemented as a relatively slow clock (e.g., 50 MHz) having a frequency selected based on the frequency pulses that need to be generated, where between 1 and (delay line stage/2) pulses may be generated per cycle of the FREF clock via tapping of the output of the delay line stage. The second clock frequency only limits the speed at which pulses can be generated, and not the width of the pulses, which depends on the delay associated with each stage of the delay line rather than the FREF frequency. This provides the potential for substantial power savings.
Referring back to fig. 1, since the width of the pulse output may be controlled based on each stage delay of the delay line 104, it may be beneficial to have accurate measurement of each stage delay. In practice, each level of delay may vary from its design based on manufacturing process variations, location in larger circuits (e.g., parasitic capacitance), temperature, etc. Since pulses are generated using differences in rising edge outputs of stages separated by N stages, errors in delay accuracy per stage may result in a composite error in the generated pulse width (e.g., an x seconds error in delay accuracy per stage may result in an N x deviation from the desired pulse width).
In an embodiment, once the width controllable pulse generator 102 is initialized, each level of delay may be measured, determined, or calculated. Each stage delay may be determined based on interactions with the delay line 104 providing the pulse output 106 or with a replica delay line (not shown in fig. 1) that is similar to the delay line 104 (e.g., has the same or similar stages as the delay line 104). In some embodiments, the first clock input is used to determine the per-stage delay, where in some cases the first clock input is a fast clock (e.g., 4GHz, 5GHz, 10 times faster, 20 times faster, 50 times faster, 100 times faster) relative to the second clock input used to generate pulses during operation (i.e., after the initialization phase when each stage delay is determined). Knowing the per-stage delay determined by per-stage delay calculation circuit 110, pulse generation circuit 108 can select the output from the appropriate stage of the delay line to generate a pulse output having the desired width.
Fig. 4 illustrates an exemplary width controllable pulse generator 102 utilizing replica delay lines 412 to determine per-stage delays according to various embodiments of the present disclosure. Although different delay lines will have some magnitude of difference in each level of delay, in general, the difference will be small for delay lines located close to each other using a common fabrication process (e.g., they will have similar processes, experience similar parasitic capacitances, experience similar temperatures). Thus, the measured per-stage delay at replica delay line 412 may act as a proxy for the per-stage delay of delay line 104. In the example of fig. 4, the replica delay line 412 is controlled using a fast first clock input, wherein the output of the last stage of the replica delay line 412 is sampled according to a sampling clock input (e.g., 100MHz, 50 MHz).
Each stage of delay may be calculated in a number of ways. For example, the time difference between a rising edge of the first clock input and a corresponding rising edge of the output of the replica delay line 412 may be determined and divided by the number of stages of the replica delay line 412. However, factors such as variations in duty cycle ratio (e.g., duty cycle ratio of first clock input to sampling clock input) may lead to inaccuracies in using this approach.
Fig. 5 illustrates an exemplary width controllable pulse generator using a time-to-digital converter and a cycle stage calculator to determine per-stage delays according to various embodiments of the present disclosure. The example embodiment of fig. 5 performs the measurement of each level of delay (e.g., once at circuit initialization). The measurement is then used to tune the generation of a pulse output (PWG _ OUT) to provide an accurate pulse of the desired width, which in some embodiments is controllable (e.g., set according to a PWC signal based on a desired PulseWidth parameter). The pulse generator 500 of fig. 5 includes a pulse generation circuit 502, where the pulse generation circuit 502 is configured to generate a pulse output (pwg_out) using a delay line 504, a pulse width clipping circuit 508, and a phase selection circuit 506. Delay line 504 includes a plurality of stages that each delay an input clock signal (FREF) for a period of time. In one embodiment, such stages are connected in series such that each stage of delay line 504 delays the FREF clock cycle by one delay period per stage or more. The output of each stage of the delay line 504 may be accessed by a phase selection circuit 506 in addition to being provided to the next stage of the delay line 504. The pulse generation circuit 502 measures PSC [ N:0] using the per-stage delay indication provided by the per-stage delay calculation circuit 510 to select the tapped signal from a particular stage of the delay line 504 based on PWC [ M:0] to generate a pulse of a desired width (PulseWidth). The phase selection circuit 506 accesses the outputs of both of the stages of the delay line 504 according to PWC [ M:0] set based on the desired pulse width and each stage delay of each stage of the delay line 504 and provides the outputs to a pulse width clipping circuit 508 (e.g., an SR flip-flop as illustrated in fig. 2) to generate a pulse output (pwg_out).
The per-stage delay calculation circuit 510 may be used to determine the per-stage delay of the delay line 504 in a variety of ways. In some examples, the per-stage delay is determined based on measurements performed on the delay line 504. In the example of fig. 5, the per-stage delay calculation circuit 510 estimates the per-stage delay of the delay line 504 based on the operations and measurements performed on the replica delay line 512. A replicated delay line 512 that is substantially similar to delay line 504 (e.g., based on one or more of the number of delay stages, the type of delay stage, the proximity of locations on the manufacturing circuit) provides a good indicator of the behavior of delay line 504. When each stage of delay computation is enabled via tdc_en and tdc_pd (e.g., once during circuit initialization, periodically during circuit operation to ensure accurate circuit operation), the time-to-digital converter 514 uses the first clock input ckv_in to operate the replica delay line 512. In some embodiments, the first clock is significantly faster than the second FREF clock signal used to generate the pulse at pwg_out. For example, the first clock signal (ckv_in) used to determine each stage delay may be 10 times faster, 20 times faster, 50 times faster, 100 times faster than the second clock input (FREF) operation, where IN one example the first clock signal operates at 4GHz to 5GHz and the second clock signal operates at 50 MHz. The time to digital converter 514 samples the output of the replica delay line 512 operating with the first clock signal (ckv_in), where samples are taken according to a sampling clock frequency, which IN the example of fig. 5 is the second clock signal (FREF) used to operate the delay line 504 when generating the pulse output (pwg_out). In other examples, different clock signals with different (e.g., faster) clock signals may be used for sampling at the time-to-digital converter 514. The samples from the time-to-digital converter 514 are processed at the cycle stage calculator 516 to determine a metric indicative of the per-stage delay (PSC [ N:0 ]) transferred to the phase selection circuit 506 and used by the phase selection circuit 506 in generating the pulse output (PWG_OUT).
Fig. 6 illustrates an exemplary time-to-digital converter in accordance with various embodiments of the present disclosure. The time-to-digital converter 514 operates the replica delay line 512 by providing a first clock signal ckv_in to the replica delay line 512. The first sampling circuit 602 provides a first bit (Q) of a sampling array 0 ) The sample array is provided to the cycle stage calculator 516 based on the ckv_in signal before the ckv_in signal reaches the replica delay line 512. Subsequent sampling circuits (e.g., sampling circuits associated with the tapped output from each stage of replica delay line 512 up to final sampling circuit 604 associated with the last stage) provide subsequent bits (Q) of the sampling array 1 -Q N ) The sampling array is controlled by a sampling clock input (FREF).
Fig. 7 illustrates an exemplary sampling array generated by a time-to-digital converter, according to various embodiments of the present disclosure. The rising edge of the sampling clock FREF is used as a trigger for sampling the state of each stage of the replica delay line. Representing samples of each other as Q of a sampling array 0 To Q N The sample array is provided to a cycle stage calculator 516. The period stage calculator 516 determines the number of stages of the replica delay line 512 associated with a cycle of the sample array. FIG. 8 illustrates different example definitions of loops of a sampling array according to various embodiments of the present disclosure, where rising to a rising loop (i.e., represented by a transition from 0-1 to the next 0-1 in the sampling array) or falling to a falling period provides the most accurate measurement of delay per stage. A rising to falling cycle (i.e., represented by a transition from 0-1 to the next 1-0) may be utilized, but duty cycle ratio variations may introduce inaccuracies in each stage of computation.
Using the rise-to-rise loop in the example of fig. 7, eight replica delay line stage outputs S are required 1 To S 8 For sampling array Q to transition from 0-1 back to 1-0 and then from 0-1 again (i.e., PSC [ N: 0)]=8). The PSC value is provided to a phase selection circuit 506, which phase selection circuit 506 calculates the per-stage delay according to:
T stage = (1/frequency (CKV) IN ))/PSC[N:0]
The phase selection circuit 506 is then based on the per-stage delay T stage And the desired pulse width required by control signal PWC PWG_OUT To access the outputs of two particular stages of delay line 504. In one example, PWC is an array to have 1's in the values associated with the delay line 504 stage, this delay line 504 stage being selected as one input to the pulse width clipping circuit 508 and the 0 th stage of the first stage being the second input to the pulse width clipping circuit 508. In one embodiment, the PWC array value to be populated with 1 is determined according to the following equation:
PWC[M:0]＝PulseWidth PWG_OUT /(1/frequency (CKV) IN ))/PSC[N:0])。
As described above, the circuit for generating the pulse output may be operated using a delay line and a replica delay line for estimating each stage delay. In some embodiments, the same delay line used to generate the pulse output may be used to determine each stage delay. Fig. 9 illustrates an exemplary circuit 902 for generating a pulse output using a single delay line. During each stage of delay computation phase, the delay line 904 operates using a first (e.g., fast) clock input, wherein the output of the stage of delay line is sampled according to a sampling clock input (e.g., a second clock input or a separate sampling clock as described above with reference to fig. 5) and provided to each stage of delay computation circuitry 906. The per-stage delay calculation circuit 906 calculates a metric representing the per-stage delay of the delay line 904 and provides that metric (e.g., PSC [ N:0 ]) to the pulse generation circuit 908. The pulse generation circuit 908 uses this metric and the desired pulse width to select the stage from which to tap the output in order to generate a pulse output during operation (e.g., first and fifth stages; zeroth (before any stage) and seventh stages). The pulse generation circuit 908 accesses the outputs of the selected stages and uses those outputs to generate a pulsed output (e.g., by providing the outputs of two selected stages to an SR flip-flop as described above).
In some embodiments, a pulse may be generated having a width substantially equal to each stage delay of delay line 504, where the width of such pulse is not dependent on the second clock signal. The second clock signal frequency only indicates how often pulses of that width can be generated (e.g., 1 to N times per second clock signal period, where N depends on the number of available stages in the delay line).
FIG. 10 is a flow chart of an exemplary method of generating a pulse output having a controllable pulse width, the exemplary method including accessing a delay line having a plurality of stages. At block 1002, a delay line having a plurality of stages is accessed. At block 1004, a per-stage delay of the delay line is determined based on the delay line output generated by the first clock input. At 1006, based on the per-stage delay, a pulse output is generated using the delay line by providing a second clock input to the delay line, the second clock input having a lower frequency than the first clock input.
The use of various circuits and configurations as described herein may provide a number of advantages. For example, when the PLL is operated in the fractional-N mode, jitter performance is improved because phase noise generated by an oscillator within the PLL is eliminated. Because the realignment works in the fractional-N mode, switching operations between the fractional-N mode and the integer-N mode are facilitated.
In one embodiment, a circuit for generating a pulse output having a controllable pulse width includes a delay line having a plurality of stages. The delay per stage calculation circuit is a circuit to determine the delay per stage of the delay line using the first clock input. The pulse generation circuit is configured to generate a pulse output using the delay line based on each stage delay using a second clock input having a lower frequency than the first clock input. In one embodiment, the frequency of the second clock input used to generate the pulse output is substantially lower than the frequency of the first clock frequency used to determine the delay per stage. In one embodiment, the second clock frequency is 10% lower than the first clock frequency. In one embodiment, the circuit further comprises a replica delay line having a plurality of stages substantially similar to the delay line; wherein the delay-per-stage calculation circuit determines the delay-per-stage of the delay line based on an operation of the replica delay line to receive the first clock input. In an embodiment, wherein the delay per stage calculation circuit does not control the delay line in determining each stage delay of the delay line. In one embodiment, each stage of delay calculation circuitry uses a first clock input and a sampling clock input to determine each stage of delay. In one embodiment, each stage of delay calculation circuit includes a time-to-digital converter and a periodic stage calculator. The time-to-digital converter is used for sampling and copying one output of the delay line according to the sampling clock input; and a period stage calculator for determining a number of sampling clock periods within a cycle of the sampling output of the replica delay line using the sampling output of the replica delay line. In one embodiment, wherein each stage of delay is determined based on the determined number of sampling clock cycles and the frequency of the first clock input; and wherein the sampling clock input frequency is substantially the same as a frequency of the second clock input. In an embodiment, the replica delay line has a same number of stages as the delay line. In one embodiment, wherein the pulse generation circuit selectively accesses the outputs of two of the stages of the delay line based on each stage delay and a selected pulse width to generate the pulse output. In one embodiment, the circuit further comprises an SR flip-flop receiving the outputs of the two stages and generating the pulsed output. In an embodiment, wherein the circuit is configured to determine the delay of each stage exactly once at each initialization of the circuit.
In another embodiment, a method of generating a pulse output having a controllable pulse width includes accessing a delay line having a plurality of stages. Each stage delay of the delay line is determined based on the delay line output generated by the first clock input. Based on the per-stage delay, a pulse output is generated using the delay line by providing a second clock input to the delay line, the second clock input having a lower frequency than the first clock input. In one embodiment, wherein determining the delay per stage of the delay line comprises: providing a first clock input to a replica delay line having a plurality of stages substantially similar to the delay line; wherein each stage of delay of the delay line is based on an operation of the replica delay line to receive the first clock input. In one embodiment, wherein determining the delay per stage of the delay line further comprises: an output of the replica delay line is sampled using a sampling clock input. In one embodiment, wherein determining the delay per stage of the delay line further comprises: sampling an output of the replica delay line controlled by the first clock input using the sampling clock input; a number of sampling clock cycles is determined within a cycle of the sampled output of the replica delay line. In one embodiment, the delay per stage is determined based on the determined number of sampling clock cycles and the frequency of the first clock input. In one embodiment, wherein generating the pulsed output comprises: the outputs of two of the stages of the delay line are selectively accessed based on each stage delay and a selected pulse width to produce a pulsed output. In one embodiment, wherein two stages are selected based on a selected pulse output width and per-stage delay.
In another embodiment, a circuit for generating a pulse output having a pulse width of a controllable duration includes a delay line having a plurality of stages, and a replica delay line having the same number of stages as the delay line, the replica delay line stages being of the same type as those stages of the delay line. The delay-per-stage calculation circuit is to determine a delay per stage of the delay line based on replicating operation of the delay line using the first clock input, and the pulse generation circuit is to generate a pulse output using the delay line based on the delay per stage using the second clock input.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (61)
1. A circuit for generating a pulse output having a controllable pulse width, comprising:
a delay line having a plurality of stages;
a delay-per-stage calculation circuit for determining a delay per stage of the delay line using a first clock input; and
a pulse generation circuit for generating the pulse output based on the per-stage delay by using the delay line;
wherein the delay line receives a second clock input having a lower frequency than the first clock input;
wherein the pulse generation circuit selectively accesses the outputs of two of the plurality of stages of the delay line based on the per-stage delay and a selected pulse width to generate the pulse output.
2. The circuit of claim 1 wherein the frequency of the second clock input used to generate the pulse output is substantially lower than the frequency of the first clock input used to determine the per-stage delay.
3. The circuit of claim 2 wherein the frequency of the second clock input is 10% lower than the frequency of the first clock input.
4. The circuit as recited in claim 1, further comprising:
a replica delay line having a plurality of stages substantially identical to the delay line;
wherein the per-stage delay calculation circuit determines the per-stage delay of the delay line based on the operation of the replica delay line to receive the first clock input.
5. The circuit of claim 4 wherein the per-stage delay calculation circuit does not control the delay line in determining the per-stage delay of the delay line.
6. The circuit of claim 4 wherein the per-stage delay calculation circuit determines the per-stage delay by using the first clock input and a sampling frequency input.
7. The circuit of claim 6 wherein the delay-per-stage calculation circuit comprises:
a time-to-digital converter for sampling an output of the replica delay line according to the sampling frequency input; and
a cycle stage calculator for determining a number of sampling frequency cycles within a cycle of the sampled output of the replica delay line using the sampled output of the replica delay line.
8. The circuit of claim 7, wherein the per-stage delay is determined based on the determined number of the sampling frequency periods and the frequency of the first clock input; and
wherein the frequency of the sampling frequency input is substantially the same as the frequency of the second clock input.
9. The circuit of claim 4 wherein the replica delay line has the same number of stages as the delay line.
10. The circuit of claim 1, further comprising an SR flip-flop that receives the outputs of the two of the plurality of stages and generates the pulsed output.
11. The circuit of claim 1, wherein the circuit is configured to determine the delay per stage exactly once per initialization of the circuit.
12. The circuit of claim 1 wherein the two of the plurality of stages are selected based on a selected pulse output width and the delay per stage.
13. A method of generating a pulse output having a controllable pulse width, comprising:
accessing a delay line having a plurality of stages;
determining a per-stage delay of the delay line based on a first clock input;
Generating the pulse output using the delay line by providing a second clock input to the delay line based on the per-stage delay, the second clock input having a lower frequency than the first clock input; and
the pulse output is generated from a frequency of the second clock input, wherein the frequency of the second clock input is substantially lower than the frequency of the first clock input used to determine the per-stage delay, wherein a plurality of outputs of two of the plurality of stages of the delay line are selectively accessed based on the per-stage delay and a selected pulse width to generate the pulse output.
14. The method of claim 13, wherein determining the per-stage delay of the delay line comprises:
providing the first clock input to a replica delay line having a plurality of stages substantially identical to the delay line;
wherein the per-stage delay of the delay line is based on the operation of the replica delay line to receive the first clock input.
15. The method of claim 14 wherein the replica delay line has the same number of stages as the delay line.
16. The method of claim 15, wherein determining the per-stage delay of the delay line further comprises:
An output of the replica delay line is sampled using a sampling frequency input.
17. The method of claim 16, wherein determining the per-stage delay of the delay line further comprises:
sampling an output of the replica delay line controlled by the first clock input using the sampling frequency input;
a number of sampling frequency periods is determined, the sampling frequency periods being within a cycle of the sampled output of the replica delay line.
18. The method of claim 17, wherein the per-stage delay is determined based on the determined number of the sampling frequency periods and the frequency of the first clock input.
19. The method of claim 13, wherein the two of the plurality of stages are selected based on a selected pulse output width and the per-stage delay.
20. The method of claim 13, wherein the frequency of the second clock input is less than 10% of the frequency of the first clock input.
21. The method of claim 13 wherein each stage of delay line has a plurality of stages substantially identical to the delay line, and wherein the each stage delay calculation circuit does not control the delay line in determining the each stage delay of the delay line.
22. The method of claim 13, wherein determining the per-stage delay of the delay line further comprises:
the delay of each stage is determined exactly once at each initialization.
23. A circuit for generating a pulse output having a pulse width of a controlled duration, comprising:
a delay line having a plurality of stages;
a replica delay line having a plurality of stages of the same number as the delay line, the stages of the replica delay line being of the same type as the plurality of stages of the delay line;
a per-stage delay calculation circuit for determining a per-stage delay of the delay line by using a first clock input, wherein determining the per-stage delay of the delay line is based on operation of the replica delay line; and
a pulse generating circuit for generating the pulse output based on the delay of each stage by using the delay line, wherein the delay line receives a second clock signal,
wherein the pulse generation circuit selectively accesses the outputs of two of the plurality of stages of the delay line based on the per-stage delay and a selected pulse width to generate the pulse output.
24. The circuit of claim 23 wherein the frequency of the second clock input is substantially lower than the frequency of the first clock input.
25. The circuit of claim 24 wherein the frequency of the second clock input is less than 10% of the frequency of the first clock input.
26. A circuit for generating a pulse output having a controllable pulse width, comprising:
a delay line having a plurality of stages;
a replica delay line having a plurality of stages substantially identical to the delay line;
a delay-per-stage calculation circuit for determining a delay-per-stage of the delay line using a first clock input and a sampling frequency input; and
a pulse generating circuit for generating the pulse output based on the delay of each stage by using the delay line;
wherein the delay line receives a second clock input;
wherein the per-stage delay calculation circuit determines the per-stage delay of the delay line based on the operation of the replica delay line to receive the first clock input, wherein the pulse generation circuit selectively accesses a plurality of outputs of two of the plurality of stages of the delay line based on the per-stage delay and a selected pulse width to generate the pulse output.
27. The circuit of claim 26 wherein the delay-per-stage calculation circuit comprises:
A time to digital converter for sampling an output of the replica delay line based on the sampling frequency input.
28. The circuit of claim 27 wherein the delay-per-stage calculation circuit comprises:
a cycle stage calculator for determining a number of sampling frequency cycles within a cycle of the sampled output of the replica delay line using the sampled output of the replica delay line.
29. The circuit of claim 28 wherein the delay per stage is determined based on the determined number of sampling frequency periods and the frequency of the first clock input.
30. The circuit of claim 26 wherein the second clock input has a lower frequency than the first clock input.
31. The circuit of claim 26 wherein the second clock input has a lower frequency than both the first clock input and the sampling frequency input.
32. The circuit of claim 26 wherein the first clock input operates at a frequency of 4 to 5 GHz.
33. The circuit of claim 26 wherein the first clock input operates at a frequency that is 10 to 100 times faster than the second clock input.
34. A method of generating a pulse output having a controllable pulse width, comprising:
accessing a delay line having a plurality of stages;
providing a first clock input to a replica delay line having a plurality of stages substantially identical to the delay line;
sampling an output of the replica delay line using a sampling frequency input;
determining a per-stage delay of the delay line based on operation of the replica delay line; and
the pulse output is generated using the delay line by providing a second clock input to the delay line based on the per-stage delay, wherein a plurality of outputs of both of the plurality of stages of the delay line are selectively accessed based on the per-stage delay and a selected pulse width to generate the pulse output.
35. The method as recited in claim 34, further comprising:
a number of sampling frequency periods within a cycle of the sampled output of the replica delay line is determined.
36. The method of claim 35 wherein the per-stage delay is determined based on the determined number of sampling frequency periods and the frequency of the first clock input.
37. The method of claim 34, wherein the second clock input has a lower frequency than both the first clock input and the sampling frequency input.
38. The method of claim 34 wherein the output of the replica delay line is sampled with a time-to-digital converter.
39. The method of claim 38 wherein a periodic stage calculator processes the samples from the time-to-digital converter to determine a delay indication measurement per stage.
40. The method of claim 39, wherein the per-stage delay of the delay line is determined from per-stage delay indication measurements.
41. A circuit for generating a pulse output having a controllable pulse width, comprising:
a delay line having a plurality of stages;
a delay-per-stage calculation circuit for determining a delay-per-stage of the delay line using a sampling frequency input; and
a pulse generating circuit for generating the pulse output by using the delay line and based on the per-stage delay;
wherein the delay line receives a fast frequency input;
wherein the per-stage delay calculation circuit determines the per-stage delay of the delay line based on operation of the delay line to receive the fast frequency input,
Wherein the pulse generation circuit selectively accesses the outputs of two of the plurality of stages of the delay line based on the per-stage delay and a selected pulse width to generate the pulse output.
42. The circuit of claim 41, further comprising an SR flip-flop that receives the outputs of the two of the plurality of stages and generates the pulsed output.
43. The circuit of claim 41, wherein the two of the plurality of stages are selected based on a selected pulse output width and the per-stage delay.
44. The circuit of claim 41, wherein the delay-per-stage calculation circuit comprises:
a time-to-digital converter for sampling an output of the delay line according to the sampling frequency input; and
a period stage calculator for determining a number of sampling frequency periods within a cycle of the sampled output of the delay line using the sampled output of the delay line.
45. A circuit for generating a pulse output having a controllable pulse width, comprising:
a delay line having a plurality of stages, wherein the delay line receives a second clock input;
A replica delay line having a plurality of stages substantially identical to the delay line;
a delay-per-stage calculation circuit for determining a delay-per-stage of the delay line using a first clock input, wherein the delay-per-stage calculation circuit determines the delay-per-stage of the delay line based on operation of the replica delay line, the second clock input having a frequency lower than a frequency of the first clock input; and
a pulse generating circuit for generating the pulse output by using the delay line and based on the per-stage delay;
wherein the pulse generation circuit selectively accesses outputs of two of the plurality of stages of the delay line based on the per-stage delay and a selected pulse width to generate the pulse output.
46. The circuit of claim 45 wherein the frequency of the second clock input is 10% lower than the frequency of the first clock input.
47. The circuit of claim 45, wherein the per-stage delay calculation circuit does not control the delay line in determining the per-stage delay of the delay line.
48. The circuit of claim 45, wherein the replica delay line has the same number of stages as the delay line.
49. The circuit of claim 45, further comprising an SR flip-flop that receives the outputs of the two of the plurality of stages and generates the pulsed output.
50. The circuit of claim 45, wherein the circuit is configured to determine the delay per stage exactly once per initialization of the circuit.
51. The circuit of claim 45, wherein the two of the plurality of stages are selected based on a selected pulse output width and the per-stage delay.
52. A method of generating a pulse output having a controllable pulse width, comprising:
determining a per-stage delay of a delay line based on a first clock input;
generating the pulse output using the delay line by providing a second clock input to the delay line based on the per-stage delay, the second clock input having a lower frequency than the first clock input; and
generating the pulse output from the frequency of the second clock input, wherein the frequency of the second clock input is substantially lower than the frequency of the first clock input used to determine the per-stage delay, wherein generating the pulse output comprises:
The outputs of the two stages of the delay line are selectively accessed based on the per-stage delay and a selected pulse width to generate the pulse output.
53. The method of claim 52, wherein determining the per-stage delay of the delay line comprises:
providing the first clock input to a replica delay line having a plurality of stages substantially identical to the delay line;
wherein the per-stage delay of the delay line is based on the operation of the replica delay line to receive the first clock input.
54. The method of claim 52, wherein the two stages are selected based on a selected pulse output width and the per-stage delay.
55. The method of claim 52, wherein the frequency of the second clock input is 10% lower than the frequency of the first clock input.
56. The method of claim 53, wherein the replica delay line has the same number of stages as the delay line.
57. The method of claim 52, wherein determining the per-stage delay of the delay line further comprises:
the delay of each stage is determined exactly once at each initialization.
58. A circuit for generating a pulse output having a pulse width of a controlled duration, comprising:
a delay line and a replica delay line, each having a plurality of stages;
a per-stage delay calculation circuit for determining a per-stage delay of the delay line by using a first clock input, wherein determining the per-stage delay of the delay line is based on operation of the replica delay line; and
a pulse generating circuit for generating the pulse output based on the delay of each stage by using the delay line, wherein the delay line receives a second clock signal,
wherein the pulse generation circuit selectively accesses the outputs of two of the plurality of stages of the delay line based on the per-stage delay and a selected pulse width to generate the pulse output.
59. The circuit of claim 58 wherein the replica delay line has a plurality of stages substantially identical to the delay line, and wherein the per-stage delay calculation circuit does not control the delay line in determining the per-stage delay of the delay line.
60. The circuit of claim 58 wherein the frequency of the second clock input is substantially lower than the frequency of the first clock input.
61. The circuit of claim 60 wherein the frequency of the second clock input is 10% lower than the frequency of the first clock input.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201962867328P | 2019-06-27 | 2019-06-27 | |
| US62/867,328 | 2019-06-27 | ||
| US16/733,379 US11031927B2 (en) | 2019-06-27 | 2020-01-03 | Systems and methods for generating a controllable-width pulse signal |
| US16/733,379 | 2020-01-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112152596A CN112152596A (en) | 2020-12-29 |
| CN112152596B true CN112152596B (en) | 2024-03-08 |
Family
ID=73888613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010587448.3A Active CN112152596B (en) | 2019-06-27 | 2020-06-24 | Circuit and method for generating pulse output |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112152596B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101496280A (en) * | 2006-02-22 | 2009-07-29 | 爱萨有限公司 | Self-Calibrating Digital Pulse Width Modulator (DPWM) |
| CN101578527A (en) * | 2007-01-11 | 2009-11-11 | 国际商业机器公司 | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops |
| CN102035514A (en) * | 2010-11-11 | 2011-04-27 | 东南大学 | Control method for digital pulse width modulation (DPWM) circuit |
| TW201136171A (en) * | 2009-04-06 | 2011-10-16 | Honeywell Int Inc | Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line |
| TW201332294A (en) * | 2012-01-31 | 2013-08-01 | Univ St Johns | Counter based digital pulse width modulation device could scalable the resolution |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6998928B2 (en) * | 2003-05-06 | 2006-02-14 | Motorola, Inc. | Digital pulse width modulation |
| US7439787B2 (en) * | 2006-07-27 | 2008-10-21 | Freescale Semiconductor, Inc. | Methods and apparatus for a digital pulse width modulator using multiple delay locked loops |
| US7915938B2 (en) * | 2008-10-31 | 2011-03-29 | Exar Corporation | Multi-channel digital pulse width modulator (DPWM) |
-
2020
- 2020-06-24 CN CN202010587448.3A patent/CN112152596B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101496280A (en) * | 2006-02-22 | 2009-07-29 | 爱萨有限公司 | Self-Calibrating Digital Pulse Width Modulator (DPWM) |
| CN101578527A (en) * | 2007-01-11 | 2009-11-11 | 国际商业机器公司 | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops |
| TW201136171A (en) * | 2009-04-06 | 2011-10-16 | Honeywell Int Inc | Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line |
| CN102035514A (en) * | 2010-11-11 | 2011-04-27 | 东南大学 | Control method for digital pulse width modulation (DPWM) circuit |
| TW201332294A (en) * | 2012-01-31 | 2013-08-01 | Univ St Johns | Counter based digital pulse width modulation device could scalable the resolution |
Non-Patent Citations (1)
| Title |
|---|
| 宋瑞峰.DC-DC开关转换器中DPWM模块的电路优化设计及研究.《中国优秀硕士学位论文全文数据库 信息科技辑》.2019,I135-572. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112152596A (en) | 2020-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109387776B (en) | Method of measuring clock jitter, clock jitter measuring circuit, and semiconductor device | |
| US7816960B2 (en) | Circuit device and method of measuring clock jitter | |
| EP2944022B1 (en) | Integrated circuit comprising circuitry to determine settings for an injection-locked oscillator | |
| US9541591B2 (en) | Periodic signal measurement using statistical sampling | |
| US7930121B2 (en) | Method and apparatus for synchronizing time stamps | |
| US10352997B2 (en) | Method of measuring clock jitter, clock jitter measurement circuit, and semiconductor device including the same | |
| US11539354B2 (en) | Systems and methods for generating a controllable-width pulse signal | |
| US8786347B1 (en) | Delay circuits for simulating delays based on a single cycle of a clock signal | |
| US11888480B2 (en) | Method and apparatus for synchronizing two systems | |
| CN103645379A (en) | TTL signal frequency hopping monitoring system and method | |
| JP2017200162A (en) | Temporal digital converter of high resolution | |
| CN112152596B (en) | Circuit and method for generating pulse output | |
| CN104079265A (en) | High-speed clock duty ratio detection system | |
| US20110249702A1 (en) | Method and device for estimating parameters of a system for spreading the spectrum of a clock signal | |
| CN116131821A (en) | High-precision delay clock calibration circuit and chip | |
| WO2022110235A1 (en) | Chip and clock detection method | |
| JP2018189410A (en) | Jitter measurement circuit | |
| US6944099B1 (en) | Precise time period measurement | |
| CN203951450U (en) | High-frequency clock duty ratio detection system | |
| CN111371453A (en) | Signal period measuring circuit and method | |
| US7475270B1 (en) | System and method for waveform sampling | |
| US20060269030A1 (en) | Phase lock loop jitter measurement | |
| CN107317581B (en) | Time-to-digital converter with high resolution | |
| Li et al. | A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range | |
| CN116991227A (en) | Device for acquiring high-precision signals, soC chip and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |