CN1985371A - 包含集成电路的电子器件 - Google Patents

包含集成电路的电子器件 Download PDF

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CN1985371A
CN1985371A CNA2005800235260A CN200580023526A CN1985371A CN 1985371 A CN1985371 A CN 1985371A CN A2005800235260 A CNA2005800235260 A CN A2005800235260A CN 200580023526 A CN200580023526 A CN 200580023526A CN 1985371 A CN1985371 A CN 1985371A
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chip
electronic device
die pad
projection
pch
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CN1985371B (zh
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J·-C·G·西克斯
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Sheng Investment Co., Ltd.
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Koninklijke Philips Electronics NV
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Abstract

电子器件(ICD)包括：将该电子器件耦合至信号地线的信号地线接触件(LD1)、管芯衬垫和集成电路。管芯衬垫(DPD)具有突起(PTR3)，该突起电耦合至信号地线接触件。该集成电路(PCH)具有面向并电耦合于该管芯衬垫的突起的接触垫(GP2)。

Description

包含集成电路的电子器件
技术领域
本发明一方面涉及一种包括一集成电路的电子器件，该电子器件例如可以构成高频信号处理器。本发明的其他方面涉及一种制造这种电子器件的方法和包括这种电子器件的信号处理设备。
背景技术
电子器件可具有如下结构。集成电路被安装在一具有***部分和内部部分的基底上，该***部分包括用于将该电子器件耦合到其它电子器件的多个接触件。这些接触件中的至少一个为信号地线接触件。该集成电路的接触垫电耦合至该底板***部分的接触件。集成电路本身位于基底的内部部分。该集成电路可以构成多个电子部件叠置体的一部分，该叠置体可包括电耦合至集成电路的去耦电容器，且该叠置体可安装在基底的内部部分上。
美国专利6227260描述了一种集成电路器件，其包括和半导体芯片及平面连接元件共平面的平面去耦电容器，该平面连接元件具有多个连接指针(bond finger)、同中心的电源与接地环。该半导体芯片位于同中心的电源与接地环内，且该平面去耦电容器被定位于靠近该平面半导体芯片。连接线将平面半导体芯片电耦合至平面去耦电容器。
发明内容
根据本发明的一方面，电子器件包括具有突起的管芯衬垫，其管芯衬垫被耦合至外部的地线。位于第一芯片的第一侧上的接触垫面对且被电耦合至管芯衬垫的突起。在第一侧第二芯片(ACH)通过接触垫被电耦合至第一芯片第一侧的另外的接触垫，同时在第二侧它面向管芯衬垫。
本发明考虑到以下方面：电子器件中电路的高频性能取决于将电路耦合至地线的电通路，。电通路的电感越低，电路的高频性能越好。对于芯片上芯片(chip-on-chip)封装，也称为层叠管芯封装，从第一芯片到地线的短的电通路要求不那么明显。这是考虑到芯片上芯片封装的设计要求。进一步地，第一芯片常常具有实质上比第二芯片大的横向扩展；实际上它被作为功能内插器。突起用来构成从作为中间地线的管芯衬垫至第一芯片的短且直接的连接。
对其而言到地的短连接及其重要的电路的例子包括去耦电容器、防止静电放电的保护器件，以及电感等等。
优选的，具有从第二芯片的第二侧至管芯衬垫的电和/或热连接。然而，这不是明显必需的；突起可被作为替代部件。此时装配的问题将会减少。虽然不是明显必需的，但管芯衬垫为通常的矩形仍然是合适的；首先是考虑到板的布局，其次，作为具有突起的矩形管芯衬垫与仅仅是突起相比，其在机械上更稳定，也更容易处理。
在该器件的一个有利实施例中，突起被形成为至少部分围绕第二芯片的壁。在该实施例中，接地突起可形成围绕第二芯片的法拉第笼，以保护该第二芯片不受电磁干扰。
在一个合适的实施例中该第一芯片仅包括无源功能。这样的无源功能包括电阻器，电感器和电容器，以及可选择的二极管，例如针(pin)或齐纳二极管。另外，也可存在MEMS元件和天线。同时低通滤波器(basspandfilters)、阻抗匹配网络、耦合器、反馈和波段转换电路也可以被设计在第一芯片中。该第一芯片适合地设置在半导体衬底上，但是也可替换使用绝缘材料的衬底。半导体衬底的优点在于它的热膨胀系数与第二半导体芯片的热膨胀系数相等。结果，整个电子器件的热稳定性有了相当大的改进。用高阻硅作为衬底可以获得好的效果。该材料在高频时具有绝缘衬底的性能。
第二芯片适宜为半导体器件，例如放大器、收发器或驱动芯片。可选地，其可以是滤波器，例如，体声波滤波器、开关元件或阵列，例如包括微机电***(MEMS)元件的器件，如磁阻传感器的传感器，等等。如果希望的话，其也可以是分离的存储芯片。换句话说，这些是集成在第一芯片中的在技术上不可行或商业上无吸引力的芯片。可以理解，本发明的器件中能够提供多于一个的第二芯片。实际上，假如有更多的第二芯片，第一芯片将会横向延伸远超过这些第二芯片，其对固有接地和局部接地的要求仅是做的更大一些。
本领域技术人员均知，管芯衬垫为引线框架(leadframe)的合适部分。优选QFN型的引线框架，因为其具有适合安装SMD的引线。这里更优选HVQFN-引线框架。在近来的发展中，这种引线框架通过牺牲层来形成，该牺牲层从引线框架的底侧部分或全部去除。可选地，管芯衬垫可分离地设置。第一芯片上仍然具有阵列状配置的端子，并且端子设置有焊料凸点。这样的封装就其本身来言是芯片尺寸封装。
在更有利的实施例中，在第一芯片的第二侧存在一屏蔽。所述屏蔽适合地通过第一芯片中的通孔连接到突起。形成与沟槽一起用作电容元件的通孔的技术被描述在未公开的申请EP04300132.0(PHNL040226)中。随意地，从地到第一芯片第二侧的连接可构成用于其他功能或设置在第一芯片的这个第二侧的芯片的接地。
在本发明的另一方面中，引线框架包括具有突起的管芯衬垫和多个引线。从图和上面的描述可以清楚看出，引线框架的实施方式是本发明的基本实施方式，本发明在这里被清楚地体现。
在本发明的另一方面中，提供一种制造依据本发明的电子器件的方法，详细的如权利要求2所述，该方法包括以下步骤：
将第二芯片的第二侧安装至成型的组件下面的管芯衬垫上，以及
用凸点将第一芯片和组件装配在一起。
已经发现，通常的芯片上芯片结构作为一个整体安装至引线框架是困难的。在一个步骤中，必须进行两个连接，并且应该释放压力。这些连接是指在第二芯片和管芯衬垫之间的连接，以及在第一芯片上的端子和引线之间的连接。这里的第一芯片和引线之间的距离比管芯衬垫和第二芯片之间的距离大的多。
在本发明的方法中，首先，制作一个组件，其使得在下一步的装配步骤中将被安装的两个表面是较平的。这有助于合适的装配。
本发明的这些和其它方面将参考附图在后面被详细地描述。
附图说明
图1是说明高频放大器的图；
图2是说明高频放大器的集成电路器件的截面图；
图3是说明集成电路器件的安装和连接基底的顶视图；
图4是说明制造集成电路器件的流程图；
图5A-5E是说明该方法中间产品的截面图。
具体实施方式
图1中示出了一种高频放大器HFA。该高频放大器包括输入接头INP、其上安装有各种元件的印刷电路板、输出接头OUT和外壳CAS。集成电路器件ICD是上述元件之一。集成电路器件ICD经印刷电路板PCB耦合至其它元件。集成电路器件ICD包括放大电路，其和印刷电路板PCB上的其它元件一起，放大输入接头INP处的高频信号，以在输出接头OUT处获得放大的信号。
图2示出了集成电路器件ICD。图2是集成电路器件ICD的截面示意图。集成电路器件ICD包括安装和连接基底MCB、两个信号处理芯片ACH1、ACH2和无源元件芯片PCH。这些元件被提供机械保护的模制化合物(mold compound)MLD覆盖。安装和连接基底MCB优选包括具有较高的电和热传导率的材料，例如，安装和连接基底MCB可由包括铜的合金形成。
安装和连接基底MCB包括引线框架LFR和管芯衬垫DPD。引线框架LFR具有各种电引线LD，用于将集成电路器件ICD连接至其它电子器件。电引线LD1构成至信号地线GND的连接。电引线LD2构成至电源电压VCC的连接。两个信号处理器芯片ACH被安装在管芯衬垫DPD上。管芯衬垫包括不同的突起PTR。突起PTR1和PTR2限定了一个用于放置信号处理芯片ACH1的凹槽，突起PTR2和PTR3限定了用于放置信号处理芯片ACH2的另一个凹槽。
无源元件芯片PCH位于信号处理芯片ACH的顶部。无源元件芯片PCH包括信号地线垫GP、电源电压垫VP、导电屏蔽SHD和填充有导电材料的通孔TRH。通孔TRH构成导电屏蔽SHD和无源元件芯片PCH的信号地线垫GP1之间的电连接。无源元件芯片PCH进一步包括去耦电容器。去耦电容器电耦合至信号地线垫GP1和电源电压垫VP1之间。另一去耦电容器被电耦合至信号地线垫GP1和电源电压垫VP2之间。无源元件芯片PCH可进一步包括电子元件，例如二极管，用于提供防止静电放电的保护。因此，放电产生的电流将经由低阻抗通路流向信号地线，其防止了破坏性电压峰值的产生。
集成电路器件ICD包括各种焊料接头SC，用于引线框架LFR、管芯衬垫DPD、信号处理芯片ACH和无源元件芯片PCH之间的相互电耦合。焊料接头SC1将无源元件芯片PCH的导电屏蔽SHD电耦合至电引线LD1以形成至信号地线GND的连接。焊料接头SC2将无源元件芯片PCH的电源电压垫VP1电耦合至电引线LD2以形成至电源电压VCC的连接。电源电压垫VP1和电源电压垫VP2在无源元件芯片中互相电连接。信号处理芯片ACH经由焊料接头SC3和SC4、通孔TRH和无源元件芯片PCH的导电屏蔽SHD、以及焊料接头SC1电耦合至信号地线。信号处理芯片ACH1经由焊料接头SC5、无源元件芯片PCH的电源电压通路VP1、焊料接头SC2电耦合至电源电压VCC。信号处理芯片ACH2经由焊料接头SC6、无源元件芯片PCH的电源电压通路VP2电耦合至电源电压VCC，其和电源电压通路VP1以及焊料接头SC2互连。
管芯衬垫DPD在其粘附于印刷电路板的底侧上电耦合至地。在本实施例中，存在从一个地线接触件(管芯衬垫DPD)到另一地线接触件(信号地线GND)的连接，其可作为适合的屏蔽使用。该连接包括焊料接头SC7、金属化通孔TRH、无源元件芯片PCH的导电屏蔽SHD和焊料接头SC1。无源元件芯片PCH的信号地线接触垫GP2经由焊料接头SC8电耦合至管芯衬垫DPD的突起PTR3。
图3示出了图1所示的集成电路器件ICD的安装和连接基底MCB。图3是安装和连接基底MCB的顶视图。突起PTR形成确定两个凹槽CAV的壁，这两个凹槽用于容纳如图2所示的信号处理芯片ACH。导电引线LD2具有至管芯衬垫DPD的连接件ATT，其构成电耦合。
焊料接头SC、无源元件芯片的导电屏蔽SHD和通孔TRH，包括突起PTR的管芯衬垫DPD，和连接件ATT，在高频下具有相对较低的阻抗。因此，高频电流将优选流过这些元件。这样的电流可产生的任何高频电压将具有较合适的振幅。从而，集成电路器件内的电路将具有满意的高频性能。电路之间的任何信号串扰将比较合适。此外，壁状的突起PTR构成了防止电磁干扰的屏蔽。实际上，壁状的突起PTR和管芯衬垫DPD的空余部分及无源元件芯片PCH结合形成一个法拉第笼，其中该无源元件芯片PCH具有导电屏蔽SHD。这进一步有利于获得满意的集成电路器件ICD的高频性能。
图4和图5A-5E示出了制造图2示出的集成电路器件的方法。图4示出了该方法的多个步骤ST。图5A-5E示出了该方法的中间产品。图5A示出了具有切割线CL1和CL2的金属带MTS。金属带MTS具有上表面UF和下表面LF。
在蚀刻步骤ST1中，金属带MTS的上表面UF根据预定图案被蚀刻。金属带MTS的下表面LF也根据预定图案被蚀刻。两表面的蚀刻深度是上、下表面之间距离即金属带MTS厚度的约2/3。
图5B示出了由蚀刻步骤ST1形成的安装带。在蚀刻步骤ST1中已经形成了引线框架LFR和管芯衬垫DPD。在蚀刻步骤ST1中也已经形成了管芯衬垫DPD中确定凹槽的壁状突起PTR。切割线LC1和LC2之间的部分构成了根据本发明MCB的安装和连接基底。
在焊料准备步骤ST2中，引线框架LFR的电引线LD和管芯衬垫DPD的突起PTR上设置有焊球SB。图5C示出了由焊料准备步骤ST2形成的准备好焊料的安装带。
在芯片上芯片安装步骤ST3中，无源元件芯片PCH和信号处理芯片ACH相互安装在一起。图5D示出了由芯片上芯片安装步骤ST3形成的芯片组件。
在安装步骤ST4中，图5D所示的芯片组件被安装在如图5C所示的准备好焊料的安装带上。信号处理芯片ACH被放置在凹槽中且被可选择的安装在管芯衬垫上。加热准备好焊料的安装带的焊球SB以形成焊料连接。
图5E示出了由安装步骤ST4形成的芯片安装带。在未示出的其他步骤中，模制化合物可被应用到芯片安装带上。沿着切割线CL1以及沿着切割线CL2的切割形成如图2所示的集成电路器件。
上面参照附图的详细描述示出了以下特征。电子器件(集成电路器件ICD)包括第一芯片(PCH)和耦合至第一芯片(PCH)的第二芯片(ACH)。第一芯片(PCH)的接地不仅仅通过以引线方式的常规信号地线接触件获得，而且也可以另外以到管芯衬垫上(DPD)的突起(PTR3)的接触垫(GP2)的方式来获得。这个接触垫(GP2)位于中间，因此比常规接地更接近于第一芯片和/或第二芯片中的元件。这样，其构成了具有减小了阻抗的改进接地连接。此外，地线接触件的存在允许为第二芯片(ACH)或至少部分第一芯片(PCH)提供屏蔽。
上面参照附图的详细描述进一步示出了下面可选的特征。面向且电耦合至管芯衬垫(DPD)的突起(PTR3)的接触垫(信号地线垫GP2)位于第一芯片(无源元件芯片PCH)的中央区域。该中央区域是位于由第一芯片(PCH)上的多个接触垫(VP1、GP3)所定义的***区域内的区域，该多个接触垫用于将第一芯片连接至引线(LD)。因此面向突起的接触垫具有更多或更少的中心位置。这样，第一芯片(PCH)内的电路可经由相对较短的连接被耦合至接触垫，因而耦合至地。该连接越短它的电感越低。因此，上述描述的特征可获得高频性能的进一步改进。
上面参照附图的详细描述进一步示出了下面可选的特征。电子器件(集成电路器件ICD)包括安装于集成电路(无源元件芯片PCH)和管芯衬垫(DPD)之间的***集成电路(信号处理芯片ACH1或ACH2)。其容许在不同芯片之间的功能划分，从而可以获得更好的性价比。
上面参照附图的详细描述进一步示出了下面可选的特征。集成电路(无源元件芯片PCH)之一包括电耦合至其它集成电路(信号处理芯片ACH)的去耦电容器。其允许具有相对低阻抗的电去耦通路以进一步有助于获得好的高频性能。
上面参照附图的详细描述进一步示出了下面可选的特征。管芯衬垫(DPD)的突起(PTR3)被形成为至少部分围绕***集成电路(信号处理芯片ACH)的壁。壁状的突起构成法拉第笼以进一步有助于获得好的高频性能。
先前描述的特征可被以多种不同的方式实现。为了说明这一点，简要描述一些可替代的方式。该集成电路可以是电子器件包括的唯一的集成电路，或者或者甚至是唯一的电子元件。集成电路可包括一个或多个信号处理电路。突起不是必需形成为壁；它们可以具有任意形状。突起可以形成为例如棒、圆柱体、立方体或锥体。面向管芯衬垫的突起的集成电路接触垫可利用例如导电粘结剂被电耦合。需进一步指出，根据本发明的电子器件可应用于任何类型的信号处理装置中。图1中示出的高频放大器仅是一个示例。该电子器件还可被应用于例如处理高速数据的计算机或数字信号处理器中。
进一步地，先前参考附图详细描述的具体实施例可以以许多不同的方式实施。为了说明这一点，简要描述一些可替换方案。图2所示的任何信号处理芯片ACH可被不同类型的电子元件所代替。也可以不用一个或多个电子元件来替换信号处理芯片ACH而将其省略。在这样的可选实施例中，无源元件芯片PCH可以被这样一个芯片替换，该芯片包括信号处理电路和一个或多个例如去耦电容器的无源元件。同样地也可以用一个有源元件芯片替换无源元件芯片PCH以及用一个或多个无源元件芯片替换信号处理芯片ACH。
需要进一步指出的是，导电屏蔽和无源元件芯片PCH上的通孔TRH可以被省略。管芯衬垫DPD可经图3所示的连接件ATT耦合至单独构成信号地线GND的电引线LD1。
如图4所示的蚀刻步骤ST1可跟随一个变形步骤。在该步骤中，蚀刻过的金属带被变形至一定程度以如图2所示地相对彼此来定位引线框架和管芯衬垫。也可以用其他步骤代替蚀刻步骤，其中使用不同的技术使金属带MTS形成安装和连接基底MCB。例如，安装和连接基底MCB可用一个印模机形成，其以机械动作而不是化学反应从金属带MTS上移去材料。进一步地，也可以首先将信号处理芯片ACH单独地安装到安装和连接基底MCB上，然后在将无源元件芯片PCH固定到信号处理芯片ACH上时，将无源元件芯片PCH安装到安装和连接基底MCB上。
利用多项硬件和/或软件，有多种方式来实现各功能。基于这种考虑，附图只是概略性的，每幅图仅代表本发明的一种可能的实施例。因此，尽管附图将不同功能显示为不同模块，但决不排除单项硬件或软件执行多种功能。也不排除多项硬件和/或软件的组合来执行一种功能。
在参考附图详细说明的示例之前的描述只是对本发明的举例说明而非对本发明的限制。有多种可替换方案落入了附加权利要求的保护范围。权利要求中的附图标记不构成对权利要求的限制。术语“包括”并不排除权利要求列举之外的其它元件或步骤的存在，元件或步骤之前的限定语“一”并不排除多个这样元件或步骤的存在。

Claims (10)

1.一种电子器件(ICD)包括：
管芯衬垫(DPD)，其具有突起(PTR3)并被耦合至外部地线；
第一芯片(PCH)，其在第一侧具有接触垫(GP2)，该接触垫面向并电耦合至管芯衬垫(DPD)上的突起(PTR3)；
第二芯片(ACH)，具有第一侧和相对的第二侧，在其第一侧上具有接触垫，该接触垫面向并电耦合至第一芯片的第一侧上的接触垫，在其第二侧上第二侧面向管芯衬垫。
2.根据权利要求1所述的电子器件，其中管芯衬垫电耦合至第二芯片的第二侧。
3.根据权利要求1所述的电子器件，其中管芯衬垫(DPD)上的突起(PTR3)被形成为至少部分围绕第二芯片(ACH)的壁。
4.根据权利要求1所述的电子器件，其中第一芯片(PCH)具有耦合至外部板的端子，所述端子位于第一芯片(PCH)的第一侧上。
5.根据权利要求4所述的电子器件，其中端子上具有焊球以形成芯片尺寸封装。
6.根据权利要求4所述的电子器件，其中该端子被耦合至引线(LD)，所述引线和所述管芯衬垫作为部分的引线框架。
7.根据权利要求4所述的电子器件，其中第一芯片包括从第一侧延伸至相对的第二侧的通孔，且在第二侧具有导电屏蔽层。
8.一种信号处理装置(HFA)，其包括如权利要求1所述的电子器件(ICD)，和将该电子器件耦合至所述信号处理装置中其它电子器件的衬底(PCB)。
9.一种引线框架，包括管芯衬垫(DPD)和多个引线(LD)，其中管芯(DPD)衬垫上具有突起(PTR3)。
10.一种制造如权利要求2所述的电子器件(ICD)的方法，包括以下步骤：
将第二芯片的第二侧安装至成型组件下面的管芯衬垫上，以及
用凸点将第一芯片和该组件装配在一起。
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WO2006008679A3 (en) 2006-08-24
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US7545026B2 (en) 2009-06-09
ATE445232T1 (de) 2009-10-15
DE602005017041D1 (de) 2009-11-19
US20080191361A1 (en) 2008-08-14
CN1985371B (zh) 2011-12-28
EP1769533A2 (en) 2007-04-04

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