CN1979200A - Method for parallelly detecting multiple chips of synchronous communication - Google Patents
Method for parallelly detecting multiple chips of synchronous communication Download PDFInfo
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- CN1979200A CN1979200A CN 200510111289 CN200510111289A CN1979200A CN 1979200 A CN1979200 A CN 1979200A CN 200510111289 CN200510111289 CN 200510111289 CN 200510111289 A CN200510111289 A CN 200510111289A CN 1979200 A CN1979200 A CN 1979200A
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Abstract
The invention discloses a method to take multi-chip parallel testing by using synchronous communication chip. It includes the following steps: connecting bidirectional shift register onto a testing channel, inputting data on one testing channel of testing machine to tested chip by the method of series to parallel, inputting the data from plural tested chips to a testing channel by the method of parallel to series, taking data process to the read data to gain the testing result of the chips. The invention could improve testing efficiency of testing chip and lower testing time and cost.
Description
Technical field
The present invention relates to a kind of LSI testing method, particularly relate to a kind of method of parallelly detecting multiple chips of synchronous communication.
Background technology
Along with the development of large scale integrated circuit, circuit becomes increasingly complex, and the needed test duration is also just more and more longer, must improve the same survey number of multicore sheet (being measured device) concurrent testing in order to save the test duration.Yet the test channel number of existing tester (I/O mouth) is limited, makes the same survey number of multicore sheet concurrent testing be restricted, and can not infinitely improve with surveying number.Formed a bottleneck to improving testing efficiency like this.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method of parallelly detecting multiple chips of synchronous communication, it can realize that single chip testing passage is to multicore sheet concurrent testing, improve the same quantitation of multicore sheet concurrent testing, improve testing efficiency, reduce test duration and cost.
For solving the problems of the technologies described above, the method of parallelly detecting multiple chips of synchronous communication of the present invention, at first, bidirectional shift register is connected on the test channel of tester, with the data on the test channel of tester, change method also by string and be input on all measured devices; Then, by shift register the data of exporting on a plurality of measured devices are input on the test channel of tester by the method for also changeing string; By tester the data of reading in are carried out the pass/fail result that data processing obtains each measured device at last.
Adopt method of the present invention can obviously shorten the test duration of chip.For example adopt general tester to test simultaneously to 16 chips.And 16 chip simultaneous tests can further be extended to 64 chip simultaneous tests after adopting method of the present invention, testing efficiency has reached about 3～4 times of 16 chip simultaneous tests, it is about about 70% that this means that also the test duration of one piece of chip has shortened, and greatly reduces the testing cost of chip.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Accompanying drawing is to adopt method of the present invention to carry out with the synoptic diagram of surveying.
Embodiment
The method of parallelly detecting multiple chips of synchronous communication of the present invention realizes that to the synchronous communication chip single chip testing passage carries out concurrent testing to the multicore sheet, and it can realize a plurality of chips of synchronous communication chip are tested simultaneously to greatest extent.
The present invention is by installing four two-way input and output shift registers additional on the original single chip testing passage of tester (I/O mouth), with the data on the test channel of tester, by string change and method be input on a plurality of probes on the probe, enter data into then on all measured devices.Equally, by shift register the data of exporting on a plurality of measured devices are input on the test channel of tester by the method for also changeing string.Detailed process is, utilizes data setup time to export the data of concurrent testing successively on the I/O mouth, and (be data effectively before) is with each data parallel output before rising edge clock.
When the measured device output signal, shift register is set to input state earlier, (PAD is the thin slice of an aluminium on each input/output port on the chip with the PAD of each measured device, probe will be pricked in the above during test, be used for connecting external pin during encapsulation) signal is input to an I/O mouth of tester successively by shift register.On the ECR that on the tester I/O mouth input signal is write successively tester (ERROR CATCH ram error capturing memory), four corresponding on shift register measured devices are carried out the judgement of pass/fail by the last data of ECR are handled realization.
Shown in the drawings is to adopt method of the present invention to carry out an embodiment of many chip simultaneous tests, bidirectional shift register is made on the probe for a kind of product use, can expand the test resource of an original test channel, make original two test channel can only carry out the same survey of two chips.Can carry out the same survey of 8 chips through increasing shift register, even can also be further by increasing the same survey number of chip under the situation of frequency and test duration permission.
In test process, earlier data were moved to left before effective time in data by tester, the data that needs are input on each DUT (measured device) move on on each DUT.Then, be in input state, the data on the shift register are input on the chip under test, realize with of PATTERN (test vector) input test of a test channel a plurality of measured devices with this by the clock enabling signal measured device.
When chip is in output state, make shift register be in parallel input state earlier, the output of a plurality of measured devices is input on the shift register.Then, before the next cycle of chip arrives, the data on the register are moved to right, realize with of the collection of a test channel to a plurality of measured device chip datas.
At last, the data with input deposit among the ECR of tester laterally storage continuously in.Horizontal width is the same survey number on the same test channel.Vertically reading of data and effect reference value relatively just can be judged the current vertically pass/fail result of this row chip under test successively as long as pass through when judging the measured device pass/fail.
Bidirectional shift register can be made on the probe and use for a kind of product, also can make the test interface plate and use for multiple product.
Claims (10)
1, a kind of method of parallelly detecting multiple chips of synchronous communication, it is characterized in that: at first, bidirectional shift register is connected on the test channel of tester,, changes method also by string and be input on all measured devices the data on the test channel of tester; Then, by shift register the data of exporting on a plurality of measured devices are input on the test channel of tester by the method for also changeing string; By tester the data of reading in are carried out the pass/fail result that data processing obtains each measured device at last.
2, the method for parallelly detecting multiple chips of synchronous communication as claimed in claim 1 is characterized in that: bidirectional shift register can be made on the probe and use for a kind of product, perhaps makes the test interface plate and uses for multiple product.
3, the method for parallelly detecting multiple chips of synchronous communication as claimed in claim 1, it is characterized in that: it is with the data on the test channel of tester that described string changes method also, be input on a plurality of probes on the probe, enter data into then on all measured devices.
4, the method for parallelly detecting multiple chips of synchronous communication as claimed in claim 1, it is characterized in that: method described and the commentaries on classics string is, utilize data setup time on the I/O of tester mouth, to export the data of concurrent testing successively, before rising edge clock, each data parallel is exported.
5, the method for parallelly detecting multiple chips of synchronous communication as claimed in claim 1, it is characterized in that: when the measured device output signal, earlier shift register is set to input state, is input to the pad signal of each measured device in the test channel of tester successively by shift register; On the tester test channel input signal is being write on the ECR of tester successively, handling, realizing judgement measured device pass/fail corresponding on the shift register by ECR is gone up data.
6, as the method for any one described parallelly detecting multiple chips of synchronous communication in the claim 1 to 5, it is characterized in that: in test process, earlier data were moved to left before effective time in data by tester, the data that needs are input on each measured device move on on each measured device, then, be in input state by the clock enabling signal measured device, data on the shift register are input on the measured device, realize with of the test vector input test of a test channel a plurality of measured devices with this.
7, as the method for any one described parallelly detecting multiple chips of synchronous communication in the claim 1 to 5, it is characterized in that: when measured device is in output state, make shift register be in parallel input state earlier, the output of a plurality of measured devices is input on the shift register.Then, before the next cycle of measured device arrives, the data on the shift register are moved to right, realize with of the collection of a test channel to a plurality of measured device data.
8, the method for parallelly detecting multiple chips of synchronous communication as claimed in claim 1 is characterized in that: the data that are input to tester deposit among the ECR of tester, laterally storage continuously; Horizontal width is the same survey number on the same test channel; Vertically reading of data and effect reference value relatively just can be judged the current vertically pass/fail result of this row measured device successively as long as pass through when judging the measured device pass/fail.
9, the method for parallelly detecting multiple chips of synchronous communication as claimed in claim 1 is characterized in that: the measured device that a test channel of tester can concurrent testing is 4,8,16 or 32.
10, the method for parallelly detecting multiple chips of synchronous communication as claimed in claim 1 is characterized in that: each test channel all can connect bidirectional shift register and expands on the tester.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101112895A CN100442069C (en) | 2005-12-08 | 2005-12-08 | Method for parallelly detecting multiple chips of synchronous communication |
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| CNB2005101112895A CN100442069C (en) | 2005-12-08 | 2005-12-08 | Method for parallelly detecting multiple chips of synchronous communication |
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| CN1979200A true CN1979200A (en) | 2007-06-13 |
| CN100442069C CN100442069C (en) | 2008-12-10 |
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Cited By (23)
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| CN101078746B (en) * | 2007-07-11 | 2010-06-23 | 凤凰微电子（中国）有限公司 | Border scanning test structure of multiple chip package internal connection and test method |
| CN101458294B (en) * | 2007-12-10 | 2011-05-04 | 上海华虹Nec电子有限公司 | Method for downloading user code in chip when multi-chip test by tester |
| CN102590736A (en) * | 2011-01-05 | 2012-07-18 | 上海华虹Nec电子有限公司 | Rapid test system and rapid test method for stacked chips |
| CN103187101A (en) * | 2013-03-19 | 2013-07-03 | 西安华芯半导体有限公司 | Compressed data output method for DRAM repair test |
| CN103267943A (en) * | 2013-04-24 | 2013-08-28 | 上海宏力半导体制造有限公司 | Integrated circuit testing device and integrated circuit testing method |
| CN103345944A (en) * | 2013-06-26 | 2013-10-09 | 上海宏力半导体制造有限公司 | Storage device and method for testing storage device through test machine |
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| CN103744009A (en) * | 2013-12-17 | 2014-04-23 | 记忆科技(深圳)有限公司 | Serial transmission chip test method, serial transmission chip test system and integrated chip |
| CN103869234A (en) * | 2012-12-12 | 2014-06-18 | 复格企业股份有限公司 | Chip testing structure, device and method |
| CN103916132A (en) * | 2014-03-28 | 2014-07-09 | 西安华芯半导体有限公司 | Function switching circuit applicable to chip testing |
| CN103916133A (en) * | 2014-03-28 | 2014-07-09 | 西安华芯半导体有限公司 | Circuit applicable to chip testing |
| CN103995523A (en) * | 2014-06-11 | 2014-08-20 | 上海温光自动化技术有限公司 | Electronic device and method for detecting device events |
| CN104133172A (en) * | 2014-08-08 | 2014-11-05 | 上海华力微电子有限公司 | Novel test development method for improving simultaneous test number |
| CN104637544A (en) * | 2015-01-31 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Test circuit and test method of memory |
| CN105807211A (en) * | 2016-05-11 | 2016-07-27 | 上海华虹宏力半导体制造有限公司 | Rapid write-in method for individualized values and integrated circuit testing method |
| CN105807208A (en) * | 2016-04-25 | 2016-07-27 | 航天科工防御技术研究试验中心 | Multi-port-based asynchronous composite test method |
| CN105891695A (en) * | 2014-05-07 | 2016-08-24 | 北京同方微电子有限公司 | IC card parallel test method based on single IO |
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| CN106291099A (en) * | 2016-07-29 | 2017-01-04 | 上海华岭集成电路技术股份有限公司 | Chip port frequency test method |
| CN109239576A (en) * | 2018-08-03 | 2019-01-18 | 光梓信息科技（上海）有限公司 | A kind of high speed optical communication chip test system and method |
| CN110398617A (en) * | 2018-04-25 | 2019-11-01 | 晶豪科技股份有限公司 | Test device and folding probe card test system |
| CN111983270A (en) * | 2020-07-30 | 2020-11-24 | 华润赛美科微电子(深圳)有限公司 | Expansion circuit, tester and test method |
| CN112305402A (en) * | 2020-02-27 | 2021-02-02 | 青岛众鑫科技有限公司 | Controller special for testing hybrid integrated circuit product |
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| CN101078746B (en) * | 2007-07-11 | 2010-06-23 | 凤凰微电子（中国）有限公司 | Border scanning test structure of multiple chip package internal connection and test method |
| CN101458294B (en) * | 2007-12-10 | 2011-05-04 | 上海华虹Nec电子有限公司 | Method for downloading user code in chip when multi-chip test by tester |
| CN102590736B (en) * | 2011-01-05 | 2014-07-09 | 上海华虹宏力半导体制造有限公司 | Rapid test system and rapid test method for stacked chips |
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| CN103187101A (en) * | 2013-03-19 | 2013-07-03 | 西安华芯半导体有限公司 | Compressed data output method for DRAM repair test |
| CN103267943A (en) * | 2013-04-24 | 2013-08-28 | 上海宏力半导体制造有限公司 | Integrated circuit testing device and integrated circuit testing method |
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| CN104637544B (en) * | 2015-01-31 | 2017-11-24 | 上海华虹宏力半导体制造有限公司 | The test circuit and method of testing of memory |
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| CN109239576A (en) * | 2018-08-03 | 2019-01-18 | 光梓信息科技（上海）有限公司 | A kind of high speed optical communication chip test system and method |
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