CN102590736A - Rapid test system and rapid test method for stacked chips - Google Patents
Rapid test system and rapid test method for stacked chips Download PDFInfo
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- CN102590736A CN102590736A CN2011100010067A CN201110001006A CN102590736A CN 102590736 A CN102590736 A CN 102590736A CN 2011100010067 A CN2011100010067 A CN 2011100010067A CN 201110001006 A CN201110001006 A CN 201110001006A CN 102590736 A CN102590736 A CN 102590736A
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Abstract
The invention discloses a rapid test system for stacked chips, which comprises an integrated circuit tester, a serial-to-parallel conversion circuit module and a comparison module; the integrated circuit tester is provided with a plurality of groups of channels, each group of channels is provided with an ordinal vector generator, each ordinal vector generator corresponds to a chip unit, and is controlled by a test bit controller, and a clock synchronization module provides synchronized clock signals for the test bit controller; the serial-to-parallel conversion circuit module which is integrated in a stacked chip is used for converting the serial connection between different chip units into parallel connection; and the comparison method is used for comparing response values and expectation values of the chip units and judging whether the stacked chip is a nondefective. The invention also discloses a rapid test method based on the system. According to the rapid test system and the rapid test method for stacked chips, the tester is redesigned, the vector generators are added, and different chip units are tested in parallel, so the stacked chip-testing time is shortened, and the testing efficiency is increased.
Description
Technical field
The present invention relates to large scale integrated circuit packaging and testing field, relate in particular to the system and method for the folded sealing chip of a kind of quick test.
Background technology
Folded sealing chip be with chip unit assembled package with difference in functionality in a package casing, it can reduce chip shared area on circuit board, improves the density of encapsulation, reduces the cost of encapsulation, can also realize the multifunction of device.
At present, to the packaging and testing of folded sealing chip, generally adopt the method for sequential testing; This is because the different chip units in the folded sealing chip need use different test vectors; And existing LSI testing appearance has only a sequential vector maker usually, therefore can only be as shown in Figure 1, chip unit is carried out the serial test singly; Like this; The test duration of whole folded sealing chip is exactly the summation of the test duration of all chip units, therefore, adopts this method of testing need expend the long test duration.
Summary of the invention
The technical matters that the present invention will solve provides a kind of fast testing system of folded sealing chip, and it can shorten the test duration of folded sealing chip, improves the efficient of test.
For solving the problems of the technologies described above, the fast testing system of folded sealing chip of the present invention comprises:
Integrated circuit tester disposes many group passages, a plurality of sequential vector maker, a plurality of test level controller and a clock synchronization module, every group of corresponding sequential vector maker of passage; The corresponding chip unit of each sequential vector maker is used to produce the test vector of this chip unit; Each test level controller is used to control a sequential vector maker; Clock synchronization module is used for to each test level controller synchronizing clock signals being provided;
String changes and circuit module, is integrated in folded sealing chip inside, is used for connected in series being converted into parallel connection the between the different chip units;
Comparison module is used for the response and the expected value of comparable chip unit, judges whether each chip unit and whole folded sealing chip are non-defective unit.
Another technical matters that the present invention will solve provides a kind of method for rapidly testing of the folded sealing chip of realizing based on said system.
For solving the problems of the technologies described above, the method for rapidly testing of folded sealing chip of the present invention may further comprise the steps:
1) sends synchronizing clock signals to each sequential vector maker;
2) the different test vector of each self-generating of sequential vector maker sends to folded sealing chip;
3) go here and there folded sealing chip inside changes and operation, converts connected in series between the chip unit into parallel the connection;
4) each test vector is sent to corresponding chip unit;
5) response and the expected value that chip unit are produced compare, and judge respectively whether each chip unit is non-defective unit;
6), judge comprehensively whether whole folded sealing chip is non-defective unit according to the judged result of step 5).
The fast testing system of folded sealing chip of the present invention and method; Through design test appearance again; Increase new test level controller and sequential vector maker; Realized concurrent testing, thereby greatly shortened the whole test duration of folded sealing chip, improved the testing efficiency of folded sealing chip the different chip units of folded sealing chip.
Description of drawings
Fig. 1 is existing folded sealing chip serial method of testing synoptic diagram;
Fig. 2 is a folded sealing chip parallel test method synoptic diagram of the present invention.
Embodiment
Understand for technology contents of the present invention, characteristics and effect being had more specifically, combine illustrated embodiment at present, details are as follows:
Present embodiment redesigns the existing integrated circuits tester; On tester, append and disposed a plurality of new test level controllers, a plurality of new sequential vector maker and a clock synchronization module; And all passages of tester are divided into many groups according to the chip unit number of folded sealing chip; Every group of corresponding sequential vector maker of passage, the corresponding chip unit of each sequential vector maker, and by the control of a test level controller; Clock between the different tests position is synchronous, then realizes by clock synchronization module.
Simultaneously; In order to realize the concurrent testing of different chip units; A string also need be designed in folded sealing chip inside to be changeed and circuit module; Be used in when test, connected in series between the different chip units be converted into parallel the connection, so that different chip units can carry out different vector control simultaneously from the outside.
In addition; The test macro of present embodiment also comprises a comparison module; Be used for each chip unit received and encourage the response that the back produces and the expected value of this chip unit to compare, judge whether each chip unit is non-defective unit, and whether comprehensively judge whole folded sealing chip in view of the above be non-defective unit.
The method that following correspondence is tested folded sealing chip fast with said system is done a detailed description again.
As shown in Figure 2; Among this embodiment; All passages of tester are divided into three channel group, and promptly channel group 1, channel group 2 and channel group 3 dispose a new sequential vector maker to each channel group; Be respectively sequential vector maker 1, sequential vector maker 1 and sequential vector maker 3, each sequential vector maker is corresponding to a chip unit.
During test, clock synchronization module sends synchronizing clock signals to three sequential vector makers respectively through three channel group, and the sequential vector maker produces different test vectors separately under the control of test level controller, send to folded sealing chip simultaneously.The inner string of folded sealing chip changes and circuit module converts connected in series between the chip unit into parallel the connection, then different test vectors is sent to different chip units.Chip unit is encouraged, and produces a response, and comparison module compares the response of each chip unit and the expected value of this chip unit one by one, judges whether both are identical, if identical, then this chip unit is judged to be non-defective unit.At last, comprehensively the result of determination of each chip unit judges whether whole folded sealing chip is non-defective unit, as long as the rule of judgement is to have a chip unit bad, then whole folded sealing chip just is judged as bad.
After adopting above-mentioned parallel test method; The test duration of whole folded sealing chip is just determined by the test duration of that the longest chip unit of test duration; Rather than the stack of all chip unit test durations, thereby significantly reduced test duration of folded sealing chip, significantly improved the efficient of test.
Claims (2)
1. the fast testing system of a folded sealing chip comprises integrated circuit tester, it is characterized in that:
This integrated circuit tester disposes many group passages, a plurality of sequential vector maker, a plurality of test level controller and a clock synchronization module, every group of corresponding sequential vector maker of passage; The corresponding chip unit of each sequential vector maker is used to produce the test vector of this chip unit; Each test level controller is used to control a sequential vector maker; Clock synchronization module is used for to each test level controller synchronizing clock signals being provided;
String changes and circuit module, is integrated in folded sealing chip inside, is used for connected in series being converted into parallel connection the between the different chip units;
Comparison module is used for the response and the expected value of comparable chip unit, judges whether each chip unit and whole folded sealing chip are non-defective unit.
2. the method for rapidly testing based on the folded sealing chip of system's realization of claim 1 is characterized in that, may further comprise the steps:
1) sends synchronizing clock signals to each sequential vector maker;
2) the different test vector of each self-generating of sequential vector maker sends to folded sealing chip;
3) go here and there folded sealing chip inside changes and operation, converts connected in series between the chip unit into parallel the connection;
4) each test vector is sent to corresponding chip unit;
5) response and the expected value that chip unit are produced compare, and judge respectively whether each chip unit is non-defective unit;
6), judge comprehensively whether whole folded sealing chip is non-defective unit according to the judged result of step 5).
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110001006.7A CN102590736B (en) | 2011-01-05 | 2011-01-05 | Rapid test system and rapid test method for stacked chips |
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| CN201110001006.7A CN102590736B (en) | 2011-01-05 | 2011-01-05 | Rapid test system and rapid test method for stacked chips |
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| CN102590736A true CN102590736A (en) | 2012-07-18 |
| CN102590736B CN102590736B (en) | 2014-07-09 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103076524A (en) * | 2012-12-31 | 2013-05-01 | 中国科学院微电子研究所 | Radiation effect testing method, device and system |
| CN103837823A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Product testing circuit |
| CN109633421A (en) * | 2018-11-27 | 2019-04-16 | 珠海欧比特宇航科技股份有限公司 | A kind of test method of SOC chip, device, equipment and storage medium |
| CN110045268A (en) * | 2019-05-07 | 2019-07-23 | 广东工业大学 | A kind of chip detecting system |
Citations (3)
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| JP2006177827A (en) * | 2004-12-24 | 2006-07-06 | Sharp Corp | Apparatus and method for testing semiconductor integrated circuit |
| CN1979200A (en) * | 2005-12-08 | 2007-06-13 | 上海华虹Nec电子有限公司 | Method for parallelly detecting multiple chips of synchronous communication |
| CN201576463U (en) * | 2009-12-03 | 2010-09-08 | 上海华虹Nec电子有限公司 | Device for producing and displaying bitmap information during embedded flash memory testing process |
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2011
- 2011-01-05 CN CN201110001006.7A patent/CN102590736B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006177827A (en) * | 2004-12-24 | 2006-07-06 | Sharp Corp | Apparatus and method for testing semiconductor integrated circuit |
| CN1979200A (en) * | 2005-12-08 | 2007-06-13 | 上海华虹Nec电子有限公司 | Method for parallelly detecting multiple chips of synchronous communication |
| CN201576463U (en) * | 2009-12-03 | 2010-09-08 | 上海华虹Nec电子有限公司 | Device for producing and displaying bitmap information during embedded flash memory testing process |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103076524A (en) * | 2012-12-31 | 2013-05-01 | 中国科学院微电子研究所 | Radiation effect testing method, device and system |
| CN103837823A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Product testing circuit |
| CN109633421A (en) * | 2018-11-27 | 2019-04-16 | 珠海欧比特宇航科技股份有限公司 | A kind of test method of SOC chip, device, equipment and storage medium |
| CN110045268A (en) * | 2019-05-07 | 2019-07-23 | 广东工业大学 | A kind of chip detecting system |
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| CN102590736B (en) | 2014-07-09 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140107 |
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