CN1967279A - Circuit for measuring synchronized sampler of flying capacitance - Google Patents

Abstract

This invention discloses a flying capacitance synchronous sampling and measurement circuit and method of measurement error correction, including synchronous sampling relay group, each of the two input terminal on a synchronous sampling relay connected to the nodes of a battery module. There is the same amount of AD converter relays fitted with synchronous sampling relay group. Each of the two input nodes of an AD converter is connected to each of the two output nodes of the corresponding synchronous sampling relay, paralleling a sampling maintain capacitance between the two input nodes. The two outputs of an AD conversion relay are connected to the input of a high input impedance differential operational amplifier. After proper evacuation, operational amplifier output signal is transmitted to AD converters. This invention achieves electrical isolated, multiple functional modules battery voltage synchronous sampling. Circuit is simple and high precision, facilitate the measurement channel expansion.

Description

Circuit for measuring synchronized sampler of flying capacitance

Technical field

The present invention relates to a kind of at power battery pack multimode voltage, current signal is isolated and the technology of synchro measure.

Background technology

The measurement of power battery pack module voltage, electric current need overcome the common mode voltage up to nearly hectovolt even several hectovolts, must adopt quarantine measures, could guarantee the operate as normal of metering circuit.

Currently used technology mainly contains two kinds:

1, adopts isolated amplifier, a plurality of module voltage and current signal are isolated.

The shortcoming that this method exists that cost height, volume are big, nonlinearity erron is big, need adjust or demarcate a plurality of isolated amplifiers.

2, adopt relay array and flying capacitance, realize the isolation and the measurement of signal by touring sampling.

Though this method can realize the isolation to the multichannel measurement signal, exist the shortcoming that to carry out synchronized sampling to multiple signals.

Because electrokinetic cell has characteristics such as load variations is fast, dynamic range is big in the course of the work, therefore, in the electrokinetic cell detection system, particularly in power battery management system, realize the synchro measure of measuring-signal, for the measurement of battery charge state (SOC), cell health state (SOH) and malfunction, estimate and diagnosis has very important using value.

Summary of the invention

In order to overcome the deficiency of above-mentioned two kinds of technology, the present invention proposes a kind of novel metering circuit.Adopt this metering circuit, not only can realize the isolation of signal, also can realize the synchro measure of multiple signals simultaneously, have that circuit is simple, cost is low, be convenient to demarcate, expand characteristics easily.

The technical solution adopted in the present invention is:

A kind of circuit for measuring synchronized sampler of flying capacitance, comprise synchronized sampling relay group, two input ends of each synchronized sampling relay are connected with the both positive and negative polarity of a battery module respectively, also be provided with AD switching relay group with the same relay quantity of synchronized sampling relay group, two output terminals of the sampling relay that two input ends of each AD switching relay are corresponding with connect respectively, and a sampling in parallel keeps electric capacity between these two input ends; Two output terminals of each AD switching relay are connected to the input end of a high input impedance differential operational amplifier, and the operational amplifier output signal is through suitably giving AD converter after the conditioning; Synchronized sampling relay group and each AD switching relay are controlled by a decoder driver circuit by CPU.

Between input end of described each sampling relay and the corresponding battery that is connected, can also connect one and import current-limiting resistance.

Wherein, the sampling relay adopts double-pole single-throw (D.P.S.T.) or double-throw normally opened relay, and the AD switching relay also can adopt double-pole single-throw (D.P.S.T.) or double-throw normally opened relay.

The preferred PhotoMOS relay of sampling relay group (Ksi) or AD switching relay (Kci).

Wherein, described decoder driver circuit is that n+1 selects 1 decoder driver circuit, and wherein n is the quantity of described AD switching relay (Kci) or sampling relay group (Ksi), promptly measures number of channels.

The principle of work of measurement data acquisition:

Select n synchronized sampling relay of 1 decoder driver circuit gating synchronized sampling relay group by CPU control n+1, the corresponding maintenance capacitor C of sampling is separately charged by n battery module.

After charging process enters stable state, select 1 decoder driver circuit to turn-off n synchronized sampling relay by CPU control n+1, at this moment, the voltage on n maintenance capacitor C of sampling is the synchro measure value of n the modular battery voltage in this moment.

Select 1 decoder driver circuit gating n AD conversion sampling relay successively by CPU control n+1 again, keep the voltage on the capacitor C to carry out taking turn sampling n sampling.By the AD of gating conversion sampling relay will sample keep voltage on the capacitor C send into high input impedance differential operational amplifier A through amplify or conditioning after, carry out AD by AD converter and change, thereby finish a synchronous acquisition of taking turns n channel signal.

For keeping the measured deviation that capacitor leakage current caused by PhotoMOS relay and sampling, the algorithm that can adopt the present invention to propose in embodiment is revised and is compensated by software.

By adopting this technology, the performance of electrokinetic cell detection system and power battery management system and technical indicator are improved in the following aspects:

1, realize the synchronized sampling of a plurality of modular battery voltages, lock in time, precision can reach in the 2ms, for internal resistance, prediction SOH, SOC and the condition diagnosing of measuring battery provides a kind of effective means.

2, the conditioning of voltage signal only needs a public modulate circuit to finish, and all voltage signals have on all four range and enlargement factor, is convenient to debugging, demarcates, and has guaranteed measuring accuracy and consistance, is convenient to industrialization and through engineering approaches.

3, realized the accurate measurement of signal in 0～full range, overcome other isolation measurement modes in the bad measuring error that causes of small signal region internal linear degree.

4, can realize measuring between the passage and the voltage isolation of battery voltage measurement end and measuring unit sqignal conditioning input end 400～600V, can effectively suppress common mode interference, improve precision and the stability measured, guarantee the safety of measuring unit.

5, quit work or during power down, measure the loop and be in off state, not the electric energy of consuming cells at measuring unit.

6, circuit simple, take up room for a short time, be convenient to measure the passage expansion, help the miniaturization of the system that realizes.

Description of drawings

Fig. 1 synchronized sampling hardware elementary diagram

Figure 21 5 passage circuit for measuring synchronized sampler schematic diagrams

Figure 31 0 passage circuit for measuring synchronized sampler schematic diagram

Embodiment

Following examples are used to illustrate the present invention; but be not used for limiting the scope of the invention; the those of ordinary skill in relevant technologies field; under the situation that does not break away from the spirit and scope of the present invention; can also make various variations and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be limited by every claim.

The synchronized sampling working principle of hardware:

As shown in Figure 1:

VBi (i=1,2 ... n) be the voltage of n modular battery in the electric battery,

VCi (i=1,2 ... be that n sampling keeps the voltage on the electric capacity n),

C keeps electric capacity for sampling, and ICL keeps the leakage current of capacitor C for sampling,

R is input current-limiting protection resistance,

KS1, KS2, KS3......KSn are synchronized sampling relay group,

KC1, KC2, KC3......KCn are AD conversion sampling relay,

Synchronized sampling relay and AD conversion sampling relay are double-pole single-throw (D.P.S.T.) and often drive the PhotoMOS relay, and the withstand voltage of PhotoMOS relay switch two ends can be selected according to the total voltage of electric battery, is generally 400V or 600V;

Select the turn-on and turn-off of 1 decoder driver circuit control synchronized sampling relay group and n AD conversion sampling relay by n+1 by CPU.

A is a high input impedance operational amplifier, input impedance 〉=2M Ω;

CS is that n+1 selects 1 decoder driver circuit.

If τ ch is the RC time constant, τ ch=RC

Tch keeps capacitor charging time for sampling,

Ton is a PhotoMOS relay turn on delay time,

Toff is a PhotoMOS relay turn-off delay time,

IJL is the shutoff leakage current of synchronized sampling relay and AD conversion sampling relay

TAD is that AD converter is finished 1 required time of passage AD conversion.

T finishes once all sampling periods of channel measurement

When circuit carried out data acquisition, at first with the conducting simultaneously of n synchronized sampling relay, each battery charged by the maintenance electric capacity of each measurement path protection resistance R to each passage.Reach Tch=5-8 τ ch (τ ch=RC) when the duration of charging, VCi ≈ VBi (i=1,2, ..., n) time, n synchronized sampling relay of synchronized sampling relay group all turn-offed, control the gating of n AD conversion sampling relay then successively, keep voltage VC1, VC2, VC3......VCn on the capacitor C to sample successively to sampling, sampled signal send A/D converter to carry out the AD conversion after the operational amplifier conditioning.

Obviously, to finish the AD conversion be TADi=toff+ton+tAD the required time to each passage.Therefore having finished once sampling keeps the needed time of synchronous acquisition of electric capacity charging and n maintenance capacitance voltage to be

$T=T_{\mathrm{ch}}+\underset{i=1}{\overset{n}{\mathrm{\Σ}}}{T}_{\mathrm{ADi}}$

According to the requirement of data collection cycle T, maintenance capacitor charging time constant τ ch=RC and signal measurement error delta Vbi, can determine that charging rate τ chmax maximum in this circuit and A/D change required maximum time, concrete computing method are as follows:

${\mathrm{\&tau;}}_{\mathrm{ch}\max }<(\frac{1}{5}~\frac{1}{8})T_{\mathrm{ch}}---\left(1\right)$

$\mathrm{\&Delta;}{V}_{\mathrm{Bi}}>e^{-T_{\mathrm{ch}}/{\mathrm{\&tau;}}_{\mathrm{ch}\max }}---\left(2\right)$

After n synchronized sampling relay all disconnects, when successively the voltage on the sampling maintenance capacitor C being sampled, because the leakage current ICL of the shutoff leakage current IjL of PhotoMOS relay, maintenance capacitor C will make VC1, VC2, VC3......VCn descend in time, fall off rate is:

$\frac{d{V}_{\mathrm{Ci}}}{\mathrm{dt}}=\frac{2I_{\mathrm{jL}}+I_{\mathrm{CL}}}{C}---\left(3\right)$

If by 1,2, the order of 3......, n samples to n passage, be TADi the AD switching time of each passage (wherein comprised relay switching time), and then the voltage measurement error that causes owing to leakage current on i passage is:

${\mathrm{\&Delta;V}}_{\mathrm{Ci}}=T_{\mathrm{ADi}}i\frac{{\mathrm{dV}}_{\mathrm{Ci}}}{\mathrm{dt}}---\left(4\right)$

When AD enough fast switching time, promptly at i=1,2,3 ..., during n

Then need not the voltage measurement error that leakage current causes is revised, can satisfy the requirement of measuring accuracy.

If AD TADi switching time is longer, promptly at i=1,2,3 ..., during n

Then can press

$V_{\mathrm{Bi}}=V_{\mathrm{Ci}}+T_{\mathrm{ADi}}i\frac{d{V}_{\mathrm{Ci}}}{\mathrm{dt}}---\left(7\right)$

The voltage measurement error that leakage current causes is revised.

Because the inconsistency that IjL, ICL exist, caused each passage to keep the power on inconsistency of drops speed of capacitor C, if measuring voltage is revised, will produce certain measuring error by (7) formula.Therefore, also can measure passage to each by the following method in actual applications and demarcate, to improve measuring accuracy.

At first, measure input end at all battery voltage signals and insert a standard signal Vbs, provide synchronous sampling method by this paper front then and carry out m measurement, obtain the mean value VCi that each passage is measured for m time, can calculate the virtual voltage fall off rate KVi on each passage maintenance capacitor C thus

$K_{\mathrm{Vi}}=(V_{\mathrm{bs}}-V_{\mathrm{Ci}})/\left(\underset{j=1}{\overset{i}{\mathrm{\&Sigma;}}}{T}_{\mathrm{ADj}}\right)$ (i＝1，2，3，……n)

Deposit KVi in flash RAM or EEROM, when system's actual motion, can revise measuring voltage by following formula:

$V_{\mathrm{Bi}}=V_{\mathrm{Ci}}+K_{\mathrm{Vi}}\underset{j=1}{\overset{i}{\mathrm{\&Sigma;}}}{T}_{\mathrm{ADj}}$ (i＝1，2，3，……n)

Embodiment 1

Measure port number: 15 modular battery voltages; Voltage measurement scope: 0～17V; Measuring period: 50ms; Measuring accuracy: 0.2%; The measurement synchronization time: 1ms; Specific embodiments is as follows:

Measuring principle figure as shown in Figure 1, KS1, KS2, KS3......KS15 and KC1, KC2, KC3 ... KC15 selects for use the AQW614 dpdt double-pole double-throw (DPDT) often to drive the PhotoMOS relay, switch ends is withstand voltage to be 600V, conducting resistance≤120 Ω, turn-off leakage current≤1 μ A, typical case's ON time 0.5ms, typical case turn-off time 0.2ms.

Sampling keeps capacitor C to adopt polystyrene electric capacity, leakage current≤500nA, withstand voltage 60V.

A is the high impedance differential operational amplifier, bias current≤2nA, input impedance 〉=2M Ω.

Rf1 and Rf2 are used for measuring voltage is carried out dividing potential drop, Rf1=1.5M Ω, Rf2=500k Ω.

CS adopts 74LVC15416 to select 1 code translator, and driving circuit adopts 74HC04.

CPU adopts the 80C51F040 that is integrated with 12 bit resolutions, 100ksps switching rate AD converter.

Adopt the 24MHz crystal oscillator, the AD converter among the 80C51F040 can be finished 1 conversion in 10 μ s, by carrying out conversion Calculation continuously 10 times, needs the switching time of 100 μ s.

The ON time representative value of PhotoMOS relay AQW614 is 0.28ms, and the turn-off time representative value is 0.04ms.For guaranteeing AQW614 turn-on and turn-off reliably, get conducting time-delay ton=1ms, turn off delay time toff=0.4ms.

According to (1), (2) formula

${\mathrm{\&tau;}}_{\mathrm{ch}}=\frac{1}{8}{T}_{\mathrm{ch}}=1\mathrm{ms}$

$e^{-T_{\mathrm{ch}}/{\mathrm{\&tau;}}_{\mathrm{ch}}}=e^{-8}<0.012\%$

τ ch=RC, optional R=5k Ω, C=200000pF.Consider that PhotoMOS relay ON time and turn-off time add up to 0.7ms, therefore sampling time of keeping capacitor C to switch to after the charged state should not got Tch=10ms at this less than (Tch+0.7)=8.7ms.

The AD that finishes 15 passages changes the needed time and is

15(ton+toff+tAD)+Tch＝22.5ms+10ms＝32.5ms

Satisfy the requirement of 50ms measuring period.

According to (3) formula, after KS 1, KS2, a KS3......KSn n synchronized sampling relay all disconnected, each voltage fall off rate that keeps on the capacitor C was

$\frac{d{V}_{\mathrm{Ci}}}{\mathrm{dt}}=\frac{2I_{\mathrm{jL}}+I_{\mathrm{CL}}}{C}=\frac{2000\mathrm{nA}+500\mathrm{nA}}{200000\mathrm{pF}}=12.5\mathrm{mV}/\mathrm{ms}$

According to (4) formula, can press

$V_{\mathrm{Bi}}=V_{\mathrm{Ci}}+i(t_{\mathrm{on}}+t_{\mathrm{off}}+t_{\mathrm{AD}})\frac{d{V}_{\mathrm{Ci}}}{\mathrm{dt}}=V_{\mathrm{Ci}}+18.75i$

Measured value to each passage in software is revised.The result shows through actual detected, the measuring error of each passage all in 20mV, the design objective that is better than stipulating.

AQW614 turn-off time representative value is 0.2ms, when synchronized sampling relay group is turn-offed simultaneously, remains on each channel sample and keeps voltage on capacitor C to be the synchro measure voltage in this moment, is better than 1ms lock in time.

Embodiment 2

Monomer battery voltage measures 10 the tunnel, measurement range: 0～2V, measuring accuracy: 0.1%, total voltage measures 1 the tunnel, measurement range: 0～20V, measuring accuracy: 0.2%, charging current measures 1 the tunnel, measurement range: 0～100A, measuring accuracy: 0.2%, discharge current measures 1 the tunnel, measurement range: 0～100A, measuring accuracy: 0.2%, measuring period: 100ms.

Measuring principle figure as shown in Figure 2, total voltage measure to adopt 0～20V input, 0～5V output voltage transmitter.0～100A input, 0～5V output current transmitter are adopted in the charge and discharge current measurement.KS1, KS2, KS3......KS13 and KC1, KC2, KC3......KC13 select for use the AQW210 dpdt double-pole double-throw (DPDT) often to drive the PhotoMOS relay, switch ends is withstand voltage to be 350V, and conducting resistance≤35 Ω is turn-offed leakage current≤1 μ A, typical case's ON time 0.25ms, typical case turn-off time 0.05ms.

Sampling keeps capacitor C to adopt polystyrene electric capacity, leakage current≤500nA, withstand voltage 60V.

A1, A2 are the high impedance differential operational amplifier, bias current≤500nA, input impedance 〉=1M Ω.CS adopts 74LVC15416 to select 1 code translator and 4 74HC04 to constitute.

CPU adopts by what U.S. TURN company produced and is integrated with 16 bit resolutions, 100ksps switching rate AD converter, 24 tunnel universal I interfaces, the R-Engine embedded type CPU module of 1 road RS232 serial line interface.

In actual applications, for guaranteeing AQW210 turn-on and turn-off reliably, get conducting time-delay ton=0.9ms, turn off delay time toff=0.5ms.According to (1), (2) formula

${\mathrm{\&tau;}}_{\mathrm{ch}}=\frac{1}{8}{T}_{\mathrm{ch}}=1\mathrm{ms}$

$e^{-T_{\mathrm{ch}}/{\mathrm{\&tau;}}_{\mathrm{ch}}}=e^{-8}<0.012\%$

According to τ ch=RC, optional R=1k Ω, C=1 μ F.Consider that PhotoMOS relay ON time and turn-off time add up to 0.7ms, therefore sampling time of keeping capacitor C to switch to after the charged state should not got Tch=10ms at this less than (Tch+0.7)=8.7ms.

The AD that finishes 13 passages changes the needed time and is

13(ton+toff+tAD)+Tch＝13(0.9+0.5+0.1)ms+10ms＝29.5ms

Satisfy the requirement of 100ms measuring period.

According to (3) formula, after n synchronized sampling relay all disconnects, keep the voltage fall off rate on the capacitor C to be

$\frac{d{V}_{\mathrm{Ci}}}{\mathrm{dt}}=\frac{2I_{\mathrm{jL}}+I_{\mathrm{CL}}}{C}=\frac{2000\mathrm{nA}+500\mathrm{nA}}{1\mathrm{\&mu;F}}=2.5\mathrm{mV}/\mathrm{ms}$

If carry out the AD conversion by the order of total voltage, charging current, discharge current, monomer battery voltage, according to (4) formula, monomer battery voltage can be pressed

$V_{\mathrm{Bi}}=V_{\mathrm{Ci}}+(3+i)(t_{\mathrm{on}}+t_{\mathrm{off}}+t_{\mathrm{AD}})\frac{d{V}_{\mathrm{Ci}}}{\mathrm{dt}}=V_{\mathrm{Ci}}+3.75(3+i)\mathrm{mV}$

Measured value to each passage in software is revised.

Total voltage, charging current, discharge current are pressed

$V_V=V_{C1}+(t_{\mathrm{on}}+t_{\mathrm{off}}+t_{\mathrm{AD}})\frac{d{V}_{C1}}{\mathrm{dt}}=V_{C1}+3.75\mathrm{mV}$

$V_{C1}=V_{C2}+2(t_{\mathrm{on}}+t_{\mathrm{off}}+t_{\mathrm{AD}})\frac{d{V}_{C2}}{\mathrm{dt}}=V_{C2}+7.5\mathrm{mV}$

$V_{D1}=V_{C3}+3(t_{\mathrm{on}}+t_{\mathrm{off}}+t_{\mathrm{AD}})\frac{d{V}_{C3}}{\mathrm{dt}}=V_{C3}+11.25\mathrm{mV}$

Revise

The result shows through actual detected, the design objective that the measuring error of each passage all reaches or is better than stipulating.

AQW210 reliable turn-off time≤0.2ms as synchronized sampling relay group KS1, when KS2, KS3......KS15 turn-off simultaneously, remains on each channel sample and keeps voltage on capacitor C to be the synchro measure voltage signal in this moment, is better than 1ms lock in time.

Claims (8)

1, a kind of circuit for measuring synchronized sampler of flying capacitance reaches, comprise synchronized sampling relay group (Ks), two input ends of each synchronized sampling relay (Ks) are connected with the both positive and negative polarity of a battery module respectively, it is characterized in that, also be provided with AD switching relay (Kc) with the same relay quantity of synchronized sampling relay group (Ks), two output terminals of the synchronized sampling relay (Ksi) that two input ends of each AD switching relay (Kc) are corresponding with connect respectively, and a sampling in parallel keeps electric capacity (C) between these two input ends; Two output terminals of each AD switching relay (Kc) are connected to the input end of a high input impedance differential operational amplifier (A), and the operational amplifier output signal is sent AD converter after suitable conditioning; Synchronized sampling relay group (Ks) and each AD switching relay (Kc) are controlled by decoder driver circuit by CPU, realize that the synchronized sampling of multichannel measurement signal is measured.

2, circuit for measuring synchronized sampler of flying capacitance as claimed in claim 1 is characterized in that, also is in series with one and imports current-limiting resistance (R) between input end of described each sampling relay (Ks) and the corresponding battery that is connected.

3, circuit for measuring synchronized sampler of flying capacitance as claimed in claim 1 is characterized in that, described sampling relay (Ks) and/or AD switching relay (Kc) adopt double-pole single-throw (D.P.S.T.) or double-throw normally opened relay.

4, circuit for measuring synchronized sampler of flying capacitance as claimed in claim 3 is characterized in that, described sampling relay group (Ks) or AD switching relay (Kc) adopt the PhotoMOS relay.

5, circuit for measuring synchronized sampler of flying capacitance as claimed in claim 1 is characterized in that, described decoder driver circuit is that n+1 selects 1 decoder driver circuit, and wherein n is the quantity of described AD switching relay (Kc) or sampling relay group (Ks).

6, a kind of synchronized sampler of flying capacitance measuring method is characterized in that, may further comprise the steps:

(1) all synchronized sampling relays of gating synchronized sampling relay group allow each battery module keep electric capacity to charge to each self-corresponding sampling;

(2) after charging process enters stable state, turn-off all synchronized sampling relays;

(3) CPU controls each AD conversion sampling relay of gating successively, keep the voltage on the capacitor C to carry out taking turn sampling to all samplings, to sample by the AD of gating conversion sampling relay and to keep the voltage on the electric capacity to send into high input impedance differential operational amplifier A after amplification and dividing potential drop, carry out the AD conversion by AD converter, acquired signal is given CPU;

(4) CPU deal with data and export measurement data.

7, method as claimed in claim 6 is characterized in that,

Calculate earlier before or setting measurement drift correction parameter in step (1): finish once all sampling period T of channel measurement, sampling keeps capacitor charging time Tch, relay turn on delay time ton, relay turn-off delay time toff, the shutoff leakage current IJL of relay, AD converter is finished 1 required time tAD of passage AD conversion;

The CPU deal with data is by formula to calculate on each passage because the voltage measurement deviation that relay and sampling keep capacitor leakage current to cause is adjusted measurement result then in step (4), and described formula is:

$V_{\mathrm{bi}}-V_{\mathrm{Cbi}}=i(t_{\mathrm{on}}+t_{\mathrm{off}}+t_{\mathrm{AD}})\frac{{\mathrm{dV}}_{\mathrm{Cbi}}}{\mathrm{dt}}$

Vbi is a cell voltage in the formula, and VCbi keeps capacitance voltage for sampling, and i is for measuring the passage Ser.No..

8, method as claimed in claim 6 is characterized in that,

Earlier carry out repeated detection at each passage before in step (1), obtain the mean value VCbi that each passage is repeatedly measured with standard signal Vbs., calculate the virtual voltage fall off rate KVi on each channel sample maintenance electric capacity;

The CPU deal with data is by formula to calculate on each passage because the voltage measurement deviation that relay and sampling keep capacitor leakage current to cause is adjusted measurement result then in step (4), and described formula is:

$V_{\mathrm{bi}}=V_{\mathrm{Cbi}}+K_{\mathrm{Vi}}\underset{j=1}{\overset{i}{\mathrm{\&Sigma;}}}{T}_{\mathrm{ADj}}$

Vbi is a cell voltage in the formula, and VCbi keeps capacitance voltage for sampling, and i is for measuring the passage Ser.No..