CN103760392A - Adjustment amendment signal generating circuit used for DC-DC converter - Google Patents
Adjustment amendment signal generating circuit used for DC-DC converter Download PDFInfo
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- CN103760392A CN103760392A CN201410029320.XA CN201410029320A CN103760392A CN 103760392 A CN103760392 A CN 103760392A CN 201410029320 A CN201410029320 A CN 201410029320A CN 103760392 A CN103760392 A CN 103760392A
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Abstract
The invention discloses an adjustment amendment signal generating circuit used for a DC-DC converter. The adjustment amendment signal generating circuit mainly solves the problem of secondary deviation caused by index adjustment amendment of an existing converter before chip placing and packaging. The adjustment amendment signal generating circuit comprises a sequence generating unit (1), a counter (2), four to sixteen decoders (3), an adjustment amendment unit (4) and a current bias unit (5). The sequence generating unit generates clock signals, wherein the number of the clock signals is equal to the number of signal pulses exerted outside a chip; the counter is used for counting the clock signals to obtain four-bit binary codes, outputting the four-bit binary codes to the decoder to be decoded and providing enable signals for the adjustment amendment unit, meanwhile the current bias unit supplies bias currents to the adjustment amendment unit, so that a fuse is burnt out and adjustment amendment singles are obtained, and the adjustment amendment signals are output to external circuits for index amendment. The adjustment function of the adjustment amendment signal generating circuit can be completed after the chip is packaged, secondary index deviation caused by the packaging process can be avoided, and the adjustment amendment signal generating circuit can be used for simulating an integrated circuit.
Description
Technical field
The invention belongs to electronic circuit technology field, relate to Analogous Integrated Electronic Circuits, especially for the adjusting corrected signal generation circuit of DC-DC converter.
Background technology
Along with popularizing of the digital products such as portable media player, navigator, panel computer, power management chip has obtained swift and violent development.DC-DC is widely used in the battery-powered occasion of employing lithium-ion electric because it has the advantage that load capacity is strong, efficiency is high.Along with the complexity of DC-DC design is more and more higher, be also subject to the impact of technological level simultaneously, once throw the successful possibility of sheet also more and more less.For farthest cost-saving, people wish after throwing sheet, to measure easily relevant important technology index, and can regulate correction.
Fig. 1 has shown the system chart of existing DC-DC converter, this DC-DC converter is comprised of bandgap reference voltage VREF, bias current sources IBIAS, error amplifier, PWM comparer, logical drive, oscillator, slope compensation, main switch, synchronous freewheeling pipe, feedback resistance RA, feedback resistance RB and pin FB, EN, VIN, LX, GND, wherein the mimic channel such as bandgap reference voltage VREF, bias current sources IBIAS is due to the deviation of manufacturing process, after throwing sheet, need to finely tune, to meet index request.
In integrated circuit, the normal mode of blow current fuse that adopts is carried out index fine setting.Fig. 2 has provided the circuit theory diagrams of the electric current fuse regulon of classic method employing.By fuse FUSE is passed into large electric current, blow, change the resistance size of access K, L point-to-point transmission resistance, thereby circuit index is regulated.
Traditional electric current fuse method for trimming is due to need be at fuse two ends access probe, thereby when the large electric current of introducing blows processing, the performance of recording device will be limited to, simultaneously higher electric current also likely produces accidental damage to recording device, cause unnecessary loss, and maintenance cost is higher; Due in carrying out trim process, probe contact spacing is less simultaneously, and probe is easy to encounter and causes together short circuit.In addition because tradition regulates modification method, be generally to complete before chip package, after encapsulation, due to the impact of encapsulating material, packaging technology etc., can cause the secondary deviation of the indexs such as bandgap voltage reference, reference current.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned prior art, propose a kind of adjusting corrected signal for DC-DC converter and produce circuit, cause the secondary deviation of bandgap voltage reference and reference current index when avoiding chip package, improve yield rate.
The technical thought that realizes the object of the invention is, in bandgap voltage reference and reference current module, a switching tube is carried out in parallel with regulating resistance, adopt the adjusting corrected signal producing to control opening or turn-offing of this switching tube, thereby the resistance value size that changes place in circuit, reaches the object regulating at the laggard row index of chip package.
Whole circuit of the present invention comprises: counter 2, and 4-16 code translator 3, current offset unit 5, is characterized in that: also comprise sequence generation unit 1 and regulate amending unit 4;
Described sequence generation unit 1, for generation of the clock sequence PULSE and the enable signal EN1 that have with the additional square wave excitation same period of chip, this clock sequence PULSE is connected to counter 2, and this enable signal EN1 is connected to current offset unit 5;
Described counter 2, carries out step-by-step counting for the square-wave signal that sequence generation unit 1 is produced, and exports tetrad coded signal to 4-16 code translator 3;
Described 4-16 code translator 3, for the tetrad coded signal of counter 2 outputs is carried out to decoding, and exports the decoded signal TM0～TM15 of generation to regulate amending unit 4 to, and it is enabled;
Described adjusting amending unit 4, for generation of regulating corrected signal TRIM, exports to bandgap reference voltage and the current reference that will revise outside;
Described current offset unit 5, is used to and regulates amending unit 4 that current offset signal IBIAS2 is provided.
Above-mentioned adjusting corrected signal produces circuit, wherein sequence generation unit 1, comprise 6 PMOS pipes M1, M2, M3, M4, M5, M6,7 NMOS manage M7, M8, M9, M10, M11, M12, M13,6 phase inverter X1, X2, X3, X4, X5, X6,1 rising edge testing circuit X7,1 rest-set flip-flop X8,1 d type flip flop X9;
The one NMOS pipe M7, the 2nd NMOS pipe M8, the 3rd NMOS pipe M9, the 4th NMOS pipe M10, the 5th NMOS pipe M11 connect successively, form the first current mirror;
The 2nd PMOS pipe M2 is connected with the 3rd PMOS pipe M3, forms the second current mirror;
The one NMOS pipe M7, as the input end of the first current mirror, the outside bias current sources IBIAS1 providing is provided in its drain electrode; Its source electrode is connected to ground; Its grid drains and is connected with self, and is connected with the grid of the 2nd NMOS pipe M8 simultaneously;
The 2nd NMOS pipe M8, as the first output terminal of the first current mirror, its drain electrode is connected with the drain electrode of a PMOS pipe M1, and as the input end of the first phase inverter X1; Its source electrode is connected to ground; Its grid is connected with the grid of the 3rd NMOS pipe M9;
The 3rd NMOS pipe M9, as the second output terminal of the first current mirror, its drain electrode is connected with the drain electrode of the 2nd PMOS pipe M2; Its source electrode is connected to ground; Its grid is connected with the grid of the 4th NMOS pipe M10;
The 4th NMOS pipe M10, as the 3rd output terminal of the first current mirror, its drain electrode is connected with the drain electrode of the 3rd PMOS pipe M3, and as the input end of the 3rd phase inverter X3; Its source electrode is connected to ground; Its grid is connected with the grid of the 5th NMOS pipe M11;
The 5th NMOS pipe M11, as the 4th output terminal of the first current mirror, its drain electrode is connected with the source electrode of the 6th NMOS pipe M12; Its source electrode is connected to ground;
The 6th NMOS pipe M12, its drain electrode is connected with the drain electrode of the 4th PMOS pipe, and as the input end of rising edge testing circuit X7; Its grid is connected with the grid of the 5th PMOS pipe;
The 7th NMOS pipe M13, its drain electrode is connected with the drain electrode of the 6th PMOS pipe M6, and as the input end of the 5th phase inverter X5; Its source electrode is connected to ground; The outside voltage bias signal VBIAS1 providing is provided its grid;
The one PMOS pipe M1, its source electrode connects the enable signal EN of place chip; Grid connects the supply voltage VIN of place chip;
The 2nd PMOS pipe M2, as the input end of the second current mirror, its source electrode connects the supply voltage VIN of place chip; Its grid drains and is connected with self, and is connected with the grid of the 3rd PMOS pipe M3 simultaneously;
The 3rd PMOS pipe M3, as the output terminal of the second current mirror, its source electrode is connected with the grid of the 4th PMOS pipe M4 with the enable signal EN of place chip respectively;
The 4th PMOS pipe M4, its source electrode is connected with the supply voltage VIN of place chip, and its drain electrode is connected with the input end of rising edge testing circuit X7 with the drain electrode of the 5th PMOS pipe M5 respectively; The output terminal of rising edge testing circuit X7 is connected with the input end of the 4th phase inverter X4; The output terminal of the 4th phase inverter X4 is connected with the first input end R of rest-set flip-flop X8; The second input end S of rest-set flip-flop X8 is connected with the output terminal of the 3rd phase inverter X3; The first output terminal Q of rest-set flip-flop X8 is connected with the grid of the 5th PMOS pipe M5, and output clock sequence signal PULSE, and the second output terminal QB of rest-set flip-flop X8 is unsettled;
The source electrode of the 5th PMOS pipe M5 connects the supply voltage VIN of place chip;
The 6th PMOS pipe M6, its source electrode connects the feedback signal FB of place chip, and its grid connects the supply voltage VIN of place chip;
The first phase inverter X1, its output terminal is connected with the input end of the second phase inverter X2; The output terminal of the second phase inverter X2 is connected with the first input end D of d type flip flop X9;
D type flip flop X9, its second input end CLK is connected with the output of hex inverter X6, its first output terminal Q output enable control signal EN1, the second output terminal QB is unsettled;
The input of hex inverter X6 is connected with the output terminal of the 5th phase inverter X5.
Above-mentioned adjusting corrected signal produces circuit, wherein regulates amending unit 4,16 identical module U0～U15 of structure, consists of, and the input end of these modules U0～U15 is corresponding connected with 16 signal TM0～TM15 of 4-16 code translator 3 outputs respectively; A binary coded signal of each module output, the output of these 16 modules forms sixteen bit binary coded signal TRIM jointly.
Above-mentioned adjusting corrected signal produces circuit, wherein each module in module U0～U15 includes two input nand gate X10, a FUSE fuse X13, a resistance R 2, with a PMOS pipe, three NMOS pipes, two phase inverters, the 7th PMOS manages M14, the 8th NMOS pipe M15, the 9th NMOS pipe M16, the tenth NMOS pipe M17, the 7th phase inverter X11, the 8th phase inverter X12;
The 7th PMOS pipe M14, its drain electrode is connected with the drain electrode of the 9th NMOS pipe M16, and as the input of the 8th phase inverter X12, its source electrode is connected with the first end of fuse X13 with the drain electrode of the 8th NMOS pipe M15 respectively, the voltage bias signal VBIAS2 that its grid provides with outside is connected; A binary coded signal of output terminal output of the 8th phase inverter X12; The second end of fuse X13 is connected with the supply voltage VIN of place chip;
The 8th NMOS pipe M15, the current offset signal IBIAS2 that its source electrode provides with outside is connected; Grid is connected with one end of the first resistance R 2 with the output of the 7th phase inverter X11 respectively; The other end of the first resistance R 2 is connected to ground; The input end of the 7th phase inverter X11 is connected with the output terminal of two input nand gate X10; The first input end of two input nand gate X10 is connected with signal TM0～TM15; The second input end of two input nand gate X10 is connected with enable signal EN2;
The 9th NMOS pipe M16, its source electrode is connected with the drain electrode of the tenth NMOS pipe M17, and the voltage bias signal VBIAS3 that its grid provides with outside is connected;
The tenth NMOS pipe M17, its source electrode is connected to ground, and the voltage bias signal VBIAS4 that its grid provides with outside is connected;
The 9th NMOS pipe M16 is connected with the tenth NMOS pipe M17, and the input end for the 8th phase inverter X12 provides suitable operating voltage jointly.
Above-mentioned adjusting corrected signal produces circuit, wherein current offset unit 5, comprise three NMOS pipes, three resistance and two phase inverters, the 11 NMOS pipe M18, the 12 NMOS pipe M19, the 13 NMOS manage M20, the second resistance R 3, the 3rd resistance R 4, the 4th resistance R 5, the nine phase inverter X14, the tenth phase inverter X15;
The 11 NMOS pipe M18 is connected with the 12 NMOS pipe M19, forms the 3rd current mirror, the 11 NMOS pipe M18, and as the input end of the 3rd current mirror, its source electrode connects one end of the 3rd resistance R 4; The other end of the 3rd resistance R 4 is connected to ground; The grid of the 11 NMOS pipe M18 drains and is connected with self, and is connected with the source electrode of the 13 NMOS pipe M20 with the grid of the 12 NMOS pipe M19 respectively;
The 12 NMOS pipe M19, as the output terminal of the 3rd current mirror, its source electrode is connected with the 4th resistance R 5, its drain electrode output current offset signal IBIAS2;
The 13 NMOS pipe M20, its drain electrode connects one end of the second resistance R 3, and its grid is connected with the output of the tenth phase inverter X15; The input of the tenth phase inverter X15 is connected with the output of the 9th phase inverter X14; The input end of the 9th phase inverter X14 connects signal EN1, and the other end of the second resistance R 3 is connected with the supply voltage VIN of place chip.
The present invention due to the indoor design at DC-DC chip clock sequence generation unit and fuse regulate amending unit, compare with the method for the additional probe blown fuse of employing, can directly in the inside of DC-DC chip, produce and regulate corrected signal, and completing technology index adjustment process, avoided the impact that recording device is produced, reduced cost, and fusing process is safer to chip, can improves yield rate; Because this adjusting corrected signal is to produce at DC-DC chip internal, therefore can adjust its technical indicator, compare the Quadratic deviation that can avoid encapsulation process to bring with regulate correction before chip package after chip package completes simultaneously.
Accompanying drawing explanation
Fig. 1 is the system chart of existing DC-DC converter;
Fig. 2 is the circuit theory diagrams of the electric current fuse regulon of classic method employing;
Fig. 3 is that adjusting corrected signal of the present invention produces circuit block diagram;
Fig. 4 is the sequence generation element circuit schematic diagram in the present invention;
Fig. 5 is the adjusting amending unit structured flowchart in the present invention;
Fig. 6 is the adjusting amending unit circuit theory diagrams in the present invention;
Fig. 7 is the current offset element circuit schematic diagram in the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the invention will be further described.
With reference to Fig. 3, adjusting corrected signal of the present invention produces circuit and comprises: sequence generation unit 1, and counter 2,4-16 code translator 3, regulates amending unit 4 and current offset unit 5, wherein:
Described sequence generation unit 1, for generation of the clock sequence PULSE and the enable signal EN1 that have with the additional square wave excitation same period of chip, this clock sequence PULSE is connected to counter 2, and this enable signal EN1 is connected to current offset unit 5;
Described counter 2, carries out step-by-step counting for the square-wave signal that sequence generation unit 1 is produced, and exports tetrad coded signal to 4-16 code translator 3;
Described 4-16 code translator 3, for the tetrad coded signal of counter 2 outputs is carried out to decoding, and exports the decoded signal TM0～TM15 of generation to regulate amending unit 4 to, and it is enabled;
Described adjusting amending unit 4, for generation of regulating corrected signal TRIM, exports to bandgap reference voltage and the current reference that will revise outside;
Described current offset unit 5, is used to and regulates amending unit 4 that current offset signal IBIAS2 is provided.
With reference to Fig. 4, sequence generation of the present invention unit 1, comprise six PMOS pipes M1, M2, M3, M4, M5, M6, seven NMOS manage M7, M8, M9, M10, M11, M12, M13, six phase inverter X1, X2, X3, X4, X5, X6, a rising edge testing circuit X7, a rest-set flip-flop X8, a d type flip flop X9;
The one NMOS pipe M7, the 2nd NMOS pipe M8, the 3rd NMOS pipe M9, the 4th NMOS pipe M10, the 5th NMOS pipe M11 connect successively, form the first current mirror;
The 2nd PMOS pipe M2 is connected with the 3rd PMOS pipe M3, forms the second current mirror;
The one NMOS pipe M7, as the input end of the first current mirror, the outside bias current sources IBIAS1 providing is provided in its drain electrode; Its source electrode is connected to ground; Its grid drains and is connected with self, and is connected with the grid of the 2nd NMOS pipe M8 simultaneously;
The 2nd NMOS pipe M8, as the first output terminal of the first current mirror, its drain electrode is connected with the drain electrode of a PMOS pipe M1, and as the input end of the first phase inverter X1; Its source electrode is connected to ground; Its grid is connected with the grid of the 3rd NMOS pipe M9;
The 3rd NMOS pipe M9, as the second output terminal of the first current mirror, its drain electrode is connected with the drain electrode of the 2nd PMOS pipe M2; Its source electrode is connected to ground; Its grid is connected with the grid of the 4th NMOS pipe M10;
The 4th NMOS pipe M10, as the 3rd output terminal of the first current mirror, its drain electrode is connected with the drain electrode of the 3rd PMOS pipe M3, and as the input end of the 3rd phase inverter X3; Its source electrode is connected to ground; Its grid is connected with the grid of the 5th NMOS pipe M11;
The 5th NMOS pipe M11, as the 4th output terminal of the first current mirror, its drain electrode is connected with the source electrode of the 6th NMOS pipe M12; Its source electrode is connected to ground;
The 6th NMOS pipe M12, its drain electrode is connected with the drain electrode of the 4th PMOS pipe, and as the input end of rising edge testing circuit X7; Its grid is connected with the grid of the 5th PMOS pipe;
The 7th NMOS pipe M13, its drain electrode is connected with the drain electrode of the 6th PMOS pipe M6, and as the input end of the 5th phase inverter X5; Its source electrode is connected to ground; The outside voltage bias signal VBIAS1 providing is provided its grid;
The one PMOS pipe M1, its source electrode connects the enable signal EN of place chip; Its grid connects the supply voltage VIN of place chip;
The 2nd PMOS pipe M2, as the input end of the second current mirror, its source electrode connects the supply voltage VIN of place chip; Its grid drains and is connected with self, and is connected with the grid of the 3rd PMOS pipe M3 simultaneously;
The 3rd PMOS pipe M3, as the output terminal of the second current mirror, its source electrode is connected with the grid of the 4th PMOS pipe M4 with the enable signal EN of place chip respectively;
The 4th PMOS pipe M4, its source electrode is connected with the supply voltage VIN of place chip;
The 5th PMOS pipe M5, its drain electrode is connected with the drain electrode of the 4th PMOS pipe; Its source electrode connects the supply voltage VIN of place chip;
The 6th PMOS pipe M6, its source electrode connects the feedback signal FB of place chip; Its grid connects the supply voltage VIN of place chip;
The first phase inverter X1, its output terminal is connected with the input end of the second phase inverter X2;
The second phase inverter X2, its output terminal is connected with the first input end D of d type flip flop X9;
The 3rd phase inverter X3, its output terminal is connected with the second input end S of rest-set flip-flop X8;
The 4th phase inverter X4, its input end is connected with the output of rising edge testing circuit X7; Its output terminal is connected with the first input end R of rest-set flip-flop X8;
The 5th phase inverter X5, its output terminal is connected with the input end of hex inverter X6;
Hex inverter X6, its output terminal is connected with the second input end CLK of d type flip flop X9;
Rest-set flip-flop X8, its first output terminal Q is connected with the grid of the 5th PMOS pipe M5, and output clock sequence signal PULSE; QB is unsettled for its second output terminal;
D type flip flop X9, its first output terminal Q output enable control signal EN1; QB is unsettled for its second output terminal.
Above-mentioned sequence generation unit 1 mainly contains two functions: the one, and make DC-DC chip enter adjusting modification model by normal mode of operation; The 2nd, after entering adjusting modification model, produce and regulate clock sequence PULSE.
The principle that realizes above-mentioned two functions is as follows:
When the EN leads ends at DC-DC chip applies high voltage, make it meet V
eN>V
vIN, V wherein
eNfor the magnitude of voltage of EN leads ends, V
vINfor the magnitude of voltage of input power, now the first input end D of d type flip flop X9 is connected to high level; Then, in feedback voltage FB leads ends, apply high voltage, make it meet V
fB>V
vIN+ | V
tHP (M6)|, V wherein
fBfor the magnitude of voltage of FB leads ends, V
tHP (M6)it is the threshold voltage of the 6th PMOS pipe M6.Now at the second input end CLK place of d type flip flop X9, will produce a rising edge clock signal, make the signal EN1 that the first output terminal Q of d type flip flop X9 exports become high level from low level, thereby make chip enter adjusting modification model, realize first function of this sequence generation unit 1.
When the EN leads ends at DC-DC chip applies high voltage, make a point be pulled to high level, the second input end S of rest-set flip-flop X8 will become low level, thereby make signal PULSE output high level.
When the EN leads ends at DC-DC chip applies low-voltage, make the 3rd PMOS pipe M3 cut-off, a point voltage is pulled down to low level, so the second input end S of rest-set flip-flop X8 becomes high level.Now, the 4th PMOS pipe M4 conducting, b point is pulled to high level, by rising edge testing circuit X7 and the 4th phase inverter X4, makes the first input end R of rest-set flip-flop X8 become low level, thus signal PULSE output low level.
By the EN leads ends at DC-DC chip, apply the square wave clock signal that height changes, can obtain the adjusting clock sequence PULSE identical with inputting square wave clock signal pulse number, to realize second function of this sequence generation unit 1.
With reference to Fig. 5, adjusting amending unit 4 of the present invention, by 16 identical module U0～U15 of structure, formed, the input end of these modules U0～U15 is corresponding connected with 16 signal TM0～TM15 of 4-16 code translator 3 outputs respectively, the input end that is first module U0 is connected with first signal TM0 of 4-16 code translator output, the input end of second module U1 is connected with second signal TM1 of 4-16 code translator output, the input end of the 3rd module U2 is connected with the 3rd signal TM2 of 4-16 code translator output, the input end of the 4th module U3 is connected with the 4th signal TM3 of 4-16 code translator output, the input end of the 5th module U4 is connected with the 5th signal TM4 of 4-16 code translator output, the input end of the 6th module U5 is connected with the 6th signal TM5 of 4-16 code translator output, the input end of the 7th module U6 is connected with the 7th signal TM6 of 4-16 code translator output, the input end of the 8th module U7 is connected with the 8th signal TM7 of 4-16 code translator output, the input end of the 9th module U8 is connected with the 9th signal TM8 of 4-16 code translator output, the input end of the tenth module U9 is connected with the tenth signal TM9 of 4-16 code translator output, the input end of the 11 module U10 is connected with the 11 signal TM10 of 4-16 code translator output, the input end of the 12 module U11 is connected with the 12 signal TM11 of 4-16 code translator 3 outputs, the input end of the 13 module U12 is connected with the 13 signal TM12 of 4-16 code translator output, the input end of the 14 module U13 is connected with the 14 signal TM13 of 4-16 code translator output, the input end of the 15 module U14 is connected with the 15 signal TM14 of 4-16 code translator output, the input end of the 16 module U15 is connected with the 16 signal TM15 of 4-16 code translator output.A binary coded signal of each module output, the output of these 16 modules forms sixteen bit binary coded signal TRIM jointly.
With reference to Fig. 6, the present invention regulates in 16 module U0～U15 of amending unit, its each module includes two input nand gate X10, a FUSE fuse X13, a resistance R 2, with a PMOS pipe, three NMOS pipes, two phase inverters, the 7th PMOS manages M14, the 8th NMOS pipe M15, the 9th NMOS pipe M16, the tenth NMOS pipe M17, the 7th phase inverter X11, the 8th phase inverter X12;
The 7th PMOS pipe M14, its drain electrode is connected with the drain electrode of the 9th NMOS pipe M16, and as the input of the 8th phase inverter X12; Its source electrode is connected with one end of fuse X13 with the drain electrode of the 8th NMOS pipe M15 respectively; The voltage bias signal VBIAS2 that its grid provides with outside is connected;
The 8th NMOS pipe M15, the current offset signal IBIAS2 that its source electrode provides with outside is connected; Its grid is connected with the output of the 7th phase inverter X11, and is connected to one end of the first resistance R 2;
The 9th NMOS pipe M16, its source electrode is connected with the drain electrode of the tenth NMOS pipe M17; The voltage bias signal VBIAS3 that its grid provides with outside is connected;
The tenth NMOS pipe M17, its source electrode is connected to ground; The voltage bias signal VBIAS4 that its grid provides with outside is connected;
The 9th NMOS pipe M16 is connected with the tenth NMOS pipe M17, and the input end for the 8th phase inverter X12 provides suitable operating voltage jointly.
Two input nand gate X10, its first input end is connected with signal TM0～TM15; Its second input end is connected with enable signal EN2; Its output terminal is connected with the input end of the 7th phase inverter X11;
Fuse X13, its other end is connected with the supply voltage VIN of place chip;
Resistance R 2, its other end is connected to ground;
The 8th phase inverter X12, a binary coded signal of its output terminal output.
With reference to Fig. 6, when chip enters adjusting modification model, the second input end signal EN2 of two input nand gate X10 becomes high level, when any one in signal TM0～TM15 becomes high level, the first input end of two input nand gate X10 will become high level, thereby make the 8th NMOS pipe M15 conducting.The bias current IBIAS2 now being exported by the current offset unit fuse X13 that flows through, this fuse is fused, thereby c point voltage is become to low level, make the output signal of the 8th phase inverter X12 become high level, this high level signal is connected to outside bandgap reference voltage and current reference regulates correction.
With reference to Fig. 7, current offset of the present invention unit 5, comprise three NMOS pipes, three resistance and two phase inverters, the 11 NMOS pipe M18, the 12 NMOS pipe M19, the 13 NMOS manage M20, the second resistance R 3, the 3rd resistance R 4, the 4th resistance R 5, the 9th phase inverter X14, the tenth phase inverter X15, wherein:
The 11 NMOS pipe M18 is connected with the 12 NMOS pipe M19, forms the 3rd current mirror;
The 11 NMOS pipe M18, as the input end of the 3rd current mirror, its source class connects one end of the 3rd resistance R 4; Its grid drains and is connected with self, and is connected with the source electrode of the 13 NMOS pipe M20 with the grid of the 12 NMOS pipe M19 respectively;
The 12 NMOS pipe M19, as the output terminal of the 3rd current mirror, its source electrode connects one end of the 4th resistance R 5; Its drain electrode output current offset signal IBIAS2;
The 13 NMOS pipe M20, its drain electrode connects one end of the second resistance R 3; Its grid is connected with the output of the tenth phase inverter X15;
The second resistance R 3, its other end is connected with the supply voltage VIN of place chip;
The 3rd resistance R 4, its other end is connected to ground;
The 4th resistance R 5, its other end is connected to ground;
The 9th phase inverter X14, its input end is connected with signal EN1; Its output terminal is connected with the input of the tenth phase inverter X15.
With reference to Fig. 7, when the input end signal EN1 of the 9th phase inverter X14 becomes high level, chip enters adjusting modification model, make the 13 NMOS pipe M20 conducting, therefore have electric current to pass through in the 11 NMOS pipe M18, through the mirror image effect of the 3rd current mirror, by the 12 NMOS pipe M19 output current offset signal IBIAS2, be connected to and regulate in amending unit 4.
Principle of work of the present invention is as follows:
When the EN leads ends at DC-DC applies pulse number and is the square wave clock signal CLK of n, 1≤n≤16, sequence generation unit 1 can be converted into signal CLK the signal PULSE that pulse number is similarly n, then the pulse number of 2 couples of signal PULSE of counter is counted, obtain tetrad coding, and export in 4-16 code translator 3.4-16 code translator 3 carries out decoded operation, and export high level enable signal, this high level enable signal can make to regulate the fuse module U0～U15 in amending unit 4 to start working, the fuse that the bias current IBIAS2 of now current offset unit 5 outputs flows through in module U0～U15, this fuse is fused, then can be at the adjusted corrected signal TRIM of output terminal that regulates amending unit 4, this signal TRIM exports outside bandgap reference voltage to and current reference carries out index correction.
Below be only a preferred example of the present invention, do not form any limitation of the invention, obviously, under design of the present invention, can carry out different changes and improvement to its circuit, but these are all at the row of protection of the present invention.
Claims (5)
1. the adjusting corrected signal for DC-DC converter produces circuit, comprise counter (2), 4-16 code translator (3), current offset unit (5), is characterized in that: also comprise sequence generation unit (1) and regulate amending unit (4);
Described sequence generation unit (1), for generation of the clock sequence PULSE and the enable signal EN1 that have with the additional square wave excitation same period of chip, this clock sequence PULSE is connected to counter (2), and this enable signal EN1 is connected to current offset unit (5);
Described counter (2), carries out step-by-step counting for the square-wave signal that sequence generation unit (1) is produced, and exports tetrad coded signal to 4-16 code translator (3);
Described 4-16 code translator (3), for the tetrad coded signal of counter (2) output is carried out to decoding, and exports the decoded signal TM0～TM15 of generation to regulate amending unit (4) to, and it is enabled;
Described adjusting amending unit (4), for generation of regulating corrected signal TRIM, exports to bandgap reference voltage and the current reference that will revise outside;
Described current offset unit (5), is used to and regulates amending unit (4) that current offset signal IBIAS2 is provided.
2. adjusting corrected signal according to claim 1 produces circuit, it is characterized in that sequence generation unit (1), comprise 6 PMOS pipes M1, M2, M3, M4, M5, M6,7 NMOS manage M7, M8, M9, M10, M11, M12, M13,6 phase inverter X1, X2, X3, X4, X5, X6,1 rising edge testing circuit (X7), 1 rest-set flip-flop (X8), 1 d type flip flop (X9);
The one NMOS pipe M7, the 2nd NMOS pipe M8, the 3rd NMOS pipe M9, the 4th NMOS pipe M10, the 5th NMOS pipe M11 connect successively, form the first current mirror;
The 2nd PMOS pipe M2 is connected with the 3rd PMOS pipe M3, forms the second current mirror;
The one NMOS pipe M7, as the input end of the first current mirror, the outside bias current sources IBIAS1 providing is provided in its drain electrode; Its source electrode is connected to ground; Its grid drains and is connected with self, and is connected with the grid of the 2nd NMOS pipe M8 simultaneously;
The 2nd NMOS pipe M8, as the first output terminal of the first current mirror, its drain electrode is connected with the drain electrode of a PMOS pipe M1, and as the input end of the first phase inverter X1; Its source electrode is connected to ground; Its grid is connected with the grid of the 3rd NMOS pipe M9;
The 3rd NMOS pipe M9, as the second output terminal of the first current mirror, its drain electrode is connected with the drain electrode of the 2nd PMOS pipe M2; Its source electrode is connected to ground; Its grid is connected with the grid of the 4th NMOS pipe M10;
The 4th NMOS pipe M10, as the 3rd output terminal of the first current mirror, its drain electrode is connected with the drain electrode of the 3rd PMOS pipe M3, and as the input end of the 3rd phase inverter X3; Its source electrode is connected to ground; Its grid is connected with the grid of the 5th NMOS pipe M11;
The 5th NMOS pipe M11, as the 4th output terminal of the first current mirror, its drain electrode is connected with the source electrode of the 6th NMOS pipe M12; Its source electrode is connected to ground;
The 6th NMOS pipe M12, its drain electrode is connected with the drain electrode of the 4th PMOS pipe, and as the input end of rising edge testing circuit (X7); Its grid is connected with the grid of the 5th PMOS pipe;
The 7th NMOS pipe M13, its drain electrode is connected with the drain electrode of the 6th PMOS pipe M6, and as the input end of the 5th phase inverter X5; Its source electrode is connected to ground; The outside voltage bias signal VBIAS1 providing is provided its grid;
The one PMOS pipe M1, its source electrode connects the enable signal EN of place chip; Grid connects the supply voltage VIN of place chip;
The 2nd PMOS pipe M2, as the input end of the second current mirror, its source electrode connects the supply voltage VIN of place chip; Its grid drains and is connected with self, and is connected with the grid of the 3rd PMOS pipe M3 simultaneously;
The 3rd PMOS pipe M3, as the output terminal of the second current mirror, its source electrode is connected with the grid of the 4th PMOS pipe M4 with the enable signal EN of place chip respectively;
The 4th PMOS pipe M4, its source electrode is connected with the supply voltage VIN of place chip, and its drain electrode is connected with the input end of rising edge testing circuit X7 with the drain electrode of the 5th PMOS pipe M5 respectively; The output terminal of rising edge testing circuit X7 is connected with the input end of the 4th phase inverter X4; The output terminal of the 4th phase inverter X4 is connected with the first input end R of rest-set flip-flop X8; The second input end S of rest-set flip-flop X8 is connected with the output terminal of the 3rd phase inverter X3; The first output terminal Q of rest-set flip-flop X8 is connected with the grid of the 5th PMOS pipe M5, and output clock sequence signal PULSE, and the second output terminal QB of rest-set flip-flop X8 is unsettled;
The source electrode of the 5th PMOS pipe M5 connects the supply voltage VIN of place chip;
The 6th PMOS pipe M6, its source electrode connects the feedback signal FB of place chip, and its grid connects the supply voltage VIN of place chip;
The first phase inverter X1, its output terminal is connected with the input end of the second phase inverter X2; The output terminal of the second phase inverter X2 is connected with the first input end D of d type flip flop X9;
D type flip flop X9, its second input end CLK is connected with the output of hex inverter X6, its first output terminal Q output enable control signal EN1, the second output terminal QB is unsettled;
The input of hex inverter X6 is connected with the output terminal of the 5th phase inverter X5.
3. adjusting corrected signal according to claim 1 produces circuit, it is characterized in that regulating amending unit (4), 16 identical module U0～U15 of structure, consist of, the input end of these modules U0～U15 is corresponding connected with 16 signal TM0～TM15 of 4-16 code translator (3) output respectively; A binary coded signal of each module output, the output of these 16 modules forms sixteen bit binary coded signal TRIM jointly.
4. adjusting corrected signal according to claim 3 produces circuit, it is characterized in that each module includes two input nand gate X10, a FUSE fuse X13, a resistance R 2, with a PMOS pipe, three NMOS pipes, two phase inverters, the 7th PMOS manages M14, the 8th NMOS pipe M15, the 9th NMOS pipe M16, the tenth NMOS pipe M17, the 7th phase inverter X11, the 8th phase inverter X12;
The 7th PMOS pipe M14, its drain electrode is connected with the drain electrode of the 9th NMOS pipe M16, and as the input of the 8th phase inverter X12, its source electrode is connected with the first end of fuse X13 with the drain electrode of the 8th NMOS pipe M15 respectively, the voltage bias signal VBIAS2 that its grid provides with outside is connected; A binary coded signal of output terminal output of the 8th phase inverter X12; The second end of fuse X13 is connected with the supply voltage VIN of place chip;
The 8th NMOS pipe M15, the current offset signal IBIAS2 that its source electrode provides with outside is connected; Grid is connected with one end of the first resistance R 2 with the output of the 7th phase inverter X11 respectively; The other end of the first resistance R 2 is connected to ground; The input end of the 7th phase inverter X11 is connected with the output terminal of two input nand gate X10; The first input end of two input nand gate X10 is connected with signal TM0～TM15; The second input end of two input nand gate X10 is connected with enable signal EN2;
The 9th NMOS pipe M16, its source electrode is connected with the drain electrode of the tenth NMOS pipe M17, and the voltage bias signal VBIAS3 that its grid provides with outside is connected;
The tenth NMOS pipe M17, its source electrode is connected to ground, and the voltage bias signal VBIAS4 that its grid provides with outside is connected;
The 9th NMOS pipe M16 is connected with the tenth NMOS pipe M17, and the input end for the 8th phase inverter X12 provides suitable operating voltage jointly.
5. adjusting corrected signal according to claim 1 produces circuit, it is characterized in that current offset unit (5), comprise three NMOS pipes, three resistance and two phase inverters, the 11 NMOS pipe M18, the 12 NMOS pipe M19, the 13 NMOS manage M20, the second resistance R 3, the 3rd resistance R 4, the 4th resistance R 5, the nine phase inverter X14, the tenth phase inverter X15;
The 11 NMOS pipe M18 is connected with the 12 NMOS pipe M19, forms the 3rd current mirror, the 11 NMOS pipe M18, and as the input end of the 3rd current mirror, its source electrode connects one end of the 3rd resistance R 4; The other end of the 3rd resistance R 4 is connected to ground; The grid of the 11 NMOS pipe M18 drains and is connected with self, and is connected with the source electrode of the 13 NMOS pipe M20 with the grid of the 12 NMOS pipe M19 respectively;
The 12 NMOS pipe M19, as the output terminal of the 3rd current mirror, its source electrode is connected with the 4th resistance R 5, its drain electrode output current offset signal IBIAS2;
The 13 NMOS pipe M20, its drain electrode connects one end of the second resistance R 3, and its grid is connected with the output of the tenth phase inverter X15; The input of the tenth phase inverter X15 is connected with the output of the 9th phase inverter X14; The input end of the 9th phase inverter X14 connects signal EN1, and the other end of the second resistance R 3 is connected with the supply voltage VIN of place chip.
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