CN103760392B - Adjusting corrected signal for DC-DC converter produces circuit - Google Patents
Adjusting corrected signal for DC-DC converter produces circuit Download PDFInfo
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- CN103760392B CN103760392B CN201410029320.XA CN201410029320A CN103760392B CN 103760392 B CN103760392 B CN 103760392B CN 201410029320 A CN201410029320 A CN 201410029320A CN 103760392 B CN103760392 B CN 103760392B
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Abstract
The invention discloses a kind of adjusting corrected signal for DC-DC converter and produce circuit, mainly solve existing converter throwing sheet and encapsulate the caused secondary offset issue of row index adjusting correction of advancing. This adjusting corrected signal produces circuit and comprises sequence generation unit (1), counter (2), and 4-16 decoder (3), regulates amending unit (4) and current offset unit (5); Sequence generation unit produces and the outer clock signal that signal pulse number is consistent that applies of chip; Counter is to this clock signal counting, obtain tetrad coding, export to decoder and carry out decoding, for regulating amending unit that enable signal is provided, simultaneously by current offset unit for regulating amending unit that bias current is provided, make fuse failure, adjusted corrected signal, exports external circuit to and carries out index correction. Regulatory function of the present invention can complete after chip package, has avoided the Quadratic deviation that causes because of encapsulation process, can be used for Analogous Integrated Electronic Circuits.
Description
Technical field
The invention belongs to electronic circuit technology field, relate to Analogous Integrated Electronic Circuits, especially for DC-DC converterRegulate corrected signal to produce circuit.
Background technology
Along with popularizing of the digital products such as portable media player, navigator, panel computer, power management chipObtain swift and violent development. DC-DC is widely used in and adopts because it has load capacity is strong, efficiency is high advantageBy the battery-powered occasion of lithium-ion electric. Along with the complexity of DC-DC design is more and more higher, be also subject to technological level simultaneouslyImpact, once throw the successful possibility of sheet also more and more less. For farthest cost-saving, people wish canAfter throwing sheet, measure easily relevant important technology index, and can regulate correction.
Fig. 1 has shown the system block diagram of existing DC-DC converter, and this DC-DC converter is by bandgap reference voltageVREF, bias current sources IBIAS, error amplifier, PWM comparator, logical drive, oscillator, slope compensation,Main switch, synchronous freewheeling pipe, feedback resistance RA, feedback resistance RB and pin FB, EN, VIN, LX, GNDComposition, wherein the analog circuit such as bandgap reference voltage VREF, bias current sources IBIAS is due to the deviation of manufacturing process,After throwing sheet, need to finely tune, to meet index request.
In integrated circuit, the normal mode that adopts blow current fuse is carried out index fine setting. Fig. 2 has provided conventional method employingThe circuit theory diagrams of electric current fuse regulon. Blow by fuse FUSE is passed into large electric current, change access K,The resistance size of L point-to-point transmission resistance, thus circuit index is regulated.
Traditional electric current fuse method for trimming is due to need be at fuse two ends access probe, thereby blows introducing large electric currentWhen processing, will be limited to the performance of recording device, simultaneously higher electric current also likely produces unexpected damage to recording deviceEvil, cause unnecessary loss, and maintenance cost is higher; Simultaneously due to carrying out in trim process, probe contact spacingLess, probe is easy to encounter and causes together short circuit. In addition be generally at chip package because tradition regulates modification methodBefore complete, after encapsulation, due to the impact of encapsulating material, packaging technology etc., can cause bandgap voltage reference, reference currentEtc. the secondary deviation of index.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned prior art, propose a kind of adjusting for DC-DC converterCorrected signal produces circuit, causes the secondary deviation of bandgap voltage reference and reference current index when avoiding chip package,Improve yield rate.
The technical thought that realizes the object of the invention is, in bandgap voltage reference and reference current module, by a switching tubeCarry out in parallelly with regulating resistance, adopt the opening or turn-offing of this switching tube of adjusting corrected signal control producing, thereby changeThe resistance value size of place in circuit, reaches the object regulating at the laggard row index of chip package.
Whole circuit of the present invention comprises: counter 2, and 4-16 decoder 3, current offset unit 5, is characterized in that:Also comprise sequence generation unit 1 and regulate amending unit 4;
Described sequence generation unit 1, for generation of having and the clock sequence of the additional square wave excitation same period of chipPULSE and enable signal EN1, this clock sequence PULSE is connected to counter 2, and this enable signal EN1 is connected toCurrent offset unit 5;
Described counter 2, carries out step-by-step counting for the square-wave signal that sequence generation unit 1 is produced, and exports fourBinary coded signal is to 4-16 decoder 3;
Described 4-16 decoder 3, carries out decoding for the tetrad code signal that counter 2 is exported, and will produceRaw decoded signal TM0～TM15 exports to and regulates amending unit 4, and it is enabled;
Described adjusting amending unit 4, for generation of regulating corrected signal TRIM, exports to the band that outside will be revisedGap voltage reference and current reference;
Described current offset unit 5, is used to and regulates amending unit 4 that current offset signal IBIAS2 is provided.
Above-mentioned adjusting corrected signal produces circuit, wherein sequence generation unit 1, comprise 6 PMOS pipes M1, M2,M3, M4, M5, M6,7 NMOS manage M7, M8, M9, M10, M11, M12, M13, and 6 are anti-Phase device X1, X2, X3, X4, X5, X6,1 rising edge testing circuit X7,1 rest-set flip-flop X8,1D type flip flop X9;
The one NMOS pipe M7, the 2nd NMOS pipe M8, the 3rd NMOS pipe M9, the 4th NMOS pipe M10,The 5th NMOS pipe M11 connects successively, forms the first current mirror;
The 2nd PMOS pipe M2 is connected with the 3rd PMOS pipe M3, forms the second current mirror;
The one NMOS pipe M7, as the input of the first current mirror, the outside bias current sources providing is provided in its drain electrodeIBIAS1; Its source electrode is connected to ground; Its grid drains and is connected with self, and manages the grid of M8 with the 2nd NMOS simultaneouslyExtremely connected;
The 2nd NMOS pipe M8, as the first output of the first current mirror, its drain electrode is with a PMOS pipe M1'sDrain electrode is connected, and as the input of the first phase inverter X1; Its source electrode is connected to ground; Its grid and the 3rd NMOS pipeThe grid of M9 is connected;
The 3rd NMOS pipe M9, as the second output of the first current mirror, its drain electrode is with the 2nd PMOS pipe M2'sDrain electrode is connected; Its source electrode is connected to ground; Its grid is connected with the grid of the 4th NMOS pipe M10;
The 4th NMOS pipe M10, as the 3rd output of the first current mirror, its drain electrode and the 3rd PMOS pipe M3Drain electrode be connected, and as the input of the 3rd phase inverter X3; Its source electrode is connected to ground; Its grid and the 5th NMOSThe grid of pipe M11 is connected;
The 5th NMOS pipe M11, as the 4th output of the first current mirror, its drain electrode and the 6th NMOS pipe M12Source electrode be connected; Its source electrode is connected to ground;
The 6th NMOS pipe M12, its drain electrode is connected with the drain electrode of the 4th PMOS pipe, and as rising edge testing circuitThe input of X7; Its grid is connected with the grid of the 5th PMOS pipe;
The 7th NMOS pipe M13, its drain electrode is connected with the drain electrode of the 6th PMOS pipe M6, and as the 5th phase inverterThe input of X5; Its source electrode is connected to ground; The outside voltage bias signal VBIAS1 providing is provided its grid;
The one PMOS pipe M1, its source electrode connects the enable signal EN of place chip; Grid connects the electricity of place chipSource voltage VIN;
The 2nd PMOS pipe M2, as the input of the second current mirror, its source electrode connects the supply voltage of place chipVIN; Its grid drains and is connected with self, and is connected with the grid of the 3rd PMOS pipe M3 simultaneously;
The 3rd PMOS pipe M3, as the output of the second current mirror, its source electrode respectively with the enable signal of place chipEN is connected with the grid of the 4th PMOS pipe M4;
The 4th PMOS pipe M4, its source electrode is connected with the supply voltage VIN of place chip, and it drains respectively with the 5thThe drain electrode of PMOS pipe M5 is connected with the input of rising edge testing circuit X7; The output of rising edge testing circuit X7End is connected with the input of the 4th phase inverter X4; The output of the 4th phase inverter X4 and rest-set flip-flop X8's is first defeatedEnter to hold R to be connected; The second input S of rest-set flip-flop X8 is connected with the output of the 3rd phase inverter X3; RS triggersThe first output Q of device X8 is connected with the grid of the 5th PMOS pipe M5, and output clock sequence signal PULSE,The second output QB of rest-set flip-flop X8 is unsettled;
The source electrode of the 5th PMOS pipe M5 connects the supply voltage VIN of place chip;
The 6th PMOS pipe M6, its source electrode connects the feedback signal FB of place chip, its grid connection place chipSupply voltage VIN;
The first phase inverter X1, its output is connected with the input of the second phase inverter X2; The output of the second phase inverter X2End is connected with the first input end D of d type flip flop X9;
D type flip flop X9, its second input CLK is connected with the output of hex inverter X6, its first output QOutput enable control signal EN1, the second output QB is unsettled;
The input of hex inverter X6 is connected with the output of the 5th phase inverter X5.
Above-mentioned adjusting corrected signal produces circuit, wherein regulates amending unit 4, by 16 module U0～U15 that structure is identicalComposition, 16 signal TM0～TM15 that the input of these modules U0～U15 is exported with 4-16 decoder 3 respectivelyCorresponding being connected; A binary coded signal of each module output, the output of these 16 modules forms sixteen bit two jointlyScale coding signal TRIM.
Above-mentioned adjusting corrected signal produces circuit, wherein the each module in module U0～U15 include one two input withNot gate X10, a FUSE fuse X13, a resistance R 2, and PMOS pipe, three NMOS pipes, twoIndividual phase inverter, i.e. the 7th PMOS pipe M14, the 8th NMOS pipe M15, the 9th NMOS pipe M16, the tenth NMOSPipe M17, the 7th phase inverter X11, the 8th phase inverter X12;
The 7th PMOS pipe M14, its drain electrode is connected with the drain electrode of the 9th NMOS pipe M16, and as the 8th phase inverterThe input of X12, its source electrode is connected with the first end of fuse X13 with the drain electrode of the 8th NMOS pipe M15 respectively, its gridThe voltage bias signal VBIAS2 that the utmost point provides with outside is connected; A binary system of output output of the 8th phase inverter X12Code signal; The second end of fuse X13 is connected with the supply voltage VIN of place chip;
The 8th NMOS pipe M15, the current offset signal IBIAS2 that its source electrode provides with outside is connected; Grid respectively withThe output of the 7th phase inverter X11 is connected with one end of the first resistance R 2; The other end of the first resistance R 2 is connected to ground;The input of the 7th phase inverter X11 is connected with the output of two input nand gate X10; Of two input nand gate X10One input is connected with signal TM0～TM15; The second input of two input nand gate X10 and enable signal EN2 phaseConnect;
The 9th NMOS pipe M16, its source electrode is connected with the drain electrode of the tenth NMOS pipe M17, and its grid and outside are carriedThe voltage bias signal VBIAS3 of confession is connected;
The tenth NMOS pipe M17, its source electrode is connected to ground, its grid and the outside voltage bias signal VBIAS4 providingBe connected;
The 9th NMOS pipe M16 is connected with the tenth NMOS pipe M17, is the input of the 8th phase inverter X12 jointlySuitable operating voltage is provided.
Above-mentioned adjusting corrected signal produces circuit, and wherein current offset unit 5 comprises three NMOS pipes, three resistanceWith two phase inverters, i.e. the 11 NMOS pipe M18, the 12 NMOS pipe M19, the 13 NMOS pipe M20,The second resistance R 3, the 3rd resistance R 4, the 4th resistance R 5, the nine phase inverter X14, the tenth phase inverter X15;
The 11 NMOS pipe M18 is connected with the 12 NMOS pipe M19, forms the 3rd current mirror, the 11NMOS manages M18, and as the input of the 3rd current mirror, its source electrode connects one end of the 3rd resistance R 4; The 3rd resistanceThe other end of R4 is connected to ground; The grid of the 11 NMOS pipe M18 drains and is connected with self, and respectively with the tenthThe grid of two NMOS pipe M19 is connected with the source electrode of the 13 NMOS pipe M20;
The 12 NMOS pipe M19, as the output of the 3rd current mirror, its source electrode is connected with the 4th resistance R 5, itsDrain electrode output current offset signal IBIAS2;
The 13 NMOS pipe M20, its drain electrode connects one end of the second resistance R 3, its grid and the tenth phase inverter X15Output be connected; The input of the tenth phase inverter X15 is connected with the output of the 9th phase inverter X14; The 9th phase inverter X14Input connect signal EN1, the other end of the second resistance R 3 is connected with the supply voltage VIN of place chip.
The present invention due to the indoor design at DC-DC chip clock sequence generation unit and fuse regulate amending unit,Compared with adopting the method for additional probe blown fuse, can directly produce and regulate corrected signal in the inside of DC-DC chip,And completing technology index adjustment process, avoid the impact on recording device generation, reduce cost, and fusing processSafer to chip, can improve yield rate; Simultaneously because this adjusting corrected signal is to produce at DC-DC chip internal,Therefore can after completing, chip package adjust its technical indicator, with regulate correction before chip package compared with, and canWith the Quadratic deviation of avoiding encapsulation process to bring.
Brief description of the drawings
Fig. 1 is the system block diagram of existing DC-DC converter;
Fig. 2 is the circuit theory diagrams of the electric current fuse regulon of conventional method employing;
Fig. 3 is that adjusting corrected signal of the present invention produces circuit block diagram;
Fig. 4 is the sequence generation element circuit schematic diagram in the present invention;
Fig. 5 is the adjusting amending unit structured flowchart in the present invention;
Fig. 6 is the adjusting amending unit circuit theory diagrams in the present invention;
Fig. 7 is the current offset element circuit schematic diagram in the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing and embodiment, the invention will be further described.
With reference to Fig. 3, adjusting corrected signal of the present invention produces circuit and comprises: sequence generation unit 1, counter 2,4-16Decoder 3, regulates amending unit 4 and current offset unit 5, wherein:
Described sequence generation unit 1, for generation of having and the clock sequence of the additional square wave excitation same period of chipPULSE and enable signal EN1, this clock sequence PULSE is connected to counter 2, and this enable signal EN1 is connected toCurrent offset unit 5;
Described counter 2, carries out step-by-step counting for the square-wave signal that sequence generation unit 1 is produced, and exports fourBinary coded signal is to 4-16 decoder 3;
Described 4-16 decoder 3, carries out decoding for the tetrad code signal that counter 2 is exported, and will produceRaw decoded signal TM0～TM15 exports to and regulates amending unit 4, and it is enabled;
Described adjusting amending unit 4, for generation of regulating corrected signal TRIM, exports to the band that outside will be revisedGap voltage reference and current reference;
Described current offset unit 5, is used to and regulates amending unit 4 that current offset signal IBIAS2 is provided.
With reference to Fig. 4, sequence generation of the present invention unit 1, comprise six PMOS pipe M1, M2, M3, M4, M5,M6, seven NMOS pipe M7, M8, M9, M10, M11, M12, M13, six phase inverter X1, X2,X3, X4, X5, X6, a rising edge testing circuit X7, a rest-set flip-flop X8, a d type flip flop X9;
The one NMOS pipe M7, the 2nd NMOS pipe M8, the 3rd NMOS pipe M9, the 4th NMOS pipe M10,The 5th NMOS pipe M11 connects successively, forms the first current mirror;
The 2nd PMOS pipe M2 is connected with the 3rd PMOS pipe M3, forms the second current mirror;
The one NMOS pipe M7, as the input of the first current mirror, the outside bias current sources providing is provided in its drain electrodeIBIAS1; Its source electrode is connected to ground; Its grid drains and is connected with self, and manages the grid of M8 with the 2nd NMOS simultaneouslyExtremely connected;
The 2nd NMOS pipe M8, as the first output of the first current mirror, its drain electrode is with a PMOS pipe M1'sDrain electrode is connected, and as the input of the first phase inverter X1; Its source electrode is connected to ground; Its grid and the 3rd NMOS pipeThe grid of M9 is connected;
The 3rd NMOS pipe M9, as the second output of the first current mirror, its drain electrode is with the 2nd PMOS pipe M2'sDrain electrode is connected; Its source electrode is connected to ground; Its grid is connected with the grid of the 4th NMOS pipe M10;
The 4th NMOS pipe M10, as the 3rd output of the first current mirror, its drain electrode and the 3rd PMOS pipe M3Drain electrode be connected, and as the input of the 3rd phase inverter X3; Its source electrode is connected to ground; Its grid and the 5th NMOSThe grid of pipe M11 is connected;
The 5th NMOS pipe M11, as the 4th output of the first current mirror, its drain electrode and the 6th NMOS pipe M12Source electrode be connected; Its source electrode is connected to ground;
The 6th NMOS pipe M12, its drain electrode is connected with the drain electrode of the 4th PMOS pipe, and as rising edge testing circuitThe input of X7; Its grid is connected with the grid of the 5th PMOS pipe;
The 7th NMOS pipe M13, its drain electrode is connected with the drain electrode of the 6th PMOS pipe M6, and as the 5th phase inverterThe input of X5; Its source electrode is connected to ground; The outside voltage bias signal VBIAS1 providing is provided its grid;
The one PMOS pipe M1, its source electrode connects the enable signal EN of place chip; Its grid connects place chipSupply voltage VIN;
The 2nd PMOS pipe M2, as the input of the second current mirror, its source electrode connects the supply voltage of place chipVIN; Its grid drains and is connected with self, and is connected with the grid of the 3rd PMOS pipe M3 simultaneously;
The 3rd PMOS pipe M3, as the output of the second current mirror, its source electrode respectively with the enable signal of place chipEN is connected with the grid of the 4th PMOS pipe M4;
The 4th PMOS pipe M4, its source electrode is connected with the supply voltage VIN of place chip;
The 5th PMOS pipe M5, its drain electrode is connected with the drain electrode of the 4th PMOS pipe; Its source electrode connects the electricity of place chipSource voltage VIN;
The 6th PMOS pipe M6, its source electrode connects the feedback signal FB of place chip; Its grid connects place chipSupply voltage VIN;
The first phase inverter X1, its output is connected with the input of the second phase inverter X2;
The second phase inverter X2, its output is connected with the first input end D of d type flip flop X9;
The 3rd phase inverter X3, its output is connected with the second input S of rest-set flip-flop X8;
The 4th phase inverter X4, its input is connected with the output of rising edge testing circuit X7; Its output and RS triggerThe first input end R of device X8 is connected;
The 5th phase inverter X5, its output is connected with the input of hex inverter X6;
Hex inverter X6, its output is connected with the second input CLK of d type flip flop X9;
Rest-set flip-flop X8, its first output Q is connected with the grid of the 5th PMOS pipe M5, and output clock sequenceSignal PULSE; QB is unsettled for its second output;
D type flip flop X9, its first output Q output enable control signal EN1; QB is unsettled for its second output.
Above-mentioned sequence generation unit 1 mainly contains two functions: the one, and make DC-DC chip enter tune by normal mode of operationJoint modification model; The 2nd, entering generation adjusting clock sequence PULSE after adjusting modification model.
The principle that realizes above-mentioned two functions is as follows:
When the EN leads ends at DC-DC chip applies high voltage, make it meet VEN>VVIN, wherein VENFor EN drawsThe magnitude of voltage of foot, VVINFor the magnitude of voltage of input power, now the first input end D of d type flip flop X9 is connected toHigh level; Then, apply high voltage in feedback voltage FB leads ends, make it meet VFB>VVIN+|VTHP(M6)|, whereinVFBFor the magnitude of voltage of FB leads ends, VTHP(M6)It is the threshold voltage of the 6th PMOS pipe M6. Now at d type flip flopThe second input CLK place of X9 will produce a rising edge clock signal, make the first output of d type flip flop X9The signal EN1 that Q exports becomes high level from low level, thereby makes chip enter adjusting modification model, and realizing shouldFirst function of sequence generation unit 1.
When in the time that the EN of DC-DC chip leads ends applies high voltage, make a point be pulled to high level, RS triggersThe second input S of device X8 will become low level, thereby make signal PULSE output high level.
When the EN leads ends at DC-DC chip applies low-voltage, make the 3rd PMOS pipe M3 cut-off, a point voltageBe pulled down to low level, therefore the second input S of rest-set flip-flop X8 becomes high level. Now, the 4th PMOSPipe M4 conducting, b point is pulled to high level, by rising edge testing circuit X7 and the 4th phase inverter X4, makes RSThe first input end R of trigger X8 becomes low level, thus signal PULSE output low level.
Apply by the EN leads ends at DC-DC chip the square wave clock signal that height changes, can obtain and inputThe adjusting clock sequence PULSE that square wave clock signal pulse number is identical, to realize second of this sequence generation unit 1Individual function.
With reference to Fig. 5, adjusting amending unit 4 of the present invention, is made up of 16 identical module U0～U15 of structure, thisCorresponding being connected of 16 signal TM0～TM15 that the input of a little module U0～U15 is exported with 4-16 decoder 3 respectively,The input that is first module U0 is connected with first signal TM0 of 4-16 decoder output, second module U1Second signal TM1 of input and 4-16 decoder output be connected, input and the 4-16 of the 3rd module U2The 3rd signal TM2 of decoder output is connected, the input of the 4th module U3 and 4-16 decoder are exported theThe 5th the signal TM4 phase that four signal TM3 are connected, the input of the 5th module U4 and 4-16 decoder are exportedThe 6th the signal TM5 connect, the input of the 6th module U5 being exported with 4-16 decoder is connected, the 7th moduleThe input of U6 is connected with the 7th signal TM6 of 4-16 decoder output, input and the 4-16 of the 8th module U7The 8th signal TM7 of decoder output is connected, the input of the 9th module U8 and 4-16 decoder are exported theThe tenth the signal TM9 phase that nine signal TM8 are connected, the input of the tenth module U9 and 4-16 decoder are exportedConnect, the input of the 11 module U10 is connected with the 11 signal TM10 of 4-16 decoder output, the tenthThe 12 the signal TM11 that the input of two module U11 is exported with 4-16 decoder 3 is connected, the 13 mouldThe 13 signal TM12 of the input of piece U12 and 4-16 decoder output be connected, the 14 module U13The 14 signal TM13 of input and 4-16 decoder output is connected, the input of the 15 module U14 andThe 15 signal TM14 of 4-16 decoder output is connected, input and the 4-16 decoding of the 16 module U15The 16 signal TM15 of device output is connected. A binary coded signal of each module output, these 16 modulesOutput jointly form sixteen bit binary coded signal TRIM.
With reference to Fig. 6, the present invention regulates in 16 module U0～U15 of amending unit, and its each module includes oneTwo input nand gate X10, a FUSE fuse X13, a resistance R 2, and PMOS pipe, three NMOSPipe, two phase inverters, i.e. the 7th PMOS pipe M14, the 8th NMOS pipe M15, the 9th NMOS pipe M16,The tenth NMOS pipe M17, the 7th phase inverter X11, the 8th phase inverter X12;
The 7th PMOS pipe M14, its drain electrode is connected with the drain electrode of the 9th NMOS pipe M16, and as the 8th phase inverterThe input of X12; Its source electrode is connected with one end of fuse X13 with the drain electrode of the 8th NMOS pipe M15 respectively; Its gridThe voltage bias signal VBIAS2 providing with outside is connected;
The 8th NMOS pipe M15, the current offset signal IBIAS2 that its source electrode provides with outside is connected; Its grid andThe output of seven phase inverter X11 is connected, and is connected to one end of the first resistance R 2;
The 9th NMOS pipe M16, its source electrode is connected with the drain electrode of the tenth NMOS pipe M17; Its grid and outside are carriedThe voltage bias signal VBIAS3 of confession is connected;
The tenth NMOS pipe M17, its source electrode is connected to ground; Its grid and the outside voltage bias signal VBIAS4 providingBe connected;
The 9th NMOS pipe M16 is connected with the tenth NMOS pipe M17, is the input of the 8th phase inverter X12 jointlySuitable operating voltage is provided.
Two input nand gate X10, its first input end is connected with signal TM0～TM15; Its second input with enableSignal EN2 is connected; Its output is connected with the input of the 7th phase inverter X11;
Fuse X13, its other end is connected with the supply voltage VIN of place chip;
Resistance R 2, its other end is connected to ground;
The 8th phase inverter X12, a binary coded signal of its output output.
With reference to Fig. 6, in the time that chip enters adjusting modification model, the second input end signal EN2 of two input nand gate X10Become high level, in the time that any one in signal TM0～TM15 becomes high level, of two input nand gate X10One input will become high level, thereby make the 8th NMOS pipe M15 conducting. Now exported by current offset unitThe bias current IBIAS2 fuse X13 that flows through, is fused this fuse, thereby c point voltage is become to low level, makesThe output signal of eight phase inverter X12 becomes high level, and this high level signal is connected to outside bandgap reference voltage and electric currentBenchmark regulates correction.
With reference to Fig. 7, current offset of the present invention unit 5, comprises three NMOS pipes, three resistance and two phase inverters,I.e. the 11 NMOS pipe M18, the 12 NMOS pipe M19, the 13 NMOS pipe M20, the second resistance R 3,The 3rd resistance R 4, the 4th resistance R 5, the nine phase inverter X14, the tenth phase inverter X15, wherein:
The 11 NMOS pipe M18 is connected with the 12 NMOS pipe M19, forms the 3rd current mirror;
The 11 NMOS pipe M18, as the input of the 3rd current mirror, its source class connects one end of the 3rd resistance R 4;Its grid drains and is connected with self, and manages M20 with grid and the 13 NMOS of the 12 NMOS pipe M19 respectivelySource electrode be connected;
The 12 NMOS pipe M19, as the output of the 3rd current mirror, its source electrode connects one end of the 4th resistance R 5;Its drain electrode output current offset signal IBIAS2;
The 13 NMOS pipe M20, its drain electrode connects one end of the second resistance R 3; Its grid and the tenth phase inverter X15Output be connected;
The second resistance R 3, its other end is connected with the supply voltage VIN of place chip;
The 3rd resistance R 4, its other end is connected to ground;
The 4th resistance R 5, its other end is connected to ground;
The 9th phase inverter X14, its input is connected with signal EN1; The input of its output and the tenth phase inverter X15Be connected.
With reference to Fig. 7, in the time that the input end signal EN1 of the 9th phase inverter X14 becomes high level, chip enters to regulate and repaiiesHolotype, makes the 13 NMOS pipe M20 conducting, thus in the 11 NMOS pipe M18, there is electric current to pass through, warpCross the mirror image effect of the 3rd current mirror, by the 12 NMOS pipe M19 output current offset signal IBIAS2, be connected toRegulate in amending unit 4.
Operation principle of the present invention is as follows:
In the time applying pulse number in the EN of DC-DC leads ends and be the square wave clock signal CLK of n, 1≤n≤16,Sequence generation unit 1 can be converted into signal CLK pulse number and be similarly the signal PULSE of n, then counter 2Pulse number to signal PULSE is counted, and obtains tetrad coding, and exports in 4-16 decoder 3.4-16 decoder 3 carries out decoded operation, and exports high level enable signal, and this high level enable signal can make to regulate and reviseFuse module U0～U15 in unit 4 starts working, the bias current IBIAS2 that now current offset unit 5 is exportedFuse in the module of flowing through U0～U15, is fused this fuse, then can obtain at the output that regulates amending unit 4Regulate corrected signal TRIM, this signal TRIM exports outside bandgap reference voltage and current reference to carry out index and repaiiesJust.
Below be only a preferred example of the present invention, do not form any limitation of the invention, obviously at structure of the present inventionUnder think of, can carry out different changes and improvement to its circuit, but these are all at the row of protection of the present invention.
Claims (4)
1. produce a circuit for the adjusting corrected signal of DC-DC converter, comprise counter (2), 4-16 decoder(3), current offset unit (5), is characterized in that: also comprise sequence generation unit (1) and regulate amending unit (4);
Described sequence generation unit (1), for generation of having and the additional square wave excitation same period of DC-DC converter chipClock sequence PULSE and enable signal EN1, this clock sequence PULSE is connected to counter (2), this enables letterNumber EN1 is connected to current offset unit (5);
Described counter (2), carries out step-by-step counting for the square-wave signal that sequence generation unit (1) is produced, and exports fourPosition binary coded signal is to 4-16 decoder (3);
Described 4-16 decoder (3), for the tetrad code signal of counter (2) output is carried out to decoding, and willDecoded signal TM0～the TM15 producing exports to and regulates amending unit (4), and it is enabled;
Described adjusting amending unit (4), for generation of regulating corrected signal TRIM, exports to the band that outside will be revisedGap voltage reference and current reference, this adjusting amending unit is made up of 16 identical module U0～U15 of structure, theseThe input of module U0～U15 is corresponding connected with 16 signal TM0～TM15 of 4-16 decoder (3) output respectively;A binary coded signal of each module output, the output of these 16 modules forms sixteen bit binary coding letter jointlyNumber TRIM;
Described current offset unit (5), is used to and regulates amending unit (4) that current offset signal IBIAS2 is provided.
2. the adjusting corrected signal for DC-DC converter according to claim 1 produces circuit, and its feature existsIn sequence generation unit (1), comprise 6 PMOS pipes M1, M2, M3, M4, M5, M6,7 NMOSPipe M7, M8, M9, M10, M11, M12, M13,6 phase inverter X1, X2, X3, X4, X5, X6,1 rising edge testing circuit X7,1 rest-set flip-flop X8,1 d type flip flop X9;
The one NMOS pipe M7, the 2nd NMOS pipe M8, the 3rd NMOS pipe M9, the 4th NMOS pipe M10,The 5th NMOS pipe M11 connects successively, forms the first current mirror;
The 2nd PMOS pipe M2 is connected with the 3rd PMOS pipe M3, forms the second current mirror;
The one NMOS pipe M7, as the input of the first current mirror, the outside bias current sources providing is provided in its drain electrodeIBIAS1; Its source electrode is connected to ground; Its grid drains and is connected with self, and manages the grid of M8 with the 2nd NMOS simultaneouslyExtremely connected;
The 2nd NMOS pipe M8, as the first output of the first current mirror, its drain electrode is with a PMOS pipe M1'sDrain electrode is connected, and as the input of the first phase inverter X1; Its source electrode is connected to ground; Its grid and the 3rd NMOS pipeThe grid of M9 is connected;
The 3rd NMOS pipe M9, as the second output of the first current mirror, its drain electrode is with the 2nd PMOS pipe M2'sDrain electrode is connected; Its source electrode is connected to ground; Its grid is connected with the grid of the 4th NMOS pipe M10;
The 4th NMOS pipe M10, as the 3rd output of the first current mirror, its drain electrode and the 3rd PMOS pipe M3Drain electrode be connected, and as the input of the 3rd phase inverter X3; Its source electrode is connected to ground; Its grid and the 5th NMOSThe grid of pipe M11 is connected;
The 5th NMOS pipe M11, as the 4th output of the first current mirror, its drain electrode and the 6th NMOS pipe M12Source electrode be connected; Its source electrode is connected to ground;
The 6th NMOS pipe M12, its drain electrode is connected with the drain electrode of the 4th PMOS pipe M4, and detects as rising edgeThe input of circuit X7; Its grid is connected with the grid of the 5th PMOS pipe M5;
The 7th NMOS pipe M13, its drain electrode is connected with the drain electrode of the 6th PMOS pipe M6, and as the 5th phase inverterThe input of X5; Its source electrode is connected to ground; The outside voltage bias signal VBIAS1 providing is provided its grid;
The one PMOS pipe M1, its source electrode connects the enable signal EN of place DC-DC converter chip; Grid connectsThe supply voltage VIN of place DC-DC converter chip;
The 2nd PMOS pipe M2, as the input of the second current mirror, its source electrode connects place DC-DC converter coreThe supply voltage VIN of sheet; Its grid drains and is connected with self, and is connected with the grid of the 3rd PMOS pipe M3 simultaneously;
The 3rd PMOS pipe M3, as the output of the second current mirror, its source electrode respectively with place DC-DC converterThe enable signal EN of chip is connected with the grid of the 4th PMOS pipe M4;
The 4th PMOS pipe M4, its source electrode is connected with the supply voltage VIN of place DC-DC converter chip, its leakageThe utmost point is connected with the input of rising edge testing circuit X7 with the drain electrode of the 5th PMOS pipe M5 respectively; Rising edge detects electricityThe output of road X7 is connected with the input of the 4th phase inverter X4; The output of the 4th phase inverter X4 and rest-set flip-flopThe first input end R of X8 is connected; The second input S of rest-set flip-flop X8 and the output phase of the 3rd phase inverter X3Connect; The first output Q of rest-set flip-flop X8 is connected with the grid of the 5th PMOS pipe M5, and output clock sequencePULSE, the second output QB of rest-set flip-flop X8 is unsettled;
The source electrode of the 5th PMOS pipe M5 connects the supply voltage VIN of place DC-DC converter chip;
The 6th PMOS pipe M6, its source electrode connects the feedback signal FB of place DC-DC converter chip, and its grid connectsMeet the supply voltage VIN of place DC-DC converter chip;
The first phase inverter X1, its output is connected with the input of the second phase inverter X2; The output of the second phase inverter X2End is connected with the first input end D of d type flip flop X9;
D type flip flop X9, its second input CLK is connected with the output of hex inverter X6, its first output QOutput enable signal EN1, the second output QB is unsettled;
The input of hex inverter X6 is connected with the output of the 5th phase inverter X5.
3. the adjusting corrected signal for DC-DC converter according to claim 1 produces circuit, and its feature existsEach module in regulating amending unit (4) include two input nand gate X10, FUSE fuse X13,A resistance R 2, and PMOS pipe, three NMOS pipes, two phase inverters, i.e. the 7th PMOS pipe M14,The 8th NMOS pipe M15, the 9th NMOS pipe M16, the tenth NMOS pipe M17, the 7th phase inverter X11, theEight phase inverter X12;
The 7th PMOS pipe M14, its drain electrode is connected with the drain electrode of the 9th NMOS pipe M16, and as the 8th phase inverterThe input of X12, its source electrode is connected with the first end of FUSE fuse X13 with the drain electrode of the 8th NMOS pipe M15 respectively,The voltage bias signal VBIAS2 that its grid provides with outside is connected; One two of the output output of the 8th phase inverter X12Scale coding signal; The supply voltage VIN phase of the second end of FUSE fuse X13 and place DC-DC converter chipConnect;
The 8th NMOS pipe M15, the current offset signal IBIAS2 that its source electrode provides with outside is connected, grid respectively withThe output of the 7th phase inverter X11 is connected with one end of the first resistance R 2; The other end of the first resistance R 2 is connected to ground;The input of the 7th phase inverter X11 is connected with the output of two input nand gate X10; Of two input nand gate X10One input is connected with signal TM0～TM15; The second input of two input nand gate X10 and enable signal EN2 phaseConnect;
The 9th NMOS pipe M16, its source electrode is connected with the drain electrode of the tenth NMOS pipe M17, and its grid and outside are carriedThe voltage bias signal VBIAS3 of confession is connected;
The tenth NMOS pipe M17, its source electrode is connected to ground, its grid and the outside voltage bias signal VBIAS4 providingBe connected;
The 9th NMOS pipe M16 is connected with the tenth NMOS pipe M17, is the input of the 8th phase inverter X12 jointlySuitable operating voltage is provided.
4. the adjusting corrected signal for DC-DC converter according to claim 1 produces circuit, and its feature existsIn current offset unit (5), comprise three NMOS pipes, three resistance and two phase inverters, i.e. the 11 NMOS pipeM18, the 12 NMOS pipe M19, the 13 NMOS pipe M20, the second resistance R 3, the 3rd resistance R 4, theFour resistance R 5, the nine phase inverter X14, the tenth phase inverter X15;
The 11 NMOS pipe M18 is connected with the 12 NMOS pipe M19, forms the 3rd current mirror, the 11NMOS manages M18, and as the input of the 3rd current mirror, its source electrode connects one end of the 3rd resistance R 4; The 3rd resistanceThe other end of R4 is connected to ground; The grid of the 11 NMOS pipe M18 drains and is connected with self, and respectively with the tenthThe grid of two NMOS pipe M19 is connected with the source electrode of the 13 NMOS pipe M20;
The 12 NMOS pipe M19, as the output of the 3rd current mirror, its source electrode is connected with the 4th resistance R 5, itsDrain electrode output current offset signal IBIAS2;
The 13 NMOS pipe M20, its drain electrode connects one end of the second resistance R 3, its grid and the tenth phase inverter X15Output be connected; The input of the tenth phase inverter X15 is connected with the output of the 9th phase inverter X14; The 9th phase inverter X14Input connect enable signal EN1, the power supply of the other end of the second resistance R 3 and place DC-DC converter chipVoltage VIN is connected.
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