CN1913142A - Circuit board and circuit apparatus using the same - Google Patents

Circuit board and circuit apparatus using the same Download PDF

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Publication number
CN1913142A
CN1913142A CNA2006101100267A CN200610110026A CN1913142A CN 1913142 A CN1913142 A CN 1913142A CN A2006101100267 A CNA2006101100267 A CN A2006101100267A CN 200610110026 A CN200610110026 A CN 200610110026A CN 1913142 A CN1913142 A CN 1913142A
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CN
China
Prior art keywords
metal substrate
hole
circuit
face
projection
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Granted
Application number
CNA2006101100267A
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Chinese (zh)
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CN100433321C (en
Inventor
柴田清司
臼井良辅
井上恭典
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication of CN1913142A publication Critical patent/CN1913142A/en
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Publication of CN100433321C publication Critical patent/CN100433321C/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

A circuit board and a circuit apparatus using the same which can prevent displacement and film exfoliation ascribable to thermal expansion, and suppress a drop in reliability at increasing temperatures. The circuit board of the circuit apparatus includes a metal substrate having pierced holes as a core member. Protrusions are formed on the top ends of the pierced holes, and depressions are formed in the bottom ends of the pierced holes. Wiring pattern layers are formed on both sides of this metal substrate via respective insulating layers. In order to establish electrical connection between the wiring pattern layers, a conductor layer which connects the wiring pattern layers is formed through the metal substrate via the pierced holes. The conductor layer thereby establishes electrical conduction between the wiring pattern layers. Furthermore, a semiconductor chip is directly connected to the surface side of the circuit board via solder balls.

Description

Circuit substrate and use the circuit arrangement of this circuit substrate
Technical field
The present invention relates to circuit substrate and use the circuit arrangement of this circuit substrate, particularly will be located at the circuit substrate of core and use the circuit arrangement of this circuit substrate based on the substrate of metal.
Background technology
In the acceleration of the multifunction of portable electric appts such as mobile phone, PDA, DVC and DSC, this series products in order to achieve this end, requires high integrated system LSI in order need to be accepted small-sized, lightweight by market.The another side also requires operability more easily to such electronic equipment.Therefore, be accompanied by the highly integrated of LSI chip, the I/O number increases, and the miniaturization of packaging body self requires also to have improved, and for satisfying both simultaneously, strong request is suitable for the exploitation of the semiconductor package part that the highdensity substrate of semiconductor device installs.In the face of such requirement, (ChipSize Package: encapsulation technology chip size packages) is done various exploitations to CSP.
The for example known BGA of such packaging part (Ball Grid Array: ball grid array).BGA be with semiconductor chip be installed in packaging part with on the substrate and with its carry out resin molded after, on the one side of opposition side, form the structure of solder ball as outside terminal with area-shaped.Among the BGA, realize with face the installation region, so can make packaging part miniaturization more easily.In addition, the circuit substrate side also need not be carried out narrow pitch correspondence, does not also need high-precision mounting technique, so if use BGA, even total the installation cost that also can reduce under the higher a little situation of packaging cost.
Figure 17 is the schematic configuration schematic diagram of the general BGA of expression.BGA 100 has the structure of carrying LSI chip 102 on glass epoxy resin substrate 106 via adhesive linkage 108.LSI chip 102 is molded by sealing resin 110.LSI chip 102 and glass epoxy resin substrate 106 are electrically connected by metal wire 104.Arrange solder ball 112 in the back side of glass epoxy resin substrate 106 array-like.Via this solder ball 112 BGA 100 is installed on the printed wiring board.
In addition, in recent years, the semiconductor package part that electronic equipment etc. contain (circuit arrangement) is for further realizing miniaturization, densification and multifunction, and the heat release density of unit volume increases.The increase of such heat release density becomes the circuit arrangement Performance And Reliability is brought dysgenic reason, becomes big problem.Therefore, replace glass epoxy resin substrate 106 as the circuit substrate of forming circuit device and use metal substrate with high-cooling property etc.
Figure 18 is the summary section of other structures of expression patent documentation 1 disclosed existing circuit arrangement.With reference to Figure 18, in the circuit substrate 210 that constitutes existing circuit arrangement 200, the inner metal substrate 201 that uses of circuit substrate is as core components, and its two sides side forms Wiring pattern layer 203,205 via resin insulating barrier 202,204.And,, the through hole (Consistent through hole) that is called as reach through hole (through hole) 206 is set on plate thickness direction for making each layer electrical connection.The reach through hole inner face obtains the conducting of each layer by formation electrical conductivity layers 207 such as copper platings.And then, directly connect semiconductor chip 220 in a face side of circuit substrate 210 via solder ball 221.
Patent documentation 1: the spy opens the 2002-335057 communique
Generally, the metal material that is used for metal substrate 201 requires the character of low-thermal-expansion rate.But, the resin coefficient of thermal expansion height that uses in the insulating barrier 202, the coefficient of thermal expansion that for example is used for the Fe-Ni-Co alloy of metal substrate is 10 * 10 -6/ K, the coefficient of thermal expansion of copper (Cu) is 6～9 * 10 -6/ K.With respect to this, the coefficient of thermal expansion that is used for the epoxy resin of dielectric film is 60～70 * 10 -6/ K, dielectric film have about 10 times of high coefficient of thermal expansions of metal substrate.Because such character is poor, the temperature rising with circuit substrate 210 is formed on the Wiring pattern layer 203 on the insulating barrier 202 and produces position deviation.Figure 19 is the profile that produces the circuit substrate of position deviation owing to the temperature rising.In addition, among the figure, dotted line represents not bring because of thermal expansion the electrical conductivity layer 207a of the state of deviation.As shown in figure 19, reach through hole 206 interior electrical conductivity layer 207 part that form than metal substrate 201, Wiring pattern layer 203 part that are provided with on the insulating barrier 202 are bigger because of the mobile distance of expansion (departure that expansion brings), and relative deviation appears in both patterns.Circuit substrate 210 variations in temperature make under this deviation situation repeatedly, can slight crack occur between Wiring pattern layer 203 and electrical conductivity layer 207.Therefore, this part bad connection that becomes produces the problem that the reliability of circuit arrangement reduces.In addition, metal substrate 201 and insulating barrier 202 are only bonding with the connecting airtight property of contact-making surface, so the departure that is caused by the expansion of insulating barrier 202 also can cause from the problem of metal substrate 201 strippings.As a result, circuit substrate 210 and use the reliability of the circuit arrangement of this circuit substrate to reduce.
In addition, generally, be used for having the compression stress (stress of the direction that wiring material shrinks) that forming process produces on the wiring material (for example copper) of circuit substrate 210, wiring material forms operation and is processed under the state of desirable Wiring pattern layer 203,205 through pattern, also Wiring pattern layer 203,205 remaining compression stress (stress A, B).And then, the distribution density that is used for the Wiring pattern layer is big more, corresponding residual compression stress with it is big more, so as shown in figure 18, the distribution density of the Wiring pattern layer 203 that is provided with on the face of metal substrate 201 is than under the high situation of the Wiring pattern layer that is provided with on another face 205, and the compression stress (compression stress of the residual quantity of stress A and stress B) of effect Wiring pattern layer 203 side impacts circuit substrate 210.
Figure 20 is the profile of circuit arrangement with circuit substrate of distortion.As shown in figure 20, the compression stress of Wiring pattern layer 203 side effect (tensile stress of the stress A of Figure 19 and the residual quantity of stress B) becomes under the situation of stress of the rigidity that exceeds circuit substrate 210 (particularly metal substrate 201), and circuit substrate 210 compresses buckling deformation repeatedly in Wiring pattern layer 203 side.Particularly, Wiring pattern layer 203 side, to Wiring pattern layer 203 and resin insulating barrier 202 effect compression stresses (stress of the direction of material contracts), opposite Wiring pattern layer 205 side are to Wiring pattern layer 205 and resin insulating barrier 204 effect tensile stresses (stress of the direction of material extending).The result, on the Wiring pattern layer 203,205 because the migration of wiring material takes place easily, so can cause the distribution reliability to reduce, peeling off of metal substrate 201 and Wiring pattern layer can appear on resin insulating barrier 202,204, as a whole, damage the reliability of circuit arrangement 200 with circuit substrate 210.
Summary of the invention
The present invention is in view of the above problems and research and development, and its purpose is to provide a kind of position deviation and stripping that thermal expansion brings of can controlling, and the circuit substrate of the reduction of the reliability when suppressing temperature and rising and use the circuit arrangement of this circuit substrate.
For solving above-mentioned problem, circuit arrangement of the present invention comprises: the metal substrate with a plurality of through holes; Be arranged on first wiring layer on the face of a side of described metal substrate via first insulating barrier; Be arranged on second wiring layer on the face of opposite side of described metal substrate via second insulating barrier; Conductor layer, it connects described metal substrate via at least a portion through hole in described a plurality of through holes, and described first wiring layer is connected with second wiring layer; The circuit element that is connected with described first wiring layer on the face of a side of described metal substrate, wherein, the ora terminalis of at least one side that the surperficial upper edge of described metal substrate is provided with the through hole of described conductor layer is provided with projection.
According to the present invention, along the ora terminalis of the through hole that is provided with conductor layer and the projection that is provided with by the anchoring effect insulating barrier that jam-packed expands when the circuit substrate temperature rises, can reduce the pattern deviation (perhaps be connected the distortion of the conductor layer of two wiring layers: the position deviation of the connecting portion of the position of the conductor layer in the through hole of metal substrate and first and second wiring layer) particularly of the wiring layer that metal substrate and thermal expansion rate variance between insulating barrier cause.
In addition, owing to increased the contact area of metal substrate and insulating barrier along the projection of the ora terminalis setting of through hole, so can improve cementability and reduce insulating barrier peeling off from metal substrate.
The tin ball 30 on surface is so that can be installed in external circuit particularly on the mainboard.
Description of the process according to embodiment of the invention package stack is as follows.
At first make a plurality of FBGA type encapsulation with wafer-level.A plurality of then through holes are formed on by known techniques near the side presumptive area of the encapsulation made from wafer-level the line of cut of wafer.
After forming through hole, resulting structures is deposited the technology of seed metal layer, the technology that forms light sensitive layer pattern, electroplating technology successively and is removed the technology of photosensitive layer figure and following seed metal layer, makes each through hole have the surface that is electroplate with the copper layer.
Have the surface of copper electroplating layer at each through hole after, will cut into the encapsulation of separation with the encapsulation of wafer-level manufacturing along line of cut.Then, the through hole with plate surface can be exposed to the outside.
At least two encapsulation that will obtain by above-mentioned separating technology are stacked, and allow the through hole vertical arrangement that is formed on the side.
Then, scolding tin is applied in the through hole of the encapsulation of vertical arrangement.Conductive lead wire is fixed in the through hole by using scolding tin, and this scolding tin is linked to reach being electrically connected between the package stack with conductive lead wire by the moistening lip-deep copper layer of through hole that makes subsequently.
Then the tin ball is fixed on the lower surface of orlop encapsulation, finishes package stack of the present invention.
As above-mentioned, have the encapsulation of piling up according to the package stack of the embodiment of the invention, its side at them has the plating through hole and is arranged on conductive lead wire in each through hole of vertically disposed encapsulation, reaches the electrical connection between the package stack.Therefore do not need additional space to carry out being electrically connected between the package stack.In addition, through hole and conductive lead wire can replace traditional PCB and connecting wall.
Therefore, package stack of the present invention can significantly dwindle overall dimensions and thickness compared to known techniques, has therefore realized miniaturization.In addition, omit expensive PCB and connecting wall and reduced manufacturing cost and ratio of defects.
Though present embodiment describes with the package stack of two FBGA types, in fact can use more a plurality of encapsulation to pile up as required.For example, can use four FBGA type encapsulation of piling up each other to constitute package stack, as shown in Figure 4.
As mentioned above, when the package stack made according to the embodiment of the invention, through hole is formed on the side of encapsulation, and conductive lead wire is arranged in the through hole of the encapsulation of piling up, to be electrically connected between stacked package.Therefore, do not need additional space between stacked package, to be electrically connected, and can omit expensive electric connecting part.This has realized miniaturization and has reduced manufacturing cost and ratio of defects.
The above-mentioned most preferred embodiment of the present invention is only as task of explanation, and any personnel that are familiar with this technology will understand, and can carry out various improvement, additional or replace, and the spirit of the present invention and the category that do not break away from claims and limited.Mistake, the reliability of raising circuit substrate.
In addition, circuit substrate as other schemes, side at the face of a side of described metal substrate also has the projection that is provided with along the ora terminalis of described through hole, and the number of the described projection of a side of the face of the opposite side of described metal substrate is more than the number of the described projection of a side of the face of a side of described metal substrate.Like this, a side of the face that the number of projection is many suppresses the expansion of insulating barrier more, so difference appears in the expansion of insulating barrier.As a result, a side effect tensile stress of the face of a side of metal substrate, so, can reduce the warpage of the circuit substrate that compression stress that the distribution density contrast causes brings, can improve the reliability of circuit substrate.
And then the circuit arrangement in the side case of the present invention comprises: the described circuit substrate of such scheme; The circuit element that carries on the described circuit substrate.Circuit element as pyrotoxin rises circuit substrate (circuit arrangement) temperature, so it is big that the tensile stress that the difference of the expansion of the insulating barrier of a side of a side of the face of a side of metal substrate and the face of opposite side causes becomes.Thus, the compression stress that the difference of distribution density causes can reduce, so, can suppress the warpage of circuit substrate, can improve the reliability of circuit arrangement.
In addition, in the said structure, preferred described circuit element be located at described projection opposition side, on described first wiring layer.Like this, near insulating barrier easier expansion of circuit element, so it is big that the tensile stress that the difference of the expansion of the insulating barrier of a side of a side of the face of a side of metal substrate and the face of opposite side causes becomes owing to the heating of circuit element.Thus, the compression stress that the difference of distribution density causes can reduce, so, can suppress the warpage of circuit substrate, can improve the reliability of circuit arrangement.
Description of drawings
Fig. 1 is the profile of the circuit arrangement that is provided with the circuit substrate with metal substrate of expression first execution mode of the present invention;
Fig. 2 is the plane graph of the position of the through hole that is provided with on the metal substrate of expression circuit arrangement shown in Figure 1;
Fig. 3 A～3C is used to illustrate that being provided with of first execution mode of the present invention has the profile of manufacturing process of circuit arrangement of the circuit substrate of metal substrate;
Fig. 4 A～4C is used to illustrate that being provided with of first execution mode of the present invention has the profile of manufacturing process of circuit arrangement of the circuit substrate of metal substrate;
Fig. 5 is used to illustrate that being provided with of first execution mode of the present invention has the profile of manufacturing process of circuit arrangement of the circuit substrate of metal substrate;
Fig. 6 A～6D is the process chart that forms the scheme of through hole on metal substrate;
Fig. 7 is the profile of the circuit arrangement that is provided with the circuit substrate with metal substrate of expression second execution mode of the present invention;
Fig. 8 is another routine profile of the two sides projection of expression metal substrate shown in Figure 7;
Fig. 9 is the plane graph of the position of the through hole that is provided with on the metal substrate of circuit arrangement of expression third embodiment of the invention;
Figure 10 is the summary section of circuit arrangement of position that is equivalent to X-X ' line of Fig. 9;
Figure 11 is the profile of the circuit arrangement that is provided with the circuit substrate with metal substrate of expression the 4th execution mode of the present invention;
Figure 12 A～12C is used to illustrate that being provided with of the 4th execution mode of the present invention has the profile of manufacturing process of circuit arrangement of the circuit substrate of metal substrate;
Figure 13 A～13C is used to illustrate that being provided with of the 4th execution mode of the present invention has the profile of manufacturing process of circuit arrangement of the circuit substrate of metal substrate;
Figure 14 is used to illustrate that being provided with of the 4th execution mode of the present invention has the profile of manufacturing process of circuit arrangement of the circuit substrate of metal substrate;
Figure 15 is the profile of manufacturing process of the circuit arrangement that is provided with the circuit substrate with metal substrate that is used to illustrate the variation of the 4th execution mode of the present invention;
Figure 16 is the profile of the circuit arrangement that is provided with the circuit substrate with metal substrate of expression the 5th execution mode of the present invention;
Figure 17 is the figure that is used to illustrate the schematic configuration of existing general BGA;
Figure 18 is the existing profile that is provided with the circuit arrangement of the circuit substrate with metal substrate of expression;
Figure 19 is that temperature rises and the profile of the circuit arrangement of position deviation occurs in existing structure with metal substrate;
Figure 20 is in existing structure with metal substrate, has the profile of circuit arrangement of the circuit substrate of distortion.
Embodiment
Execution mode with concrete manifestation of the present invention below is described with reference to the accompanying drawings.In addition, all among the figure, same structural element is given identical symbol, suitably omits explanation.In addition, in the specification of the present invention, " on " direction dictates is last for the direction that has circuit element with respect to metal substrate.
(first execution mode)
Fig. 1 is the profile of the circuit arrangement that is provided with the circuit substrate with metal substrate of expression first execution mode of the present invention.
In the circuit arrangement 50 of first execution mode of the present invention, be provided with metal substrate 1 as core components in circuit substrate 10 inside with a plurality of through holes 2.Metal substrate 1 has projection 1a at an end of the upper face side of through hole 2, and an end of side has bight (bevelling) 1b of band fillet below through hole 2.Form Wiring pattern layer 4,6 in the two sides of this metal substrate 1 side respectively via insulating barrier 3,5.In addition, for each Wiring pattern layer is electrically connected, connects metal substrates 1 and, be able to and each wiring layer conducting the conductor layer 8 that Wiring pattern layer 4 is connected with Wiring pattern layer 6 and form via through hole 2.And then, directly be connected with LSI chip 20 at the upper face side of circuit substrate 10 via solder ball 21.In addition, insulating barrier 3 is that " first insulating barrier " of the present invention, insulating barrier 5 are that " second insulating barrier " of the present invention, Wiring pattern layer 4 are that " first wiring layer " of the present invention and Wiring pattern layer 6 are examples of " second wiring layer " of the present invention.
Particularly, in the circuit arrangement 50 of first execution mode of the present invention, has the metal substrate 1 of the thickness of about 50 μ m～about 1mm (for example about 100 μ m) as the core components use of circuit substrate 10 inside.For example, the lower metal layer of this metal substrate 1 by constituting with copper, be formed on the intermediate metal layer that the Fe-Ni class alloy (so-called iron-nickel alloy) on the lower metal layer constitutes and be formed on the clad metal that the upper metal layers that is made of copper on the intermediate metal layer is laminated and constitute.In addition, metal substrate 1 also can be the copper individual layer.
Fig. 2 is the plane graph of the position of the through hole that is provided with on the metal substrate of expression circuit arrangement shown in Figure 1.In addition, Fig. 1 is equivalent to the profile of the X-X ' line among Fig. 2.By side below metal substrate 1 carry out laser radiation or boring processing and on metal substrate 1 assigned position corresponding with honeycomb arrangement (in the arrangement of orthohexagonal each summit and center configuration through hole thereof) form through hole 2 (the diameter R: about 300 μ m) of perforation metal substrate 1.At this, the pitch S between through hole is configured to S=4R, forms ten place's through holes 2 on metal substrate 1.When forming through hole 2 like this on metal substrate 1, the upper face side of metal substrate 1 forms projection 1a (about 25 μ m) along the ora terminalis of through hole 2, and side forms bevelling 1b along the ora terminalis of through hole 2 below.In addition, this projection 1a is along the ora terminalis setting of the through hole 2 of metal substrate 1, and the leading section of projection 1a can not be uniform height, for example can be comb shape or waveform.The shape of each projection and highly can be inequality.In addition, projection 1a need not be provided with all-in-one-piece (continuous) projection along the ora terminalis of through hole 2, and for example can be independently a plurality of projections be provided with discontinuously along the ora terminalis of through hole 2.
The upper face side of metal substrate 1 and following side form about 60 μ m～about 160 μ m (for example about 75 μ m) thickness be the insulating barrier 3,5 of principal component with epoxy resin.At this moment, the through hole 2 of metal substrate 1 is fully by insulating barrier 3,5 embeddings.In addition, epoxy resin is that the insulating barrier 3,5 of principal component also can add and has about about 2 μ m～additive of diameter about 10 μ m.This additive is aluminium oxide (Al 2O 3), silica (SiO 2), aluminium nitride (AlN), silicon nitride (SiN) and boron nitride (BN) etc.In addition, the weight filling rate of additive is about 60%～about 80%.
Form the Wiring pattern layer 4,6 that constitutes by copper of thickness on the insulating barrier 3,5 respectively with about 35 μ m, by conductor layer 8 (the about 150 μ m of diameter) with each wiring layer conducting.And then on Wiring pattern layer 4, connect LSI chip 20 as semiconductor chip via solder ball 21.In addition, LSI chip 20 is examples of " circuit element " of the present invention.
Fig. 3～5th is used to illustrate that being provided with of first execution mode of the present invention has the profile of manufacturing process of circuit arrangement of the circuit substrate of metal substrate.
At first, as shown in Figure 3A, preparation has the metal substrate 1 of the thickness of about 50 μ m～about 1mm (for example about 100 μ m).For example the lower metal layer of this metal substrate 1 by being made of copper, the intermediate metal layer that is made of Fe-Ni class alloy (so-called iron-nickel alloy) that is formed on the lower metal layer constitute with the stacked clad metal that reaches of upper metal layers that is made of copper on being formed on intermediate metal layer.In addition, also copper individual layer of metal substrate 1.
Shown in Fig. 3 B, carry out laser radiation or boring processing by side below metal substrate 1, thereby form through hole 2 (the diameter R: about 300 μ m) that connects metal substrate 1 at the assigned position of corresponding honeycomb arrangement.The operation back that is processed to form through hole 2 by boring is narrated.In addition, the configuration of through hole 2 such as front is shown in Figure 2.Thus, the ora terminalis along the upper face side of the through hole 2 of metal substrate 1 forms projection 1a (about 25 μ m).The ora terminalis of side forms bevelling 1b below through hole 2.In addition, this projection 1a is along the ora terminalis setting of the through hole 2 of metal substrate 1, but the front-end edge of projection 1a can not be uniform height, for example is, also can be comb shape or waveform.In addition, can be inequality on the shape of each projection or the height.In addition, projection 1a need not be provided with all-in-one-piece (continuous) projection along the ora terminalis of through hole 2, and for example can be independently a plurality of projections be provided with discontinuously along the ora terminalis of through hole 2.
Shown in Fig. 3 C, under the environment of vacuum or decompression, the insulating barrier 3 of band Copper Foil 4a from the upper face side hot pressing of metal substrate 1, the insulating barrier 5 of band Copper Foil 6a in side hot pressing below metal substrate 1.At this, the thickness of insulating barrier 3,5 for example forms about 75 μ m, the thickness of Copper Foil 4a, 6a for example forms about 10 μ m～15 μ m about.
By pressing the insulating barrier with Copper Foil, shown in Fig. 4 A, the through hole 2 of metal substrate 1 is by insulating barrier 3,5 complete embeddings.
Shown in 4B, the insulating barriers in the through hole 2 of imbedding metal substrate 1 are carried out laser radiation or boring processing, thereby be formed for connecting this insulating barrier in the position of corresponding through hole 2 and the reach through hole 7 (the about 150 μ m of diameter) that connects the Copper Foil on two sides.At this, (ten places) is provided with reach through hole 7 to whole through hole 2.
Shown in Fig. 4 C, with electroless plating apply method on Copper Foil 4a, on the inner face of reach through hole 7 and Copper Foil 6a above with the thickness plating coating copper of about 0.5 μ m.Then, with electrolysis plating method on Copper Foil 4a, on the inner face of reach through hole 7 and Copper Foil 6a above carry out plating.In addition, in the present embodiment, by in plating solution, add inhibitor and promoter make inhibitor be adsorbed on Copper Foil 4a, above the 6a on, and promoter is adsorbed on the inner face of reach through hole 7.Thus, because the copper-plated thickness increase on the inner face of reach through hole 7, so can in reach through hole 7, imbed copper.As a result, on insulating barrier 3,5, form the wiring layer 4b, the 6b that constitute by copper of thickness respectively, and in reach through hole 7, imbed the conductor layer 8 that constitutes by copper with about 35 μ m.
Then, as shown in Figure 5, wiring layer 4b, 6b are carried out composition respectively by photoetching technique and etching technique.Thus, form Wiring pattern layer 4 and Wiring pattern layer 6.Thus, form the circuit substrate 10 that is provided with metal substrate 1 with projection 1a.
At last, as shown in Figure 1, LSI chip 20 is electrically connected lift-launch on the Wiring pattern layer 4 of circuit substrate 10 via solder ball 21, fixing by resin bed (not shown).As a result, form the circuit arrangement 50 that is provided with circuit substrate 10 with metal substrate 1.
In addition, about Fig. 2, carry out laser radiation or boring processing by side below metal substrate 1 on metal substrate 1, form the through hole 2 that connects metal substrate 1, this talks about in the above, but the formation method of through hole 2 is not limited thereto.For example also can on metal substrate 1, form through hole 2 with following method.
At first, as shown in Figure 6A, side is provided with control board 100 below the metal substrate 1 of drilling tool inserting surface opposition side.
Secondly, shown in Fig. 6 B, with drill bit 110 beginning cutting metal substrates 1.At this moment, the insertion because of drill bit 110 makes the part of metal substrate 1 become initial stage jut 112.
Secondly, shown in Fig. 6 C, make drill bit 110 connect metal substrate 1 and formation through hole 2.
At last, shown in Fig. 6 D, when metal substrate 1 is extracted drill bit 110, form projection 1a along the ora terminalis of through hole 2 at the upper face side of metal substrate 1.On the other hand, it is askew that the drill bit 110 that pulls up draws metal substrate 1, forms bevelling 1b along the ora terminalis of the through hole 2 of drilling tool inserting surface opposition side.Wherein, bevelling 1b and control board 100 join, so the pouring volume of bevelling 1b is littler than the volume of projection 1a.That is, compare, increased the volume of metal substrate 1 with the situation that the simple through hole 2 that does not have projection 1a and bevelling 1b is set on the metal substrate 1.
Circuit arrangement according to first execution mode of above explanation can obtain following effect.
(1), along the projection 1a insulating barrier 3 that jam-packed expands by anchoring effect when circuit substrate 10 temperature rise that the ora terminalis of the through hole 2 that is provided with conductor layer 8 is provided with, can reduce the pattern deviation that metal substrate 1 and the thermal expansion rate variance of 3 of insulating barriers cause Wiring pattern layer 4 (distortion of the conductor layer 8 of the Wiring pattern layer 4,6 about perhaps being connected: the position deviation of the connecting portion of the position of the interior conductor layer 8 of the through hole 2 of metal substrate 1 and Wiring pattern layer 4) particularly.In addition,, can reduce insulating barrier 3 and peel off owing to the contact area that has increased metal substrate 1 and insulating barrier 3 has improved cementability along the projection 1a of ora terminalis setting of the through hole 2 that is configured to honeycomb arrangement from metal substrate 1.Consequently, the circuit arrangement reliability reduces in the time of can suppressing the temperature rising.
(2), by with as the identical side of the LSI chip 20 of pyrotoxin projection 1a is set selectively, and can more effectively suppress the expansion of insulating barrier 3, so can improve adhesive property more significantly.In addition, because projection 1a edge is configured to the ora terminalis setting of the through hole 2 of honeycomb arrangement, so projection 1a evenly configuration in circuit arrangement, cementability is evenly improved in the circuit arrangement.In addition, by honeycomb arrangement, with respect to a plurality of through holes 2 are arranged in the situation of square lattice with same pitch, can be with arranged in high density, so can be provided with morely by the contact portion of projection 1a, strengthen and connect airtight the property improvement effect.These result, the reliability of the circuit arrangement in the time of can further suppressing the temperature rising effectively reduces.
(3), the Wiring pattern layer 4 of connection LSI chip 20 and the interval (distance) between the metal substrate 1 shorten relatively because of the projection 1a part of metal substrate 1, projection 1a becomes the heat that will produce from LSI chip 20 heat dissipation path to metal substrate 1 heat radiation, do not compare with on metal substrate 1, there being the situation of projection, improved the heat dissipation characteristics of circuit arrangement 50 (circuit substrate 10).The reliability of the circuit arrangement in the time of as a result, can improving the temperature rising.
(4), by projection 1a is set on metal substrate 1, increase the volume of metal substrate 1, corresponding with the increase of the volume of metal substrate 1, the thermal capacity of metal substrate 1 increases.The volume of metal substrate 1 increases and can form volume recruitment that projection 1a brings along an end of through hole 2 and surpass the volume reduction that the bevelling 1b that forms along the other end of through hole 2 brings and be achieved by making.
(second execution mode)
Fig. 7 is the profile of the circuit arrangement that is provided with the circuit substrate with metal substrate of expression second execution mode of the present invention.In first execution mode, an end of the through hole 2 of the metal substrate 1 of a side of lift-launch LSI chip 20 is provided with projection 1a.With respect to this, in the present embodiment, not only, all form projection 1a at the two ends of through hole 2 in a side of carrying LSI chip 20.In addition, the circuit arrangement of second execution mode has the structure identical with first execution mode.
In addition, the formation of the projection 1a that exists of the two ends of the through hole 2 of metal substrate 1 by do not use common boring add that use man-hour, clip machined object and machined object and abandoned substrate hole processing and realization easily fully by opening simultaneously.
According to this second execution mode, can access following effect.
(5), owing to be provided with projection 1a at the two ends of the through hole 2 of metal substrate 1, so side below metal substrate 1, the insulating barrier 5 that the projection 1a that is provided with on the ora terminalis of the through hole 2 of metal substrate 1 also expands because of the anchoring effect jam-packed when the temperature of circuit arrangement 50A (circuit substrate 10) rises.Thus, can reduce the pattern deviation that metal substrate 1 and the thermal expansion rate variance of 5 of insulating barriers cause Wiring pattern layer 6 (perhaps be connected the distortion of the conductor layer 8 of Wiring pattern layer 4,6 up and down: the position deviation of the connecting portion of the position of the conductor layer 8 in the through hole 2 of metal substrate 1 and Wiring pattern layer 6) particularly.In addition,, can reduce insulating barrier 5 and peel off owing to the contact area that has increased metal substrate 1 and insulating barrier 5 has improved cementability along the projection 1a of ora terminalis setting of the through hole 2 that is configured to honeycomb arrangement from metal substrate 1.Consequently, owing to can control position deviation and the stripping that thermal expansion brings, circuit arrangement 50A (circuit arrangement 10) reliability is reduced so can further suppress the temperature rising in the two sides of circuit substrate 10 side.
(variation of second execution mode)
As the variation of second execution mode, Fig. 8 represents another example of the two sides projection of metal substrate shown in Figure 7.
In second execution mode, projection 1a is set on the two ends of each through hole 2, set the structure of projection 1a on the two sides of realization metal substrate 1.With respect to this, in the variation of second execution mode, only the one-sided ora terminalis at through hole 2 is provided with projection 1a (opposition side is bevelling 1b), and the through hole 2 that projection 1a is positioned at the through hole 2 of upper face side of metal substrate 1 and the following side that projection 1a is positioned at metal substrate 1 mixes and exists.Remove this, the circuit arrangement of the variation of second execution mode has the structure identical with second execution mode.
The circuit arrangement of the variation of this second execution mode also can be enjoyed the effect of above-mentioned (5) of explaining in second execution mode of front.
(the 3rd execution mode)
Fig. 9 is the plane graph of the position of the through hole that is provided with on the metal substrate of circuit arrangement of expression third embodiment of the invention.Figure 10 is the summary section of circuit arrangement of position that is equivalent to X-X ' line of Fig. 9.The places different with first execution mode are: through hole 2 (the diameter R: about 300 μ m) form with honeycomb arrangement high density (pitch S is configured to S=2R between through hole) that connects metal substrate 1; Comprise through hole 2a that conductor layer 8 is set and the through hole that conductor layer 8 is not set (pseudo-through hole) 2b in these a plurality of through holes.In addition, the circuit arrangement of the 3rd execution mode is identical with first execution mode of front.
Particularly, irradiating laser or boring processing selectively in the operation shown in Fig. 4 B of front, thus desirable position forms reach through hole 7 (diameter 150 μ m) in through hole.Afterwards, in the operation shown in Fig. 4 C, implement the copper plating and handle, corresponding position is imbedded and is formed conductor layer 8.Thus, in circuit substrate, form through hole (pseudo-through hole) 2b that is provided with the through hole 2a of conductor layer 8 and is not provided with conductor layer 8 selectively.In addition, in the 3rd execution mode, through hole (pseudo-through hole) 2b that conductor layer 8 is not set is arranged more than the through hole 2a that conductor layer 8 is set, and through hole (pseudo-through hole) the 2b encirclement that conductor layer 8 is not set is provided with around the through hole 2a of conductor layer 8.
According to the circuit arrangement of the 3rd execution mode, the effect except above-mentioned (1)～(4) shown in first execution mode of front can also obtain following effect.
(6), contain the such honeycomb arrangement of through hole 2b that conductor layer 8 is not set by through hole formation with metal substrate 1, thereby compare than the structure that only constitutes honeycomb arrangement by the through hole 2a that is provided with conductor layer 8, easy on the design arrangement, so can realize the cost degradation of circuit arrangement.
(7), contain the such honeycomb arrangement of through hole 2b that conductor layer 8 is not set by through hole formation with metal substrate 1, thereby compare than the structure that only constitutes honeycomb arrangement by the through hole 2a that is provided with conductor layer 8, can through hole be set high density in the metal substrate 1, so can strengthen the effect of above-mentioned (2).
(8), the metal substrate 1 with through hole that honeycomb arrangement forms is provided with reach through hole 7 in desirable position, form conductor layer 8, thereby make the layout design generalization that on metal substrate 1, forms through hole, can adopt said metal substrates 1 to the circuit arrangement of a plurality of distinct device kinds, so can realize the cost degradation of each circuit arrangement.
(9), the through hole 2b that will not be provided with conductor layer 8 sees from the plane to surround and the through hole 2a of conductor layer 8 is set and disposes, so near the expansion of the insulating barrier 3 the through hole 2a is by the further jam-packed of projection that is provided with along the ora terminalis that is disposed at its through hole 2b on every side, so can further reduce the pattern deviation of the Wiring pattern layer 4 of through hole 2a.
(the 4th execution mode)
Figure 11 is the profile of the circuit arrangement that is provided with the circuit substrate with metal substrate of expression the 4th execution mode of the present invention.
The circuit arrangement 50 of the 4th execution mode of the present invention is provided with the metal substrate 1 with through hole 2 as core components in circuit substrate 10 inside.The ora terminalis of metal substrate 1 side below through hole 2 has projection 1a, has bevelling 1b at the ora terminalis of the upper face side of through hole 2.The two sides side of this metal substrate 1 forms Wiring pattern layer 4,6 respectively via insulating barrier 3,5.In addition,, form via through hole 2 and connect metal substrate 1, connect the conductor layer 8 of Wiring pattern layer 4 and Wiring pattern layer 6, be able to and each Wiring pattern layer conducting for each Wiring pattern layer is electrically connected.In addition, the upper face side at circuit substrate 10 directly connects semiconductor chip 20 via solder ball 21.
Particularly, in the circuit arrangement 50 in the 4th execution mode of the present invention, has the metal substrate 1 of the thickness of about 50 μ m～about 1mm (for example about 100 μ m) as the core components use of circuit substrate 10 inside.For example, the lower metal layer of this metal substrate 1 by constituting by copper, be formed on the intermediate metal layer that the Fe-Ni class alloy (so-called iron-nickel alloy) on the lower metal layer constitutes and be formed on the clad metal that the upper metal layers that is made of copper on the intermediate metal layer is laminated and constitute.In addition, metal substrate 1 also can be the copper individual layer.
By metal substrate 1 being carried out laser radiation or boring processing, the position of regulation forms the through hole 2 (the about 300 μ m of diameter) that connects metal substrate 1 on metal substrate 1.Thus, the ora terminalis of side through hole 2 forms projection 1a (about 25 μ m) below metal substrate 1, and the ora terminalis of side through hole 2 forms bevelling 1b in the above.In addition, for example every 100mm of the through hole 2 of metal substrate 1 2Be provided with more than 10 places, thereby can effectively suppress circuit substrate described later and use the reduction of reliability of the circuit arrangement of this circuit substrate.
The upper face side of metal substrate 1 and below side to form what have about 60 μ m～about 160 μ m (for example about 75 μ m thickness) be the insulating barrier 3,5 of principal component with epoxy resin.At this moment, the through hole 2 of metal substrate 1 is by insulating barrier 3,5 complete embeddings.In addition, be to add filler in the insulating barrier 3,5 of principal component with epoxy resin with the diameter about about 2 μ m～10 μ m.As this filler aluminium oxide (Al is arranged 2O 3), silica (SiO 2), aluminium nitride (AlN), silicon nitride (Si 3N 4) and boron nitride (BN) etc.In addition, the weight filling rate of additive is about 60%～about 80%.
Form the Wiring pattern layer 4,6 that constitutes by copper of thickness on the insulating barrier 3,5 respectively with about 35 μ m, by conductor layer 8 (the about 150 μ m of diameter) with each wiring layer conducting.At this moment, below the distribution density of Wiring pattern layer 6 of side be about 30%, the distribution density of the Wiring pattern layer 4 of upper face side is about 50%.And then on Wiring pattern layer 4, connect the LSI chip as semiconductor chip 20 via solder ball 21.In addition, distribution density is meant that distribution accounts for the percentage of regulation area.
Figure 12～14th is used to illustrate the profile of manufacturing process of the circuit arrangement that is provided with the circuit substrate with metal substrate of the 4th execution mode of the present invention shown in Figure 11.
At first, shown in Figure 12 A, prepare to have about 50 μ m～approximately the metal substrate 1 of the thickness of 1mm (for example about 100 μ m) is as core components.For example the lower metal layer of this metal substrate 1 by constituting by copper, be formed on the intermediate metal layer that constitutes by Fe-Ni class alloy (so-called iron-nickel alloy) on the lower metal layer and the stacked clad metal that constitutes of upper metal layers that is made of copper that is formed on the intermediate metal layer constituting.In addition, also copper individual layer of metal substrate 1.
Shown in Figure 12 B, by metal substrate 1 being carried out laser radiation or boring processing, thereby form the through hole 2 (the about 300 μ m of diameter) that connects metal substrate 1 at assigned position.Thus, the ora terminalis of side forms projection 1a (about 25 μ m) below the through hole 2 of metal substrate 1.Ora terminalis along the upper face side of through hole 2 forms bevelling 1b.In addition, this projection 1a is along the ora terminalis setting of the through hole 2 of metal substrate 1, but the front-end edge of projection 1a can not be uniform height, for example is, also can be comb shape or waveform.In addition, the shape of each projection with highly also can be different.In addition, the projection 1a of metal substrate 1 (through hole) 2 for example every 100mm 2Be provided with more than 10 places, thereby can reduce the stress load that the difference of distribution density of the layer of Wiring pattern causes, the high circuit substrate of reliability is provided and uses the circuit arrangement of this circuit substrate.In addition, preferred through hole 2 is provided with in the face of metal substrate 1 equably.Shown in Figure 12 C, under the environment of vacuum or decompression, the insulating barrier 3 of band Copper Foil 4a from the upper face side hot pressing of metal substrate 1, the insulating barrier 5 of band Copper Foil 6a in side hot pressing below metal substrate 1.At this, the thickness of insulating barrier 3,5 for example forms about 75 μ m, the thickness of Copper Foil 4a, 6a for example forms about 10 μ m～15 μ m about.
As shown in FIG. 13A, by pressing insulating barrier with Copper Foil, and with the through hole 2 of metal substrate 1 by insulating barrier 3,5 complete embeddings.
Shown in 13B, metal substrate 1 is carried out laser radiation or boring processing, thereby be formed for connecting the reach through hole 7 (the about 150 μ m of diameter) of two sides Copper Foil in the position of corresponding through hole 2.
Secondly, shown in Figure 13 C, with electroless plating apply method on Copper Foil 4a, on the inner face of reach through hole 7 and Copper Foil 6a below with the thickness plating coating copper of about 0.5 μ m.Then, with electrolysis plating method on Copper Foil 4a, on the inner face of reach through hole 7 and Copper Foil 6a below carry out plating.
In addition, in four embodiment of the invention, by in plating solution, add inhibitor and promoter make inhibitor be adsorbed on Copper Foil 4a, above the 6a on, and promoter is adsorbed on the inner face of reach through hole 7.Thus, because the copper-plated thickness increase on the inner face of reach through hole 7, so can in reach through hole 7, imbed copper.As a result, on insulating barrier 3,5, form the wiring layer 4,6 that constitutes by copper of thickness respectively, and in reach through hole 7, imbed the conductor layer 8 that constitutes by copper with about 35 μ m.
Then, as shown in figure 14, wiring layer 4,6 is carried out composition respectively by common photoetching technique and etching technique.Thus, form Wiring pattern layer 4 and Wiring pattern layer 6.At this moment, the distribution density that has on the face of projection 1a is the distribution density lower than opposing face, and the difference of distribution density is about more than 10%.Thus, form the circuit substrate 10 that is provided with metal substrate 1 with projection 1a.
At last, as shown in figure 11, LSI chip 20 is electrically connected lift-launch on the Wiring pattern layer 4 of circuit substrate 10 via solder ball 21, fixing by resin bed (not shown).As a result, form the circuit arrangement 50 that is provided with circuit substrate 10 with metal substrate 1.
In the 4th execution mode, as mentioned above, the ora terminalis of the through hole 2 of metal substrate 1 has projection 1a.Difference tensile stress (power that the insulating barrier desire will expand) because of coefficient of thermal expansion between metal substrate 1 and insulating barrier 3,5 acts on, but tensile stress between metal substrate 1 and the insulating barrier 3 and the tensile stress between metal substrate 1 and 5 can be balanced usually, and roughly obtain balance.But, about the expansion of insulating barrier 5, because the restriction of the anchoring effect that the projection 1a of the insulating barrier 5 that is subjected to nipping has, so be suppressed to such an extent that reduce with respect to the expansion of insulating barrier 3.As a result, deviation appears in the equilibrium of the tensile stress that each insulating barrier causes, the tensile stress of the residual quantity of insulating barrier 3 and insulating barrier 5 is to circuit substrate 10 effects.The compression stress (acting on the compression stress of wiring layer 4 sides) that the tensile stress of this residual quantity causes the difference of the distribution density of the Wiring pattern layer of being located on the circuit substrate 10 reduces, so can prevent the warpage of circuit substrate 10, and can suppress on the circuit substrate 10 the generation of distribution migration and peeling off of insulating barrier that the compression stress of effect causes.And then, can prevent to carry wrong generation when circuit element 20 from installing, and improve the reliability of circuit substrate 10 with metal substrate 1.
In addition and since form by the projection 1a along the ora terminalis setting of through hole 2 make metal substrate 1 below the structure that is enhanced of side, so the warpage of metal substrate 1 and the patience of distortion (crooked patience) are increased.Therefore, stress load (acting on the compression stress of wiring layer 4 sides) acts under the situation on the circuit substrate 10, suppresses the warpage and the distortion of circuit substrate 10.
In addition, in the 4th execution mode, has circuit element 20 on the circuit substrate 10.The circuit element 20 that becomes pyrotoxin rises the temperature of circuit substrate 10 (circuit arrangement 50), so insulating barrier 3 and insulating barrier 5 expand easily.But the expansion of insulating barrier 5 is subjected to the restriction of projection 1a, so the difference of the swell increment of insulating barrier 3 and insulating barrier 5 enlarges, it is big that the tensile stress that insulating barrier causes further becomes.Thus, the compression stress that the difference of distribution density causes reduces, so can suppress the warpage and the distortion of circuit substrate 10, can improve the reliability of circuit arrangement 50.
Further, if circuit substrate 20 is configured to cover through hole 2, then the difference of the swell increment of insulating barrier 3 and insulating barrier 5 increases, and it is big that the tensile stress that insulating barrier causes further becomes, and is effective so suppress the warpage and the distortion of circuit substrate 10.
And then, in the 4th execution mode, circuit element 20 be located at projection 1a opposition side, on the wiring layer 4.The insulating barrier 3 that is close to circuit element 20 is more prone to expand because of the heating of circuit element 20, so that the tensile stress that the difference that expands because of insulating barrier produces further becomes is big.Thus, the compression stress that the distribution density contrast causes further reduces, thus the warpage of circuit substrate 10 and the distortion further suppressed, thereby the circuit arrangement with high reliability can be provided.
(variation of the 4th execution mode)
Figure 15 is the profile of manufacturing process of the circuit arrangement that is provided with the circuit substrate with metal substrate that is used to illustrate the variation of the 4th execution mode of the present invention.In the variation of the 4th execution mode, the projection 1a of the ora terminalis setting of the through hole 2 of metal substrate 1 is provided with on whole through holes of metal substrate 1, forms but mixing is not provided with the through hole 2a (end 1c) of projection.In addition, identical with the 4th execution mode.
In the variation of the 4th execution mode, also the through hole ora terminalis at metal substrate 1 is provided with projection 1a, so, identical with the 4th execution mode, not only reduce the compression stress that the distribution density because of the Wiring pattern layer causes, can also suppress the warpage and the distortion of the metal substrate 1 that compression stress brings, so the circuit substrate 10 of the metal substrate 1 that is provided with high reliability can be provided and use the circuit arrangement 50A of this circuit substrate.
(the 5th execution mode)
Figure 16 is the profile of the circuit arrangement that is provided with the circuit substrate with metal substrate of expression the 5th execution mode of the present invention.The places different with the 4th execution mode are: the projection 1a of the through hole 2 of metal substrate 1 (opposition side bevelling 1b) is not the following side that only is formed on the through hole 2 of metal substrate 1, but side and following side form projection 1a respectively in the above.In addition, in the drawings, upper face side and following side are represented to form one example, but in fact, below the number of projection 1a of side more than the number of the projection 1a of upper face side.In addition, identical with the 4th execution mode.
In the 5th execution mode, the number of the projection 1a that the following side of metal substrate 1 is provided with is more than the number of the projection 1a that the upper face side of metal substrate 1 is provided with, thus than the expansion of the insulating barrier 3 of upper face side, below the expansion of insulating barrier 5 of side limited by projection 1a.Therefore, identical with the 4th execution mode, reduce the compression stress that the distribution density of Wiring pattern layer causes, can improve the reliability of circuit arrangement 50B.
In addition, embodiments of the present invention all only are illustrations, rather than the qualification to inventing.The present invention can do various distortion and change.
For example, in the above-mentioned execution mode, the present invention is applicable to the circuit arrangement that the LSI chip is installed, but the invention is not restricted to this, also can be applicable to the circuit arrangement that LSI chip circuit element in addition has been installed.For example, passive component such as electric capacity, resistance.
And then, in the above-mentioned execution mode, with the circuit substrate of the two-layer distribution structure that on the two sides of metal substrate, forms insulating barrier and wiring layer in turn with use the circuit arrangement of this circuit substrate to be applicable to that the present invention is illustrated as example, but the present invention is not limited to this, also applicable to the circuit substrate of four layers of distribution structure that further form insulating barrier and wiring layer on the wiring layer on two sides in turn and the circuit arrangement that uses this circuit substrate.In addition, also applicable to the circuit substrate of the sandwich construction more than six layers and the circuit arrangement of this circuit substrate of use.
In the above-described 3rd embodiment, only illustration only be located at the example that carries LSI chip 20 1 sides along the projection 1a of the ora terminalis setting of the through hole 2 of metal substrate 1, but also can form projection 1a in the both sides of the through hole 2 of metal substrate 1.At this moment, can benefit from the effect of above-mentioned (5) shown in second execution mode.
In above-mentioned first and second execution modes, illustration whole through holes 2 of metal substrate 1 are provided with the example of conductor layer 8, but also can not be arranged on whole through holes 2 of conductor layer 8 and only the position that is necessary is provided with.At this moment, can benefit from above-mentioned (6) shown in the 3rd execution mode and the effect of (8).
In the above-described embodiment, illustration metal substrate 1 is provided with the example of through hole 2 with honeycomb arrangement, but the present invention is not limited to this, also can arrange with square lattice a plurality of through holes 2 are set.In addition, also a plurality of through holes 2 can be set at random if design is upward out of question.
In the variation of above-mentioned second execution mode, illustration side and the following side single face side setting that is respectively formed at metal substrate 1 in the above have the example of the through hole 2 of projection 1a (opposition side bevelling 1b), but such projection 1a is under the situation that the upper face side of metal substrate 1 more than 1 is provided with than following side, owing to exist in a large number, can play the effect of improving connecting airtight property more effectively with LSI chip 20 mutually same lateral process 1a as pyrotoxin.
In addition, in the above-mentioned execution mode, the example that uses metal substrate has been described, but so long as can be processed to form projection, also can has been resin substrate by laser radiation or boring.

Claims (15)

1. circuit arrangement, it comprises: the metal substrate with a plurality of through holes; Be arranged on first wiring layer on the face of a side of described metal substrate via first insulating barrier; Be arranged on second wiring layer on the face of opposite side of described metal substrate via second insulating barrier; Conductor layer, it connects described metal substrate via at least a portion through hole in described a plurality of through holes, and described first wiring layer is connected with second wiring layer; The circuit element that is connected with described first wiring layer on the face of a side of described metal substrate, wherein, the ora terminalis of a certain at least side that the surperficial upper edge of described metal substrate is provided with the through hole of described conductor layer is provided with projection.
2. circuit arrangement as claimed in claim 1, the described through hole that is provided with described conductor layer in the face of described metal substrate with the honeycomb arrangement setting.
3. circuit arrangement as claimed in claim 2, wherein, described projection is provided with manyly in the face side of the face of a side of described metal substrate than the face side of the face of opposite side.
4. circuit arrangement as claimed in claim 2, wherein, described projection is arranged on the face side of face of a side of described metal substrate selectively.
5. circuit arrangement as claimed in claim 4, wherein, the through hole that described conductor layer is not set in described a plurality of through holes sees that from the plane surrounding the through hole that described conductor layer is set disposes.
6. circuit arrangement as claimed in claim 1, wherein, described projection is provided with manyly in the face side of the face of a side of described metal substrate than the face side of the face of opposite side.
7. circuit arrangement as claimed in claim 6, wherein, described projection is arranged on the face side of face of a side of described metal substrate selectively.
8. circuit arrangement as claimed in claim 7, wherein, the through hole that described conductor layer is not set in described a plurality of through holes sees that from the plane surrounding the through hole that described conductor layer is set disposes.
9. circuit arrangement as claimed in claim 1, wherein, under the situation that the ora terminalis of the described through hole of the opposition side of the face of described formation projection is poured into, the volume recruitment that described projection is brought is more than pouring the volume reduction of bringing into.
10. circuit substrate, it comprises: the metal substrate with a plurality of through holes; Be arranged on first wiring layer on the face of a side of described metal substrate via first insulating barrier; Second wiring layer that be arranged on the face of opposite side of described metal substrate via second insulating barrier, distribution density is littler than described first wiring layer; Connect described metal substrate via described through hole, the conductor layer that described first wiring layer is connected with second wiring layer; Along the ora terminalis of described through hole projection is set in a side of the face of the opposite side of described metal substrate.
11. circuit substrate as claimed in claim 10, wherein, side at the face of a side of described metal substrate also has the projection that is provided with along the ora terminalis of described through hole, and the number of the described projection of a side of the face of the opposite side of described metal substrate is more than the number of the described projection of a side of the face of a side of described metal substrate.
12. a circuit arrangement, it comprises: the described circuit substrate of claim 10; The circuit element that carries on the described circuit substrate.
13. circuit arrangement as claimed in claim 12, wherein, described circuit element be located at described projection opposition side, on described first wiring layer.
14. a circuit arrangement, it comprises: the described circuit substrate of claim 11; The circuit element that carries on the described circuit substrate.
15. circuit arrangement as claimed in claim 14, wherein, described circuit element be located at described projection opposition side, on described first wiring layer.
CNB2006101100267A 2005-07-29 2006-07-28 Circuit board and circuit apparatus using the same Expired - Fee Related CN100433321C (en)

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CN104333981A (en) * 2014-10-16 2015-02-04 惠州智科实业有限公司 Manufacturing method of LED heat radiating substrate and LED module with substrate
CN107492537A (en) * 2016-06-09 2017-12-19 日月光半导体制造股份有限公司 Intermediary layer, semiconductor package and semiconductor technology
US10388598B2 (en) 2016-06-09 2019-08-20 Advanced Semiconductor Engineering, Inc. Interposer, semiconductor package structure, and semiconductor process
CN107960004A (en) * 2016-10-14 2018-04-24 鹏鼎控股(深圳)股份有限公司 Scalable circuit board and preparation method thereof
CN108347838A (en) * 2018-02-07 2018-07-31 维沃移动通信有限公司 A kind of production method of circuit board, circuit board and mobile terminal
CN108430172A (en) * 2018-02-28 2018-08-21 维沃移动通信有限公司 A kind of preparation method and circuit board of circuit board
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