CN1909200B - 具有改善的开态电阻和击穿电压性能的半导体结构 - Google Patents
具有改善的开态电阻和击穿电压性能的半导体结构 Download PDFInfo
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Abstract
在一个实施方案中,横向FET单元被形成在半导体材料本体中。此横向FET单元包括形成在漏接触与本体区之间的漂移区中的超结结构。此超结结构包括多个分隔开的填充的沟槽,这些填充的沟槽具有环绕沟槽的相反或交替的导电类型的掺杂区。
Description
技术领域
本发明一般涉及到半导体器件,更确切地说是涉及到功率开关结构及其制造方法。
背景技术
诸如横向金属氧化物半导体场效应晶体管(MOSFET)之类的MOSFET,常常被用于诸如开关器件通信***或AC-DC电压转换器中的脱机开关调节器之类的高压(亦即高于200V)应用中。在典型的高压横向MOSFET中,源和漏区被中间区即漂移区分隔开。栅结构被安置成临近器件的沟道区。在开通状态下,电压被施加到栅,以便在源和漏区之间形成导电的沟道区,使电流能够流过器件。在关断状态下,施加到栅的电压足够低,致使不形成导电的沟道区,电流因而不流动。在此关断状态期间,器件必须承受源和漏区之间的高压。
开态电阻(RON)是MOSFET开关器件特性的一个重要指标。开态电阻是当开关闭合且信号通过时存在于MOSFET开关的输入插脚与输出插脚之间的欧姆电阻。开态电阻与信号通过器件时会引起多少信号衰减有关。另一个重要的特性指标是开态比电阻(RSP),此RSP是RON与表面积的乘积,即RON×面积。较小的RON×面积使设计者能够使用较小的高压横向MOSFET来满足给定应用的开态电阻要求,这降低了功率集成电路的面积和成本。
常规高压横向MOSFET的一个问题是,倾向于使击穿电压(VBD)最大化的技术和结构对RON有不利的影响,反之亦然。例如,为了承受较高的VBD,典型的横向MOSFET要求较低的掺杂浓度,这就增大了开态比电阻(RSP)。
为了克服这一问题,已经提出了几种设计,试图提供高击穿电压和低RON×面积的可接受的组合。例如,已经设计了具有一个或多个降低了表面场(RESURF)的区域和/或局域化掺杂的区域(也称为超结结构或多导电结构)的器件。但这些设计要求昂贵的晶片加工,涉及到多次掩蔽和离子注入步骤、非常深的扩散本体区或接触(例如30-40微米深)、和/或昂贵的绝缘体上硅衬底,这就提高了芯片制造的成本。
因此,对于改善横向MOSFET器件的RON×面积性能,同时保持高阻挡电压能力和制造灵活性的成本可行的结构和方法,存在着需求。
发明内容
根据本发明的一方面,提供一种制作横向IGFET器件的方法,包括下列步骤:提供具有第一导电类型的漂移区的半导体衬底,其中,此半导体衬底包含第二导电类型;形成邻近漂移区的第二导电类型的本体区;形成邻近漂移区的第一导电类型的漏接触区;在漏接触与本体区之间的漂移区中形成分隔开的沟槽;用第一导电类型的掺杂剂,对分隔开的沟槽的侧壁和下表面进行掺杂,以便在漂移区内形成第一掺杂区,其中,第一掺杂区的掺杂浓度高于漂移区的掺杂浓度;用第二导电类型的掺杂剂,对分隔开的沟槽的侧壁和下表面进行掺杂,以便在第一掺杂区内形成第二掺杂区,其中,各沟槽具有与其下表面交叠的第一掺杂区和第二掺杂区;用材料填充分隔开的沟槽;在本体区中形成第一导电类型的源区;以及形成邻近本体区的栅结构。
根据本发明的另一方面,提供一种制作横向IGFET器件的方法,包括下列步骤:提供具有第一导电类型的半导体区的半导体衬底;在半导体区内形成第一和第二沟槽;形成邻近第一和第二沟槽侧壁和下表面的第一导电类型的第一区;形成邻近第一和第二沟槽侧壁和下表面的第二导电类型的第二区;将材料置于第一和第二沟槽内,以便在半导体层内形成超结结构;在邻近超结结构一侧的半导体衬底中,形成第二导电类型的本体区;形成邻近超结结构反侧的第一导电类型的漏接触区;在本体区中,形成第一导电类型的源区;以及形成邻近本体区的栅结构。
根据本发明的另一方面,提供一种横向IGFET器件,包括:第一导电类型的漂移区;形成在漂移区中的第二导电类型的本体区;形成在漂移区中的第一导电类型的漏接触区;形成在漏接触区与本体区之间的漂移区中的第一和第二沟槽;形成在第一和第二沟槽的侧壁和下表面中的第一导电类型的第一掺杂区,其中,第一掺杂区的掺杂浓度高于漂移区的掺杂浓度;形成在第一和第二沟槽的侧壁和下表面中的第二导电类型的第二掺杂区,其中,第一和第二掺杂区都围绕着第一和第二沟槽的下表面;形成在本体区中的第一导电类型的源区;以及邻近本体区形成的栅结构。
根据本发明的另一方面,提供一种制作横向IGFET器件的工艺,包括下列步骤:在第一表面处的第一导电类型的漂移区内,形成第一和第二沟槽;在第一和第二沟槽内,形成第一导电类型的第一外延层,其中,第一外延层的掺杂浓度高于半导体区的掺杂浓度;在第一和第二沟槽内的第一外延层上,形成第二导电类型的第二外延层,其中,第一和第二外延层填充第一和第二沟槽,以便提供超结结构;在邻近第一表面的超结结构的一侧上,形成第二导电类型的本体区;在邻近第一表面的超结结构的反侧上,形成第一导电类型的漏接触区;在本体区内形成第一导电类型的源区;以及形成邻近本体区的栅结构。
附图说明
图1示出了根据本发明的半导体器件的局部放大剖面图;
图2示出了根据本发明第一实施方案的图1半导体器件一部分沿参考线1-1的局部放大等轴剖面图;
图3示出了图1半导体器件一部分在制造的早期阶段的局部放大剖面图;
图4示出了根据本发明第二实施方案的图1半导体器件一部分的局部放大轴等剖面图;
图5示出了根据本发明第三实施方案的图1半导体器件一部分的局部放大等轴剖面图;
图6示出了本发明另一实施方案的一部分的局部放大等轴剖面图;
图7示出了本发明另一实施方案的一部分的局部放大等轴剖面图;
图8示出了本发明另一实施方案的一部分的局部放大等轴剖面图;
图9示出了本发明另一实施方案的一部分的局部放大等轴剖面图;
图10示出了根据本发明不同实施方案的半导体器件的局部放大剖面图;
图11示出了根据第一实施方案的图10半导体器件一部分沿参考线2-2的局部放大等轴剖面图;
图12示出了根据第二实施方案的图10半导体器件一部分沿参考线2-2的局部放大等轴剖面图;
图13-18示出了根据本发明的方法制作的半导体器件一部分在制造的各个阶段的局部放大剖面图;
图19示出了根据变通的制造方法制作的另一半导体器件一部分的局部放大剖面图;而
图20示出了根据本发明的另一半导体器件一部分的局部放大剖面图。
具体实施方式
为了容易理解,各附图中的元件无须按比例绘制,且相似的参考号被适当地用于所有附图。为了附图清晰,器件结构的掺杂区被示为通常具有直线边沿和角度精确的角落。但本技术领域的熟练人员理解的是,由于掺杂剂的扩散和激活,掺杂区的边沿通常不是直线,且角落通常也不是精确的角度,而是典型被倒圆。
此外,为了简化描述而省略了众所周知步骤和元件的描述和细节。虽然这些器件在此处被解释为某种n沟道器件,但本技术领域的一般熟练人员可理解的是,根据本发明,借助于适当地改变各区域的导电类型,p沟道器件以及互补器件也是可以的。所示的实施方案适合于阻挡约为700V的电压。
图1示出了根据本发明的一种绝缘栅场效应晶体管(IGFET),即横向FET、横向MOSFET、半导体或开关器件、结构、或单元10的局部剖面图,此绝缘栅场效应晶体管10具有改进了的RON×面积和高的阻挡电压能力。举例来说,MOSFET单元10是集成在半导体芯片中作为功率集成电路一部分的许多这种单元中的一种。或者,MOSFET单元10是一种单个的分立晶体管。
器件10包括半导体材料区或衬底11,它包含例如掺杂浓度约为每立方厘米1.5×1014原子的p型区或衬底。半导体材料区11包括主表面14。器件10还包括阱区,即扩散区、漂移区、或延伸的漏区13,本实施方案中的阱包括n型导电性。阱区13被形成在衬底11中,并从主表面14延伸。举例来说,阱区13的掺杂浓度约为每立方厘米4.0×1014-1.0×1016原子,且深度或厚度约为5-15微米。
隔离区或场区31被形成在器件10上、器件10上方、器件10中、或与器件10重叠,以便提供局域化钝化区。隔离区31包含例如硅的局域化氧化(LOCOS)区、浅沟槽隔离区、场氧化物区、它们的组合之类。在一个实施方案中,隔离区31包含用LOCOS技术形成的厚度约为0.5-2.0微米的热场氧化物区。
器件10还包括p型高压区(PHV)、本体区或扩散区41、以及从主表面14延伸的n型源区43。本体区43部分地延伸进入到半导体材料区11内。p型掺杂区44被进一步形成在本体区41内,并用来降低器件10内的寄生效应等。漏接触区33被形成在部分阱区13中,并从主表面14延伸。漏接触区33包含n型导电性,并被掺杂以提供足够的欧姆结构。用常规的掩蔽和掺杂技术,来形成区域13、33、41、43、以及44。
包括薄的栅介质层53和栅电极51的栅结构46,被形成为邻近或重叠部分主表面14和本体区41。栅介质层53包含例如厚度约为0.01-0.1微米的氧化硅。或者,栅介质层53包含诸如氮化硅、五氧化钽、二氧化钛、钛酸锶钡之类的其它介质、或它们的包括与氧化硅的组合的组合。栅电极51包含例如掺杂的多晶硅、铝、铝合金、它们的组合之类。栅结构46控制着沟道58的形成以及器件10中的电流传导。
根据本发明,器件10还包括一个区域即超结结构61,它包含一对或多个分隔开的填充的沟槽、钝化的沟槽、或至少部分地(例如二侧上)界定或限定多个形成在部分阱区13内的具有相反或交替导电类型的条形掺杂区的填充的条形沟槽或凹槽。
在一个实施方案中,填充的条形沟槽和条形掺杂区基本上彼此平行。区域61在极小的表面区内提供了具有低开态电阻的器件10,同时保持了高的击穿电压。区域61被分隔于本体区41一定距离,例如约为1-4微米。下面结合图2-9来描述区域61的各种实施方案。
图2示出了沿图1中参考线1-1的器件10一部分的局部放大等轴剖面图,用来说明区域61的第一实施方案。在本实施方案中,区域61包含多个界定多个条形掺杂区64和66的填充的沟槽。具体地说,掺杂的条形区域64包含第一导电类型,并被夹在各为第二导电类型的条形掺杂区66之间。根据本发明的这一实施方案,区域64和66沿侧壁向沟槽23的深度方向延伸,但这些区域与沟槽23的底部或底壁不交叠。亦即,区域64和66大致沿沟槽23的侧壁部分终止,且这些区域不与沟槽23的底部表面接合或连接。区域64和66的深度大致等于沟槽23的深度。在本实施方案中,条形区域64包含与阱区13相同的导电类型,但掺杂浓度更高。举例来说,区域64的净峰值掺杂浓度约为每立方厘米1.0×1016-3.0×1016原子,且区域66的净峰值掺杂浓度约为每立方厘米1.0×1016-3.0×1016原子。
图3示出了器件10一部分的局部剖面图,来说明条形掺杂区或区域64和66的形成。在本实施方案中,沟槽23被首先从器件10的主表面14腐蚀进入到阱区13中。在一个实施方案中,各个沟槽23被分隔开一个约为2-7微米的距离,此距离决定于所需的RESURF电荷要求。沟槽23的深度依赖于器件10的电压额定值。举例来说,对于RON×面积为60欧姆×平方厘米以及击穿电压约为700V的器件,沟槽23的深度约为8-10微米,且宽度约为1-2微米。为了满足700V的击穿,漂移长度约为60微米。用常规的光刻和腐蚀技术,来形成这些沟槽23。举例来说,用使用氟或氯基化学剂的干法腐蚀技术,来腐蚀沟槽23。
接着,介质层或钝化区230被形成在沟槽23的底部处。例如,首先用氮化物或掩蔽层覆盖沟槽23的表面,随后,用各向异性腐蚀技术清除底部部分,以便暴露部分阱区13。然后,暴露部分被氧化,从而形成局域化的钝化区230,如沟槽23底部表面所示。区域230提供了一个掩模即保护层,以便防止区域64和66沿沟槽23的底部表面形成。举例来说,区域230的厚度各约为0.3-0.5微米。
然后,第一导电类型的掺杂剂(例如n型)被引入到沟槽23的侧壁表面中。举例来说,倾斜的离子注入、气相掺杂、或固体源掺杂,被用来将掺杂粒子引入到阱区13中。图3示出了倾斜注入工艺作为一个例子,其中,箭头4表示掺杂剂离子的简化的大致轨迹。掩蔽层16防止了掺杂剂离子到达主表面14。在一个实施方案中,第一导电类型的掺杂剂然后在热处理过程中被扩散到阱区13中,从而形成第一导电类型区域64。举例来说,第一导电类型掺杂剂在1200℃下被扩散大约30分钟。
接着,第二导电类型的掺杂剂(例如p型)被引入到沟槽23的侧壁表面中(例如倾斜的离子注入、气相掺杂、或固体源掺杂),然后在热工艺中被扩散到阱区13中,从而提供图2所示的第二导电类型区域66。在一个实施方案中,从邻近沟槽23引入的第一导电类型掺杂剂一起扩散,从而形成图2所示的连接或接合区域64。
借助于首先扩散第一导电类型的掺杂剂,随后通过沟槽23的侧壁表面将第二导电类型掺杂剂扩散到第一导电类型区中,得到了沿漂移区深度方向和长度的完全受控的n型和p型区。此外,借助于使区域64位于阱区13与区域66之间,得到了适当的电荷平衡以及改善了的击穿电压特性。区域64在开态工作过程中提供了电流的传导通道即路径。在关态工作过程中,区域64和66彼此补偿,从而增强了击穿电压能力。
在随后的一个步骤中,用诸如氧化物(例如热氧化物、淀积的氧化物、或甩涂的氧化物)、氮化物、半绝缘多晶硅(SIPOS)、不掺杂的多晶半导体材料(例如多晶硅)、它们的组合之类的材料或介质材料24,来填充沟槽23。这在第一导电类型(例如n型)阱区内提供了一种超结结构61,它具有多个(例如一对)部分地(例如二个侧面上)界定第二导电类型(例如p型)掺杂的条形区域、第一导电类型(例如n型)掺杂的条形区域、以及第二导电类型(例如p型)掺杂的条形区域的填充的沟槽。根据本发明的这一实施方案,第二导电类型区域和第一导电类型区域与填充的沟槽的底部表面完全不交叠、不环绕、不连接。在一个实施方案中,第一和第二导电类型区域以及填充的沟槽终止于漂移区中基本上相等的深度处。在一个实施方案中,填充材料将沟槽23一直填充到或超过主表面14。
器件10的模拟分析表明能够阻挡高于700V的电压,同时得到小于60欧姆×平方厘米的RON×面积结果。
图4示出了器件10一部分沿图1中参考线1-1的局部放大等轴剖面图,来说明区域61的第二实施方案。与图2的第一实施方案相比,在此第二实施方案中,区域64和66的顺序被反转了。在本实施方案中,首先,第二导电类型区66被引入到沟槽23的侧壁表面中,随之以将第一导电类型区64引入到侧壁表面中。这在第一导电类型(例如n型)漂移区内提供了一种超结结构61,它具有多个(例如一对)部分地(例如二个侧面上)界定第一导电类型(例如n型)掺杂的条形区域、第二导电类型(例如p型)掺杂的条形区域、以及第一导电类型(例如n型)掺杂的条形区域的填充沟槽。根据本发明的这一实施方案,第二导电类型区域和第一导电类型区域与填充的沟槽的底部表面完全不交叠、不环绕、不连接。在一个实施方案中,第一和第二导电类型区域以及填充的沟槽终止于漂移区中基本上相等的深度处。
图5示出了根据本发明第三实施方案的部分器件10的局部放大等轴剖面图。在此实施方案中,第一导电类型区64被引入到沟槽23的一个侧壁中,而第二导电类型区66被引入到沟槽23的其它侧壁中。这提供了一种单侧超结结构61,其中,第一掺杂条形区(例如区域64)被形成为接合或连接一对条形填充沟槽之一,且其中,第二掺杂条形区(例如区域66)被形成为接合或连接一对条形填充沟槽中的另一个,且其中,第一掺杂条形区接合第二掺杂条形区。根据本发明的这一实施方案,第二导电类型区域和第一导电类型区域与填充的沟槽的底部表面完全不交叠、不环绕、不连接。在一个实施方案中,第一和第二导电类型区域以及填充的沟槽终止于漂移区中基本上相等的深度处。
图6示出了器件10另一实施方案的一部分的局部放大等轴剖面图。在此实施方案中,绝缘层或介质区71被形成在衬底11中并接合或邻近沟槽23的底部表面即下表面。在此实施方案中,绝缘层71将衬底11分隔于半导体层111。如所示,区域61被形成在半导体层111中,且绝缘层71延伸超过本体区41下方的阱区13。虽然示出了图2的区域61实施方案,但可以理解的是,例如此处所示的任何区域61的实施方案都可以与绝缘层71一起被使用。举例来说,绝缘层71包含氧化物,且厚度约为3-4微米,用高能离子注入或其它生长或淀积技术来形成。或者采用SOI衬底。
图7示出了器件10另一实施方案的一部分的局部放大等轴剖面图。在此实施方案中,局域化的绝缘层或局域化的介质区171将区域61的底部分隔于阱区13。具体地说,绝缘层171被形成或限制在阱区13内,并用腐蚀/外延生长再填充技术或高能离子注入技术来形成。
图8示出了器件10的另一实施方案的一部分的局部放大等轴剖面图。在此实施方案中,局域化的钝化区或局域化的介质区271沿沟槽23的横向方向向下邻近各沟槽的底部表面。在本实施方案中,阱区13各部分横向分隔各相邻局域化钝化区271。举例来说,在形成沟槽23之后,用各向同性腐蚀来形成区域271,这就在沟槽23下方形成了空腔。然后对空腔进行氧化。在一个实施方案中,区域271被限制或形成在阱区13内。此外,其它的实施方案仅仅包括其附近具有局域化钝化区271的部分沟槽23。
图9示出了器件100的本发明另一实施方案的一部分的局部放大等轴剖面图。除了如所示增加了位于本体区41的与区域61相反的一侧上的沟槽栅结构105之外,器件100相似于器件10。在此实施方案中,阱区113延伸在包括本体区41和沟槽栅结构105的有源器件下方。沟槽栅结构105包括栅介质层106和形成为重叠栅介质层106的导电电极107。栅介质层包含相同于栅介质层53的材料或其它材料。沟槽栅结构105提供了垂直沟道158等,以便协助尽可能减小电流聚集在沟道58中表面处。这进一步提供了区域61的更优化使用。在所示实施方案中,图2的超结区61被提供作为例子。可以理解的是,此处所示的其它超结实施方案可以与沟槽栅结构105进行组合。
图10示出了根据本发明另一实施方案的一种绝缘栅场效应晶体管(IGFET),即横向FET、横向MOSFET、半导体或开关器件、结构、或单元210的局部剖面图,此绝缘栅场效应晶体管210具有改进了的RON×面积性能和高的阻挡电压能力。举例来说,MOSFET单元210是集成在半导体芯片中作为功率集成电路一部分的许多这种单元中的一种。或者,MOSFET单元210是一种单个的分立晶体管。
如图10所示,除了漂移区或延伸的漏区213包含形成在衬底11上的外延层,或包含延伸在本体区41下方的扩散阱区之外,器件210相似于器件10。或者,当区域213包含扩散区或阱时,它终止于本体区41下方或如图1所示作为区域13。采用外延生长来形成区域213的一个好处是,与扩散阱或区域相比,提供了更厚的层或区域以及具有更受控的掺杂浓度分布。利用更厚的区域以及受控的浓度,人们能够采用更深的沟槽,这提供了更低的开态电阻。举例来说,衬底11包含掺杂浓度约为每立方厘米1.5×1014原子的p型衬底。而超结结构下方的区域213的电荷浓度约为每平方厘米0.2×1012-1.0×1012原子。
根据本发明的这一实施方案,器件210还包括一个区域或超结结构261,它包含一对或多个分隔开的填充沟槽或填充的条形沟槽或部分地界定多个形成在各填充沟槽之间和周围的阱区213部分内的具有相反或交替导电类型的条形掺杂区的凹槽。在一个实施方案中,填充沟槽与条形掺杂区基本上彼此平行。区域261提供了具有低的开态电阻同时保持高的击穿电压的器件210等。下面结合图11和12来描述区域261的各种实施方案。
图11示出了沿参考线2-2的半导体器件210一部分的局部放大等轴剖面图,用来说明根据本发明的区域261的第一实施方案。在此实施方案中,区域261包含形成在区域213内且在区域213中延伸的多个沟槽223。各沟槽223被分隔开,且横向延伸在区域41与33之间,典型的深度小于或等于区域213的深度或厚度。漏接触区33是超结区261的一侧,本体区41位于超结区261的反侧。第一导电类型即n型区264通过沟槽223的侧壁和底部表面即下表面被形成在区域213中,且第二导电类型即p型区266通过相同的侧壁和底部表面即下表面被形成在区域213中。在本实施方案中,区域264和266环绕沟槽223、与沟槽223完全交叠、或被形成在沟槽223周围,区域264终止于小于区域213的深度的深度处。亦即,区域264被分隔于衬底11。此外,区域264和266沿着漂移区213的深度和长度。举例来说,n型区264和p型区266的峰值掺杂浓度都约为每立方厘米1.0×1016-3.0×1016原子。
举例来说,用倾斜离子注入、气相掺杂、或固体源掺杂,来形成区域264和266。再举例来说,用剂量约为每平方厘米2.0×1013-5.0×1013原子的倾斜离子注入,来形成区域264和266。再举例来说,当相邻沟槽之间的距离约为5-7微米时,用剂量约为每平方厘米2.5×1013-4.5×1013原子的倾斜离子注入,来形成区域264和266。在一个例子中,离子注入之后在1200℃下大约30分钟,区域264被扩散。然后就完成了266的离子注入步骤,且区域266可以与本体区41同时被扩散。
区域264和266在沟槽223周围构成一个自补偿超结结构并用来尽可能减小来自各沟槽223之间和沟槽223下方的区域213部分的电荷影响等。而且,由于区域264和266与沟槽223的底部表面交叠,故提供了额外的电流路径以及沿沟槽223侧壁的电流路径,这降低了开态电阻。此外,由于区域213的掺杂浓度比区域264的小得多,故降低了典型地出现在n型阱区与p型本体之间的过早的击穿问题。
在后续的一个步骤中,用诸如氧化物(例如热氧化物、淀积的氧化物、或甩涂的氧化物)、氮化物、半绝缘多晶硅(SIPOS)、不掺杂的多晶半导体材料(例如多晶硅)、它们的组合之类的材料或介质材料224,来填充沟槽223。
图12示出了半导体器件210一部分沿参考线2-2的局部放大等轴剖面图,来说明根据本发明的区域261的第二实施方案。在本实施方案中,区域264被扩散,从而延伸通过区域213,以便接触衬底11和/或与邻接的264区合并在一起。
如图9进一步所示,图11和12所示的器件210可以进一步以修正的区域43和44的位置而组合图9所示的沟槽栅结构105。此外,在所示的二个实施方案中,区域261被分隔于本体区41。举例来说,区域261被分隔一个约为1-4微米的距离。
现在参照图13-19来描述用来形成本发明超结器件的一种变通方法。图13示出了制造早期步骤中的衬底11局部剖面图。在此实施方案中,衬底11包含p型导电性。接着,沟槽或凹槽323被腐蚀在衬底11中,从主表面14延伸。常规的掩蔽和腐蚀技术被用于此步骤。
图14示出了额外加工时的衬底11,其中,阱区13通过沟槽323的表面被形成在衬底11中。举例来说,n型掺杂剂被注入到表面内,并扩散到所希望的深度。或者采用气相掺杂或固体源掺杂技术。
图15示出了进一步加工之后的衬底11。在此阶段中,外延生长/回腐蚀或选择性外延生长技术被用来形成填充沟槽323的n型条形区或n型外延区364。接着,第二沟槽423被形成在外延区364内的衬底11中。在一个实施方案中,各沟槽423延伸通过区域364,以便暴露部分阱区13。在一个下面要更详细地解释的变通实施方案中,沟槽423不一直延伸通过区域364。接着,如结合图3所述,局域化的钝化区231被形成在图16所示的沟槽423的底部表面或下表面处。
图17示出了进一步加工之后的衬底11,其中,p型条形区366被形成在沟槽423的侧壁中。区域231掩蔽了沟槽423底部表面或下表面处的掺杂剂。举例来说,倾斜离子注入被用来形成区域366。或者采用气相掺杂或固体源掺杂技术。在进一步的一个步骤中,如图18所示,用氧化物(例如热氧化物、淀积的氧化物、或甩涂的氧化物)、氮化物、半绝缘多晶硅(SIPOS)、不掺杂的多晶半导体材料(例如多晶硅)、它们的组合之类,来填充沟槽223,以便提供超结结构,其中,n型区364和p型区365与沟槽423完全不交叠。区域231被留在原位或在填充沟槽423之前被清除。在一个变通实施方案中,各区域364被一起合并在阱区13中。
图19示出了变通实施方案的剖面图,其中,沟槽523被形成在外延区364中,但不一直延伸通过区域364。p型掺杂剂被引入到沟槽523的侧壁和底部表面或下表面,以便提供超结结构,其中n型区364和p型区366与沟槽523完全交叠。在后续步骤中,用材料424填充沟槽523。在一个变通实施方案中,各个区域364被一起合并在阱区13内。
图20示出了用来代替器件10中的结构61或器件210中的结构261的根据本发明另一实施方案的超结结构361的剖面图。结构361包括形成在漂移区、阱区、或外延区213中的多个填充的沟槽623。填充的沟槽623各包含填充部分沟槽623或形成在沟槽623的侧壁和下表面上的n型掺杂区364以及形成在区域364上的p型掺杂区566。在一个实施方案中,区域566填充了填充沟槽623的其余部分。例如用结合图13-15所述的腐蚀/外延生长方法,来形成结构361。然后,额外的沟槽被形成在各个区域364中,再在此结构上形成p型外延层,将任何过量的材料清除,以便提供图20所示的区域566和最终结构361。
于是,显然已经根据本发明提供了一种横向FET结构,此横向FET结构具有改进了的阻挡电压和开态比电阻性能。此结构组合了超结结构,此超结结构包含多个(至少一对)分隔开的填充沟槽或至少部分地界定或限定多个条形掺杂区的形成在阱区或漂移区中的具有相反或交替导电类型的填充的条形沟槽或凹槽。
虽然参照其具体的实施方案已经描述了本发明,但不要认为本发明局限于这些说明性的实施方案。例如,可以采用包括具有圆角或倒圆的底部表面的沟槽的更多的填充沟槽。或者,可以采用所公开的填充材料的组合,包括氧化物/氮化物、氧化物/SIPOS、氧化物/多晶硅、氧化物/氮化物/氧化物、它们的组合之类。本技术领域的熟练人员可以理解的是,能够作出各种修正和改变而不偏离本发明的构思。因此认为本发明包罗了所附权利要求范围内的所有这些改变和修正。
Claims (11)
1.一种制作横向绝缘栅场效应晶体管器件的方法,包括下列步骤:
提供具有第一导电类型的漂移区的半导体衬底,其中,此半导体衬底包含第二导电类型;
形成邻近漂移区的第二导电类型的本体区;
形成邻近漂移区的第一导电类型的漏接触区;
在漏接触与本体区之间的漂移区中形成分隔开的沟槽;
用第一导电类型的掺杂剂,对分隔开的沟槽的侧壁和下表面进行掺杂,以便在漂移区内形成第一掺杂区,其中,第一掺杂区的掺杂浓度高于漂移区的掺杂浓度;
用第二导电类型的掺杂剂,对分隔开的沟槽的侧壁和下表面进行掺杂,以便在第一掺杂区内形成第二掺杂区,其中,各沟槽具有围绕其下表面的第一掺杂区和第二掺杂区;
用材料填充分隔开的沟槽;
在本体区中形成第一导电类型的源区;以及
形成第一栅结构,其中第一栅结构邻近本体区。
2.根据权利要求1的方法,还包括形成第二栅结构的步骤,其中第二栅结构邻近本体区,并且第二栅结构的特征为沟槽结构。
3.一种制作横向绝缘栅场效应晶体管器件的方法,包括下列步骤:
提供具有第一导电类型的半导体区的半导体衬底;
在半导体区内形成第一和第二沟槽;
形成邻近第一和第二沟槽侧壁和下表面的第一导电类型的第一区;
形成邻近第一和第二沟槽侧壁和下表面的第二导电类型的第二区;
将材料置于第一和第二沟槽内,以便在半导体层内形成超结结构;
在半导体衬底中形成第二导电类型的本体区,其中本体区邻近超结结构的一侧;
在半导体衬底中形成第一导电类型的漏接触区,其中漏接触区邻近超结结构的相反一侧;
在本体区中,形成第一导电类型的源区;以及
形成第一栅结构,其中第一栅结构邻近本体区。
4.根据权利要求3的方法,其中,所述将材料置于第一和第二沟槽内的步骤包括安置选自由氧化物和多晶硅构成的组的材料。
5.根据权利要求3的方法,其中,所述将材料置于第一和第二沟槽内的步骤包括安置半绝缘多晶硅。
6.根据权利要求3的方法,其中,所述形成第一区的步骤包括下列步骤:
在半导体区中形成第一和第二凹槽;
在第一和第二凹槽内,形成第一导电类型的外延区;
在第一凹槽内形成第一沟槽,其中,第一沟槽部分地延伸进入到第一凹槽内的外延区中;以及
在第二凹槽内形成第二沟槽,其中,第二沟槽部分地延伸进入到第二凹槽内的外延区中,且其中,在第一和第二沟槽周围的外延区部分提供第一区。
7.根据权利要求3的方法,还包括形成邻近本体区的第二栅结构的步骤。
8.一种横向绝缘栅场效应晶体管器件,包括:
第一导电类型的漂移区;
形成在漂移区中的第二导电类型的本体区;
形成在漂移区中的第一导电类型的漏接触区;
形成在漏接触区与本体区之间的漂移区中的第一和第二沟槽;
形成在第一和第二沟槽的侧壁和下表面中的第一导电类型的第一掺杂区,其中,第一掺杂区的掺杂浓度高于漂移区的掺杂浓度;
形成在第一和第二沟槽的侧壁和下表面中的第二导电类型的第二掺杂区,其中,第一和第二掺杂区都围绕着第一和第二沟槽的下表面;
形成在本体区中的第一导电类型的源区;以及
邻近本体区形成的第一栅结构。
9.根据权利要求8的器件,还包括形成在与所述第一和第二沟槽相反的一侧上的第二栅结构。
10.一种制作横向绝缘栅场效应晶体管器件的工艺,包括下列步骤:
在第一表面处的第一导电类型的漂移区内,形成第一和第二沟槽;
在第一和第二沟槽内,形成第一导电类型的第一外延层,其中,第一外延层的掺杂浓度高于半导体区的掺杂浓度;
在第一和第二沟槽内的第一外延层上,形成第二导电类型的第二外延层,其中,第一和第二外延层提供超结结构;
在邻近第一表面的超结结构的一侧上,形成第二导电类型的本体区;
在邻近第一表面的超结结构的相反一侧上,形成第一导电类型的漏接触区;
在本体区内形成第一导电类型的源区;以及
形成邻近本体区的栅结构。
11.根据权利要求10的工艺,其中,所述形成栅结构的步骤包括形成沟槽栅结构。
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KR101215858B1 (ko) | 2012-12-31 |
TWI353025B (en) | 2011-11-21 |
TW200709303A (en) | 2007-03-01 |
US7381603B2 (en) | 2008-06-03 |
US20070023855A1 (en) | 2007-02-01 |
KR20070015891A (ko) | 2007-02-06 |
HK1103167A1 (en) | 2007-12-14 |
CN1909200A (zh) | 2007-02-07 |
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