CN1877995A - Method and apparatus for transmitting chip interface data - Google Patents
Method and apparatus for transmitting chip interface data Download PDFInfo
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- CN1877995A CN1877995A CNA2006100333880A CN200610033388A CN1877995A CN 1877995 A CN1877995 A CN 1877995A CN A2006100333880 A CNA2006100333880 A CN A2006100333880A CN 200610033388 A CN200610033388 A CN 200610033388A CN 1877995 A CN1877995 A CN 1877995A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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Abstract
The invention discloses a transmitting method of chip interface data and device, which comprises the following steps: proceeding positional exclusion for N-position outputting data of native and next beats at output end; producing differential value pattern (N is natural number); outputting inversed-making signal when the code weight of differential value pattern is more than half N; proceeding inversed-making output for next beat N-position outputting data; inversing the corresponding data at inversed-making output N-position data at receiving end; The invention controls turning number within N/2, which reduces noisy and power consumption greatly.
Description
Technical field
The present invention relates to data transferring technique, specifically, relate to the method and apparatus that a kind of chip interface data transmits.
Background technology
At present, along with the raising of chip clock speed, chip develops toward ultra-large direction, and the pin of chip is more and more, and the noise problem of overturning synchronously becomes the major issue of a reliable veneer of design.
As shown in Figure 1, be output as example with CMOS, chip interface is generally push-pull structure, and when sending data between 1 and 0 during conversion, the pin level is corresponding to overturn.As shown in Figure 2, when level overturn, this circuit voltage VD will enter into another saturation region from the saturation region through linear zone.Corresponding in linear district, will there be bigger electric current to flow through circuit, will cause bigger power supply noise like this.The I/O end of chip interface has distributed capacitance, the power supply noise when this also can strengthen upset.
If it is a lot of that the pin of level upset takes place simultaneously, power supply power consumption can increase on the one hand; On the other hand, the intensity of this power supply noise is very big, is coupled to other parts by ground level or power line, will influence the normal operation of circuit.
Therefore the number of pins that reduces upset simultaneously reduces power supply noise and all benefit for reducing power supply power consumption, but does not also have overturn a simultaneously technical scheme of number of pins of minimizing on the logical design aspect at present.
Summary of the invention
The purpose of this invention is to provide the method and apparatus that a kind of chip interface data transmits, reduce chip pin level synchronization upset number.
For achieving the above object, the invention provides the method that a kind of chip interface data transmits, may further comprise the steps:
At transmitting terminal, the N position of this bat is treated that the N position of dateout and next bat treats that dateout carries out the step-by-step XOR, obtain difference pattern, N is a natural number;
When the code weight of difference pattern during greater than N/2, output negate signal, dateout negate output is treated in the N position of described next bat;
At receiving terminal, when receiving the negate signal, to the bat negate of the N bit data of described negate output in correspondence.
Wherein when the code weight of described difference pattern during smaller or equal to N/2, export not negate signal, the N position of next bat treats that dateout directly exports;
Described negate signal and not negate signal are the C bit data, and wherein C is a natural number.
The object of wherein said step-by-step XOR is that the N position of described bat treats that dateout adds described negate signal or described not negate signal, treats that with the N position of described next bat dateout adds C position setting data, obtains N and adds C potential difference value pattern;
When the code weight of difference pattern during, output negate signal, otherwise export not negate signal greater than (N+C)/2.
The device that the present invention also provides a kind of chip interface data to transmit, comprise: the Hamming distance judging module, be positioned at transmitting terminal, the N position that receives this bat treats that the N position of dateout and next bat treats dateout, two groups of data are carried out the step-by-step XOR, and whether the difference pattern that obtains is judged code weight greater than N/2, when the time greater than N/2, output negate signal, described N is a natural number;
The negate module, the negate signal that dateout and Hamming distance judging module send is treated in the N position that receives described next bat, the negate signal triggering is treated the dateout negate to the N position of described next bat, and the N bit data after the negate is sent to Hamming distance judging module and receiving terminal;
Decoding negate module is positioned at receiving terminal, receives the negate signal that N bit data after the described negate that the negate module sends and Hamming distance judging module send, N bit data corresponding clap in the negate of negate signal triggering after to described negate.
Comprise also that wherein output deposits module, described output is deposited module and is received the N position that described negate module sends and treat dateout, sends to Hamming distance judging module and receiving terminal.
Comprise also that wherein line of codes deposits module, described line of codes is deposited module and is received the described negate signal that described Hamming distance judging module sends, give described decoding negate module sending of correspondence, described line of codes is deposited module and is positioned at transmitting terminal or receiving terminal separately, or is integrated in the described decoding negate module.
Wherein said Hamming distance judging module comprises XOR device and code weight judging module, wherein
The XOR device treats that to the N position of described bat the N position of dateout and next bat treats that dateout carries out the step-by-step XOR, and the difference pattern that obtains is sent to the code weight judging module;
The code weight judging module compares code weight in the difference pattern and N/2, if greater than, output negate signal.
Wherein said code weight judging module comprises data 1 superimposer, data 0 superimposer and comparator, wherein,
Data 0 superimposer to 0 negate of the data in the difference pattern and stack, is exported to comparator with the result;
Comparator, the output result of comparing data 1 superimposer and data 0 superimposer, when the output result of data 1 superimposer greater than the output of data 0 superimposer as a result the time, output negate signal.
Wherein when described difference pattern during smaller or equal to N/2, the Hamming distance judging module is exported not negate signal.
Wherein said Hamming distance judging module also receives described negate signal and described not negate signal, the N position of described bat is treated that dateout adds described negate signal or described not negate signal, treat that with the N position of next bat dateout adds C position setting data and carries out the step-by-step XOR, and the difference pattern that obtains judged that whether code weight is greater than (N+C)/2, when greater than (N+C)/2, output negate signal, otherwise export not negate signal.
By technique scheme as can be seen, when data transmit, the present invention is by adding up the chip pin number that overturns synchronously with the step-by-step XOR, when upset number during greater than N/2, the data to be transferred negate is transmitted, make chip pin level synchronization upset number be controlled at, and then can significantly reduce the noise that brings because of pin upset synchronously, reduce power supply power consumption smaller or equal in the N/2 scope.
Description of drawings
Fig. 1 is a prior art chip interface structure;
Fig. 2 is level turnover voltage and an electric current variation diagram in the prior art;
Fig. 3 is principle of the invention figure;
Fig. 4 is chip interface data conveyer embodiment 1 of the present invention;
Fig. 5 is the cut-away view of Hamming distance judging module among Fig. 4;
Fig. 6 is the inside detailed structure view of Fig. 5;
Fig. 7 is chip interface data conveyer embodiment 2 of the present invention.
Embodiment
For understanding the present invention better, set forth core thinking of the present invention earlier.As shown in Figure 3, two width are after the binary number of N (N is a natural number, expression data bits, here N=11) carries out the step-by-step XOR, can obtain difference pattern.Each of difference pattern represents whether two bits of corresponding figure place are different.If two bit differences of the corresponding figure place of binary number, then the figure place of difference pattern correspondence is 1, otherwise then is 0.
Shown in the right figure of Fig. 3, if any one in described two binary numbers (not being two whiles) negate, also step-by-step negate of the difference pattern that obtains.Two difference patterns have a code weight (1 number), and smaller or equal to N/2, another is greater than N/2.As long as handle, just can guarantee that difference pattern can both be smaller or equal to N/2 so by negate.
According to this core thinking, the invention provides the method that a kind of chip interface data transmits:
1, at transmitting terminal, N position on this bat output bus is treated that dateout level and next clap the N position and treat that the dateout level carries out the step-by-step XOR, obtain difference pattern, difference pattern is that 1 position represent the corresponding positions on the bus different with the corresponding positions of the data of soon exporting.
2, judge that whether the code weight of difference pattern is greater than N/2.
If 3 code weights are greater than N/2, represent that the different data bits of next bat corresponding positions surpasses N/2, the figure place that then needs to overturn surpasses N/2, and next claps dateout negate output, the figure place that needs like this to overturn is just smaller or equal to N/2, and this beat of data of output negate signal indication is negate output; Otherwise when code weight during smaller or equal to N/2, next is clapped not negate of dateout and directly exports.
4, at receiving terminal, as receive the negate signal, the data level in answering the bid that receives is carried out negate.
By this method, the number of upset pin is controlled at smaller or equal in the N/2 scope in the time of with chip, and then can significantly reduce the noise that brings because of pin upset synchronously.
For realizing said method, the invention provides the device that a kind of chip interface data transmits:
As shown in Figure 4, the device that chip interface data provided by the invention transmits comprises the Hamming distance judging module, the negate module, and line of codes is deposited module, and module and decoding negate module are deposited in output.
The Hamming distance judging module that is positioned at transmitting terminal receives output and deposits the N position of this bat that module sends and treat that the N position of dateout and next bat treats dateout, two groups of data is carried out the step-by-step XOR, and the difference pattern that obtains is judged code weight.When code weight during greater than N/2, output negate signal is deposited module and negate module to line of codes.
The negate module receives the negate signal that the N position treats that dateout and Hamming distance judging module send, and negate signal triggering negate module treats that to the N position dateout carries out negate, and the N position after the negate is treated that dateout sends to output and deposits module; If the negate module does not receive the negate signal in one claps, the N position is treated that dateout directly sends to output and deposits module.
Output is deposited module and is received the N bit data that the negate module sends, and correspondingly dateout is treated in this N bit data N position of having become this bat, sends to the Hamming distance judging module in this bat, sends to the decoding negate module of receiving terminal simultaneously.
Line of codes is deposited module and is received the negate signal that the Hamming judging module sends, and sends to decoding negate module through certain time hysteresis in the bat of correspondence.Decoding negate module received code line is deposited negate signal and the output that module sends and is deposited the N bit data that module sends, negate signal triggering decoding negate module in the bat of correspondence to this data negate.
In this device, line of codes is deposited module and be can be used as an independent module and be positioned at transmitting terminal and receiving terminal, also can be integrated in the decoding negate module of receiving terminal, mainly be the effect of playing a time lag, makes the negate signal in the negate of the bat internal trigger N of correspondence bit data.Dui Ying bat refers to next bat in the ordinary course of things, but under some particular case, receiving terminal may just be received and dispatched the data that sending end is sent after several bats even tens are clapped, corresponding bat just refers to and the bat of negate signal correspondence, so keeps the locking phase of data and negate signal to work as important.
In practice, decoding negate module may include synchronizer, receive the negate signal after, to the N bit data negate of next bat, do not need line of codes to deposit module in this case.This structure can apply on the RAM data self defined interface.If RAM has the reserved place of a bit, just can be with this bit as bits of coded, with " 1 " expression negate signal.
Present ZBT, DDR2, chips such as QDR also can be under the conditions of the application before compatible fully, and will keep pin definitions is that line of codes is realized the present invention.
As shown in Figure 5, the Hamming distance judging module comprises XOR device and code weight judging module, and the XOR device treats that to the N position that receives dateout and N bit data output feedback carry out the step-by-step XOR, and the XOR result is sent to the code weight judging module; The code weight judging module with 1 number among the XOR result and N/2 relatively, if greater than, output negate signal, if smaller or equal to, do not export any signal or export not negate signal.Correspondingly, when the negate module receives not negate signal with decoding negate module, to the data in answering the bid are not dealt with.
As shown in Figure 6, when adopting analog circuit to realize the code weight judging module, the code weight judging module comprises data 1 superimposer 601, data 0 superimposer 602 and comparator 603.In data 1 superimposer 601, the data 1 in the difference pattern show as the level that is higher than certain value, and by 6011 stacks of first operational amplifier, first operational amplifier 6011 sends to comparator 603 with stack result through the smooth back of resistance.In data 0 superimposer 602, data 0 in the difference pattern show as the level that is lower than certain value, become the data 1 that level is higher than certain value by negate device 6023, by 6021 stacks of second operational amplifier, second operational amplifier 6021 sends to comparator with stack result again through the smooth back of resistance.Comparator 603 is the output result of two operational amplifiers relatively, when first operational amplifier, 6011 output results' level is exported results' level greater than second operational amplifier 6021, and comparator 603 output negate signals; When first operational amplifier, 6011 output results' level was exported results' level smaller or equal to operational amplifier 6021, comparator 603 was not exported any signal or is exported not negate signal.
The method and apparatus that the said chip interface data transmits is not considered the influence of the upset of line of codes to total upset number itself.In fact when the signal of Hamming distance judging module output was divided into negate signal and not negate signal, because the variation of signal, the upset of line of codes itself goes out also can increase synchronization noise.At this situation, the present invention also provides the following example:
The device that as shown in Figure 7 chip interface data transmits, different is that line of codes is deposited the output result of module except sending to decoding negate module, also feeds back to the Hamming distance judging module with Fig. 3.The output signal that line of codes is deposited module is C bit data (C is a natural number).C position negate signal and data output feedback constitutes the N+C bit data together so, and the Hamming distance judging module need be carried out XOR to two N+C bit data.Therefore the N position that is input to the Hamming distance judging module treats that dateout will increase C bit constant bit accordingly, and this C bit constant bit is the initial value of setting as required.
Accordingly, the code weight judging module in the Hamming distance judging module, be with 1 number among the XOR result with (N+C)/2 relatively, if greater than, output negate signal, if smaller or equal to, export not negate signal.
Getting C is 1, realizes that on this equipment the method that chip interface data transmits is:
1, at transmitting terminal, the data level that the data level on the current output bus and next bat need to transmit on the bus is carried out the step-by-step XOR, obtain difference pattern.Data level on the wherein current output general line is that N bit data level that module feedback is deposited in output adds that line of codes deposits 1 bit data level of module feedback, and the data level that next bat needs to transmit on the bus is meant that the N position treats that dateout adds 1 bit constant bit.The difference pattern that obtains is the N+1 position.
2, judge that whether the code weight of difference pattern is greater than (N+1)/2.
Different data bitss surpasses (N+1)/2 if 3 code weights, are represented next bat corresponding positions greater than (N+1)/2, and the figure place that then needs to overturn surpasses (N+1)/2.Next claps dateout negate output, and this beat of data of output negate signal indication is negate output; Otherwise, when code weight smaller or equal to (N+1)/2, next is clapped not negate of dateout and directly exports.
4, at receiving terminal, as receive the negate signal, the signal in the corresponding umber of beats that receives is carried out negate.
The present invention can be used between the chip, also can be used between chip and other circuit, can also be used for being integrated between the sub-chip of cascade of a chip, and in a word, all have the chip of transmitting terminal and receiving terminal to be suitable for.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1, a kind of method of chip interface data transmission is characterized in that, may further comprise the steps:
At transmitting terminal, the N position of this bat is treated that the N position of dateout and next bat treats that dateout carries out the step-by-step XOR, obtain difference pattern, N is a natural number;
When the code weight of difference pattern during greater than N/2, output negate signal, dateout negate output is treated in the N position of described next bat;
At receiving terminal, when receiving the negate signal, to the bat negate of the N bit data of described negate output in correspondence.
2, the method that transmits of chip interface data as claimed in claim 1 is characterized in that, when the code weight of described difference pattern during smaller or equal to N/2, exports not negate signal, and the N position of next bat treats that dateout directly exports;
Described negate signal and not negate signal are the C bit data, and wherein C is a natural number.
3, the method for chip interface data transmission as claimed in claim 2, it is characterized in that, the object of described step-by-step XOR is that the N position of described bat treats that dateout adds described negate signal or described not negate signal, treat that with the N position of described next bat dateout adds C position setting data, obtain N and add C potential difference value pattern;
When the code weight of difference pattern during, output negate signal, otherwise export not negate signal greater than (N+C)/2.
4, a kind of device of chip interface data transmission is characterized in that, comprising:
The Hamming distance judging module is positioned at transmitting terminal, and the N position that receives this bat treats that the N position of dateout and next bat treats dateout, two groups of data are carried out the step-by-step XOR, and whether the difference pattern that obtains is judged code weight greater than N/2, when the time greater than N/2, output negate signal, described N is a natural number;
The negate module, the negate signal that dateout and Hamming distance judging module send is treated in the N position that receives described next bat, the negate signal triggering is treated the dateout negate to the N position of described next bat, and the N bit data after the negate is sent to Hamming distance judging module and receiving terminal;
Decoding negate module is positioned at receiving terminal, receives the negate signal that N bit data after the described negate that the negate module sends and Hamming distance judging module send, N bit data corresponding clap in the negate of negate signal triggering after to described negate.
5, the device that transmits of chip interface data as claimed in claim 4 is characterized in that, comprises that also output deposits module, and described output is deposited module and received the N position that described negate module sends and treat dateout, sends to Hamming distance judging module and receiving terminal.
6, the device that transmits as claim 4 or 5 described chip interface datas, it is characterized in that, comprise that also line of codes deposits module, described line of codes is deposited module and is received the described negate signal that described Hamming distance judging module sends, give described decoding negate module sending of correspondence, described line of codes is deposited module and is positioned at transmitting terminal or receiving terminal separately, or is integrated in the described decoding negate module.
7, the device of chip interface data transmission as claimed in claim 4 is characterized in that described Hamming distance judging module comprises XOR device and code weight judging module, wherein
The XOR device treats that to the N position of described bat the N position of dateout and next bat treats that dateout carries out the step-by-step XOR, and the difference pattern that obtains is sent to the code weight judging module;
The code weight judging module compares code weight in the difference pattern and N/2, if greater than, output negate signal.
8, the device of chip interface data transmission as claimed in claim 7 is characterized in that described code weight judging module comprises data 1 superimposer, data 0 superimposer and comparator, wherein,
Data 1 superimposer, the data 1 in the described difference pattern that superposes are exported to comparator with the result;
Data 0 superimposer to 0 negate of the data in the difference pattern and stack, is exported to comparator with the result;
Comparator, the output result of comparing data 1 superimposer and data 0 superimposer, when the output result of data 1 superimposer greater than the output of data 0 superimposer as a result the time, output negate signal.
9, the device that transmits of chip interface data as claimed in claim 4 is characterized in that, when described difference pattern during smaller or equal to N/2, the Hamming distance judging module is exported not negate signal.
10, the device of chip interface data transmission as claimed in claim 9, it is characterized in that, described Hamming distance judging module also receives described negate signal and described not negate signal, the N position of described bat is treated that dateout adds described negate signal or described not negate signal, treat that with the N position of next bat dateout adds C position setting data and carries out the step-by-step XOR, and the difference pattern that obtains judged that whether code weight is greater than (N+C)/2, when greater than (N+C)/2, output negate signal, otherwise export not negate signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100333880A CN1877995A (en) | 2006-01-24 | 2006-01-24 | Method and apparatus for transmitting chip interface data |
| PCT/CN2007/000213 WO2007085181A1 (en) | 2006-01-24 | 2007-01-19 | Data transmission method and device for chip interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNA2006100333880A CN1877995A (en) | 2006-01-24 | 2006-01-24 | Method and apparatus for transmitting chip interface data |
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| CN1877995A true CN1877995A (en) | 2006-12-13 |
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| CNA2006100333880A Pending CN1877995A (en) | 2006-01-24 | 2006-01-24 | Method and apparatus for transmitting chip interface data |
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| CN (1) | CN1877995A (en) |
| WO (1) | WO2007085181A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104360976A (en) * | 2014-11-27 | 2015-02-18 | 杭州国芯科技股份有限公司 | Data encoding and decoding method for DDR (double data rate) interface |
| CN105760329A (en) * | 2016-02-01 | 2016-07-13 | 中国电子科技集团公司第三十八研究所 | Coding and decoding device capable of reducing bus coupling overturn |
| CN107682020A (en) * | 2017-10-26 | 2018-02-09 | 北京邮电大学 | A kind of coding based on Turbo code, coding/decoding method and device |
| CN108022612A (en) * | 2017-12-13 | 2018-05-11 | 晶晨半导体(上海)股份有限公司 | A kind of jump method of data edge |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113541912B (en) * | 2020-04-17 | 2022-11-01 | 苏州库瀚信息科技有限公司 | Data transmission device and method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5648973A (en) * | 1996-02-06 | 1997-07-15 | Ast Research, Inc. | I/O toggle test method using JTAG |
| JP3777884B2 (en) * | 1999-07-23 | 2006-05-24 | セイコーエプソン株式会社 | Display driver IC and electronic device using the same |
| CN1318973C (en) * | 2003-10-31 | 2007-05-30 | 华为技术有限公司 | Method and device for protecting external bus of CPU |
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2006
- 2006-01-24 CN CNA2006100333880A patent/CN1877995A/en active Pending
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2007
- 2007-01-19 WO PCT/CN2007/000213 patent/WO2007085181A1/en active Application Filing
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104360976A (en) * | 2014-11-27 | 2015-02-18 | 杭州国芯科技股份有限公司 | Data encoding and decoding method for DDR (double data rate) interface |
| CN104360976B (en) * | 2014-11-27 | 2017-11-17 | 杭州国芯科技股份有限公司 | A kind of data decoding method of ddr interface |
| CN105760329A (en) * | 2016-02-01 | 2016-07-13 | 中国电子科技集团公司第三十八研究所 | Coding and decoding device capable of reducing bus coupling overturn |
| CN105760329B (en) * | 2016-02-01 | 2018-07-10 | 中国电子科技集团公司第三十八研究所 | A kind of coding and decoding device for reducing bus coupling overturning |
| CN107682020A (en) * | 2017-10-26 | 2018-02-09 | 北京邮电大学 | A kind of coding based on Turbo code, coding/decoding method and device |
| CN107682020B (en) * | 2017-10-26 | 2020-09-04 | 北京邮电大学 | Encoding and decoding method and device based on Turbo code |
| CN108022612A (en) * | 2017-12-13 | 2018-05-11 | 晶晨半导体(上海)股份有限公司 | A kind of jump method of data edge |
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| WO2007085181A1 (en) | 2007-08-02 |
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