CN1873924B - 半导体制造方法 - Google Patents

半导体制造方法 Download PDF

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Publication number
CN1873924B
CN1873924B CN2006100850891A CN200610085089A CN1873924B CN 1873924 B CN1873924 B CN 1873924B CN 2006100850891 A CN2006100850891 A CN 2006100850891A CN 200610085089 A CN200610085089 A CN 200610085089A CN 1873924 B CN1873924 B CN 1873924B
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Prior art keywords
wafer
dielectric constant
chip
layer
low
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Expired - Fee Related
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CN2006100850891A
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CN1873924A (zh
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阿部由之
宫崎忠一
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Renesas Electronics Corp
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Renesas Technology Corp
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Abstract

在对具有低介电常数层的半导体器件进行的非接触划片工艺中，如下减少或防止了层中诸如有缺陷形状或变色之类的较差外观的发生。在形成于半导体晶片的主表面上的层间绝缘层中形成低介电常数层。从晶片的背面将激光束聚焦在晶片的内部，以便选择性地形成改型区域。以使得接触低介电常数层或部分地进入低介电常数层的方式形成每个改型区域。在该形成工艺中，用冷却元件对半导体晶片进行冷却。这减少或防止了由于激光束的热量而可能发生的低介电常数层的变色。

Description

半导体制造方法
相关申请的交叉引用
本申请要求于2005年6月1日提交的日本专利申请No.2005-161803的优先权，在此将其内容通过参考引入本申请。
技术领域
本发明涉及半导体器件制造技术，并且更特别地涉及对于非接触划片(Stealth Dicing)技术有用的技术。
背景技术
非接触划片技术是这样一种技术，即用激光束照射半导体晶片的内部以选择性地形成改型层(modified layer)，并以该改型层作为分割起始点对半导体晶片进行切割。根据这种技术，甚至可以直接切割厚度大约为30微米的极薄的半导体晶片而不致产生物理应力，减少了碎裂并增大了每个半导体芯片的弯曲强度，取得了在半导体器件成品率和可靠性方面的进步。此外，由于不管半导体晶片的厚度如何都可以以300mm/s或更快的速度进行高速划片，因此提高了生产量。
例如，在日本未审专利公开No.2004-235626中提到了这种非接触划片技术。该文献的第0048-0053段以及图19和图20中公开了一种激光划片技术，其中用激光束照射晶片的背面以形成用于划片的改型层。在这种方法中，将晶片的正面保持在冷却槽中或保持在使用珀耳帖(Peltier)设备的冷却卡盘上，以防止晶片温度升高。
此外，日本未审专利公开No.2005-57257(第0087段和图13、图14)、日本未审专利公开No.2005-47290(第0040段和图16)以及日本未审专利公开No.2004-1076(第0075、0076段和图23)公开了一种技术，其中用激光照射晶片的背面，该激光聚焦在晶片厚度方向的多个点上。
此外，日本未审专利公开No.2005-28438(第0022段和图3)公开了一种技术，其中在晶片的内部于其深度方向上形成多个改型层，并且用分光器将激光束分开以便用一次聚焦在不同深度的点上的激光进行激光照射。
同样，日本未审专利公开No.2003-173988(第0011段和图1、图3)和日本未审专利公开No.2004-186635(第0057段和图5)公开了一种技术，其中当用激光束照射晶片的正面而使用于划片的该晶片熔化时，使激光束穿过水射流，以引导该激光束并对切割区域进行冷却以防止热退化。
此外，日本未审专利公开No.2004-282037(第0035、0036、0049段和图2)公开了一种技术，其中在对晶片的上表面进行不完全划片之后，将激光束投射在划片区域上以使切割条痕熔掉或蒸发掉。在这种激光照射工艺中，将晶片放置在水下的处理槽中以防止晶片的温度升高。
同样，日本未审专利公开No.Hei 7(1995)-256479(第0031-0034段和图1)公开了一种划片技术，其中用激光束照射衬底，同时将该衬底放置在水下的处理槽中，以防止该衬底的温度升高.
此外，日本未审专利公开No.2004-25187(第0010、0011段和图1)公开了一种技术，其中用珀耳帖设备对晶片的一侧进行冷却并用激光束对另一侧进行照射以便划片。
同样，日本未审专利公开No.Hei 9(1997)-29472(第0027-0031段和图1、图2)公开了一种技术，其中用珀耳帖设备对衬底的分割起始点进行冷却，并从另一侧照射激光束以形成用于分割的初始断裂。在该文献的第0022-0025段和图1中，公开了一种用于改进芯片的完成(finish)的技术，其中形成布线层以便用形成于其上的低k薄膜来吸收晶片的划片区域中的激光。
此外，日本未审专利公开No.2003-320466(第0007、0008段)公开了一种技术，其中在对晶片进行划片之前用激光束去除该硅晶片上的低介电常数薄膜。
同样，日本未审专利公开No.2003-151924(第0027-0029段和图1-3)公开了一种技术，其中在用刀片在晶片的一侧形成切口的同时，使激光束穿过水到达该晶片的另一侧以对该晶片进行划片。
发明内容
本发明人发现对在布线层中具有低介电常数薄膜(低k薄膜)的半导体器件进行的非接触划片工艺存在下述问题。
当将晶片分为单个芯片时，有可能会不适当地切割低介电常数薄膜并且低介电常数薄膜的断裂造成较差外观的问题。作为一种解决方案，用激光束在晶片中形成改型层，并且同时在低介电常数薄膜中形成分割起始点。然而，尽管这种方法使得可以整齐地切割低介电常数薄膜，但是本发明人首次发现了以下问题：激光的热量可以引起薄膜的变色(discoloration)。
本发明的一个目的是提供一种技术，该技术在对具有低介电常数层的半导体器件进行的非接触划片工艺中减少了或防止了低介电常数层的断裂的较差外观，诸如有缺陷的形状或变色之类。
从本说明书以及附图中的以下详细描述，本发明的上述及其他的目的和新颖特征将更充分地得以体现。
下面将简要概括在此公开的本发明的优选实施例。
根据本发明的一个方面，通过从晶片的背面沿着晶片的每个芯片的切割区域将激光束聚焦在晶片的内部，使得当在稍后对晶片和形成在该晶片主表面的布线层中的低介电常数层进行的晶片切割步骤中形成改型区域作为分割起始点时冷却该晶片。
根据本发明的另一个方面，非接触划片工艺包括通过从晶片的背表面照射激光束而在晶片中形成改型区域的步骤，以及从晶片的主表面在晶片主表面一侧上的布线层中的低介电常数层中形成切口的步骤。
下面简要描述由本发明的优选实施例所带来的效果。
由于通过从晶片的背面沿着晶片的每个芯片的切割区域将激光束聚焦于晶片的内部，使得当在稍后对晶片和形成在晶片主表面的布线层中的低介电常数层进行的晶片切割步骤中形成改型区域作为分割起始点时冷却该晶片，因此减少了或防止了诸如有缺陷的形状或变色之类的低介电常数层断裂的较差外观的发生。
附图说明
现在参考附图，更具体地描述本发明，其中：
图1是根据本发明的第一实施例的半导体器件制造工艺的流程图；
图2是图1中的制造工艺中的激光照射步骤的流程图；
图3是在图1中的前端工艺之后的半导体晶片的主表面的总体平面图；
图4是作为例子的图3中的半导体晶片的特征部分的放大平面图；
图5是图4中的区域R1的放大平面图；
图6是沿着图5中的线X1-X1所取的截面视图；
图7是在图1中的背表面加工步骤之后的半导体晶片的特征部分的截面视图；
图8是在图1中的激光照射步骤中的半导体晶片的特征部分的截面视图；
图9是示出了图8中的改型区域的截面形状的一个例子的半导体晶片的特征部分的放大截面视图；
图10是示出了图8中的改型区域的平面布置的一个例子的半导体晶片的特征部分的放大平面图；
图11是示出了图8中的改型区域的另一个例子的半导体晶片的特征部分的放大平面图；
图12是在图1中的晶片安装步骤之后的半导体晶片及其连接到的夹具的总体平面图；
图13是沿着图12中的线X2-X2所取的截面视图；
图14是在图1中的划片步骤之后的半导体晶片的截面视图；
图15是图14中的半导体晶片的特征部分的放大截面视图；
图16是根据本发明的第一实施例的半导体器件制造方法制造的半导体器件的一个例子的截面视图；
图17是沿着图5中的线X1-X1所取的、在根据本发明的另一个实施例的半导体器件制造工艺中在图1中的激光照射步骤之后的半导体晶片的截面视图；
图18是沿着图5中垂直于线X1-X1的线Y1-Y1所取的、在图1中的激光照射步骤之后的半导体晶片的截面视图；
图19是图17中的区域R2的放大截面视图；
图20是在根据本发明的另一个实施例的半导体器件制造工艺中在图1中的划片步骤之后的半导体晶片的特征部分的放大截面视图；
图21是在激光照射步骤中的半导体晶片的截面视图；
图22是在激光照射步骤中的半导体晶片的截面视图；
图23是根据本发明的另一个实施例的半导体器件制造工艺中的激光照射步骤的流程图；
图24示出了图23中的半导体器件制造工艺中的冷却步骤；
图25是在根据本发明的另一个实施例的半导体器件制造工艺中在图1中的晶片安装步骤之后的夹具和半导体晶片的截面视图；
图26是在紧接着图25中的步骤的图1中的划片步骤之后的夹具和半导体晶片的截面视图；
图27是在根据本发明的另一个实施例的半导体器件制造工艺中在图1中的前端工艺之后的半导体晶片的主表面的特征部分的放大平面图；
图28是在根据本发明的又一个实施例的半导体器件制造工艺中在图1中的前端工艺之后的半导体晶片的主表面的特征部分的放大平面图；
图29是沿着图27和图28中的线X3-X3所取的截面视图；
图30是根据本发明的另一个实施例的半导体器件制造工艺的流程图；
图31是在根据本发明的另一个实施例的半导体器件制造工艺的激光照射步骤中的半导体晶片的特征部分的截面视图；
图32是在半导体器件制造工艺中在图31的步骤之后的半导体晶片的一个例子的特征部分的放大平面图；
图33是沿着图32中的线X4-X4所取的截面视图；
图34是沿着图32中的线X5-X5所取的截面视图；
图35是在图30中的划片步骤之后的半导体晶片的特征部分的放大截面视图；
图36是在根据本发明的另一个实施例的半导体制造工艺中的前端工艺之后的半导体晶片的特征部分的放大平面图；
图37是沿着图36中的线X6-X6所取的截面视图；以及
图38是沿着图36中的线X7-X7所取的截面视图。
具体实施方式
以下将根据需要单独地描述下述的优选实施例，但是除非另有说明，否则这些优选实施例并非是彼此不相关的。这些实施例在整体上或部分地是彼此的变型，并且有时一种描述是另一种描述的具体形式或补充形式。同样，在下述的优选实施例中，即使在元件的数值数据(件数、数值、数量、范围等)是用特定的数值数字来表示时，除非另有说明或者其在理论上限于该特定的数值数字，否则这些数值数据都不限于所表示的特定数值数字；其可以大于或小于该特定的数值数字。在下述的优选实施例中，无需赘言，除非另有说明或在理论上必要，否则其组成元件(包括组成步骤)并非是必需的。同样地，在下述的优选实施例中，当对某些元件指示特定的形式、位置或其他因素时，除非另有说明或者除非从理论的观点看只应当使用该特定的形式、位置或其他因素，否则其都应当解释为包括实质上与这些特定形式、位置或其他因素等效或相似的形式、位置或其他因素。对于上面提到的数值或范围，情况也是如此。在用于说明优选实施例的所有图中，用相同的参考标号表示具有相同功能的元件，并且除非必要，否则省略对这些元件的重复描述。接下来，将参考附图详细地描述本发明的优选实施例。
第一实施例
现在将结合图3至图15根据图1和图2中的流程图来描述第一实施例。
在前端工艺100中，例如，首先制备一个从上面看几乎为一圆形的直径大约为300mm的半导体晶片(在下文中称为晶片).晶片1W具有在其厚度方向上彼此相对的主表面和背表面.然后，在晶片1W的主表面上形成多个半导体芯片(在下文中称为芯片).这种前端工艺100也称为晶片工艺、扩散工艺或晶片制造，是一种在晶片的主表面上形成芯片(器件和电路)以准备用于利用探针进行电测试等等的工艺.该前端工艺包括淀积步骤、掺杂步骤(扩散或离子注入)、光刻步骤、蚀刻步骤、金属化步骤、清洗步骤以及不同步骤之间的检查步骤.
图3是在前端工艺100之后的晶片1W的主表面的总体平面图；图4是作为例子的图3中的晶片1W的特征部分的放大平面图；图5是图4中的区域R1的放大平面图；图6是沿着图5中的线X1-X1所取的截面视图。例如，多个方形芯片1C(从上面看)排列在晶片1W的主表面上，每个芯片周围都具有切割区域(分割区域)CR。晶片1W的半导体衬底1S(在下文中称为衬底)用单晶硅(Si)制成，并且在其主表面上方形成器件或布线层1L。在这个阶段，晶片1W的厚度(衬底1S的厚度与布线层1L的厚度之和)例如约为775微米。在图3中，N代表槽口。在图5中，CL代表切割线。切割线CL差不多沿着切割区域CR的宽度(短边)的中心延伸。
布线层1L包括层间绝缘层1Li、布线、键合焊盘(外部端子，在下文中称为焊盘)1LB、测试(TEG，或测试元件组)焊盘1LBt、对准目标Am以及表面保护层(在下文中称为保护层)1Lp。
层间绝缘层1Li包括层间绝缘层1Li1、1Li2和1Li3。层间绝缘层1Li1和1Li3由诸如氧化硅膜(SiO2等)之类的无机绝缘薄膜构成。层间绝缘层1Li2由诸如有机聚合物或有机硅玻璃薄膜之类的低介电常数薄膜(低k薄膜)构成。
可用作这种有机聚合物(完全有机的低介电层间绝缘层)的产品例如有SiLK(由美国的道氏化学公司(Dow Chemical Co.)制造；相对介电常数为2.7，耐热490℃或更高，介电击穿电压为4.0-5.0MV/Vm)和作为聚***(PAE)材料的FLARE(由美国的霍尼威尔电子材料(Honeywell Electronic Materials)公司制造；相对介电常数为2.8，耐热400℃或更高)。PAE材料提供了较高的基础性能并表现出了极好的机械强度和热稳定性，并且成本较低。
可用作上述的有机硅玻璃(SiOC)的产品包括HSG-R7(由日立化学有限公司(Hitachi Chemical Co.，Ltd.)制造；相对介电常数为2.8，耐热650℃)、黑钻石(Black Diamond)(由应用材料公司(Applied Materials，Inc.)制造；相对介电常数为3.0-2.4，耐热450℃)以及p-MTES(由HitachiKaihatsu公司制造；相对介电常数为3.2)。其他可用作SiOC材料的产品例如有CORAL(由美国的诺发***有限公司(Novellus Systems，Inc.)制造；相对介电常数为2.7-2.4，耐热500℃)和Aurora 2.7(由ASM JapanK.K制造；相对介电常数为2.7，耐热450℃)。
其他可用的低介电常数层材料包括完全无机的SiOF材料，诸如FSG(氟硅玻璃)、HSQ(含氢矽酸盐)材料、MSQ(含甲基矽酸盐)材料、多孔HSQ材料、多孔MSQ材料和多孔有机材料。
上述的HSQ材料包括OCD T-12(由东京应化工业株式会社(TokyoOhka Kogyo Co.，Ltd.)制造；相对介电常数为3.4-2.9，耐热450℃)、Fox(由美国的道康宁公司(Dow Corning Corp.)制造；相对介电常数为2.9)以及OCL T-32(由东京应化工业株式会社制造；相对介电常数为2.5，耐热450℃)。
上述的MSQ材料包括OCD T-9(由东京应化工业株式会社制造；相对介电常数为2.7，耐热600℃)、LKD-T200(由日本JSR公司制造；相对介电常数为2.7-2.5，耐热450℃)、HOSP(由霍尼威尔电子材料公司制造；相对介电常数为2.5，耐热550℃)、HSG-RZ25(由日立化学有限公司制造；相对介电常数为2.5，耐热650℃)、OCL T-31(由东京应化工业株式会社制造；相对介电常数为2.3，耐热500℃)以及LKD-T400(由日本JSR公司制造；相对介电常数为2.2-2，耐热450℃)。
上述的HSQ材料包括XLK(由道康宁公司制造；相对介电常数为2.5-2)、OCL T-72(由东京应化工业株式会社制造；相对介电常数为2.2-1.9，耐热450℃)、Nanoglass(由美国的霍尼威尔电子材料公司制造；相对介电常数为2.2-1.8，耐热500℃或更高)以及MesoELK(由美国的空气化工产品公司(Air Products and Chemicals，Inc.)制造；相对介电常数为2或更小)。
上述的多孔MSQ材料包括HSG-6211X(由日立化学有限公司制造；相对介电常数为2.4，耐热650℃)、ALCAP-S(由旭化成工业株式会社(Asahi Chemical Industry Co.，Ltd.)制造；相对介电常数为2.3-1.8，耐热450℃)、OCL T-77(由东京应化工业株式会社制造；相对介电常数为2.2-1.9，耐热600℃)、HSG-6210X(由日立化学有限公司制造；相对介电常数为2.1，耐热650℃)以及二氧化硅气凝胶(由神户制钢株式会社(Kobe Steel，Ltd.)制造；相对介电常数为1.4-1.1)。
上述的多孔有机材料包括PolyELK(由空气化工产品公司制造；相对介电常数为2或更小，耐热490℃)。
例如通过CVD(化学气相淀积)对上述的SiOC和SiOF材料进行淀积。例如，通过利用三甲基矽烷(trimethylsilane)与氧气的混合气体进行的CVD或类似的工艺对黑钻石(Black Diamond)进行淀积。通过利用三乙氧基甲基硅烷(methyltriethoxysilane)与N2O的混合气体进行的CVD或类似的工艺对p-MTES进行淀积。例如，通过涂覆，对其他的低介电常数绝缘材料进行淀积。
尽管为了更简单地进行说明，在图6中将层间绝缘层1Li2表示为单层，但其实际上是由多个低介电常数层组成的叠层。在这些低介电常数层中，层与层之间存在碳化硅(SiC)、碳氮化硅(SiCN)等的绝缘层。氧化硅(SiOx)(通常为二氧化硅(SiO2))的帽绝缘层可以位于碳化硅或碳氮化硅绝缘层与低介电常数层之间。该帽绝缘层的功能是确保低介电常数层在化学机械抛光(CMP)中的机械强度，保护表面并确保湿气抵抗性。帽绝缘层比低介电常数层薄。帽绝缘层的材料不限于氧化硅，并且可以是其他材料：例如，氮化硅(SixNy)、碳化硅或碳氮化硅。可以通过等离子体CVD来形成这些氮化硅、碳化硅或碳氮化硅层。通过等离子体CVD形成的碳化硅层的材料的一个例子是BLOk(由AMAT制造；相对介电常数为4.3)。在该形成工艺中，使用三甲基矽烷与氦(或N2、NH3)的混合气体。
为了更简单地进行说明，图6没有示出层间绝缘层1Li2中的布线，但是实际上在层间绝缘层1Li2中形成有上述的多层布线。这种布线可以是嵌入的。具体地说，通过将导体层嵌入在层间绝缘层1Li2的绝缘层中制成的布线沟槽中，完成布线。构成布线的导体层具有主导体层和覆盖其外表面(底表面和侧表面)的阻挡金属层。主导体层例如由铜(Cu)制成。阻挡金属层例如由氮化钛(TiN)、氮化钨(WN)、氮化钽(TaN)、钽(Ta)、钛(Ti)、钨(W)或钨化钛(TiW)或这些材料的叠层制成。
层间绝缘层1Li3上方的布线、焊盘1LB、1LBt和对准目标Am由如铝之类的金属制成.布线和焊盘1LB、1LBt位于最上面的位置，被形成为布线层1L的顶层的保护层1Lp所覆盖.例如，保护层1Lp是由诸如氧化硅之类的无机材料的绝缘层、淀积在它上方的诸如氮化硅之类的无机材料的绝缘层以及又淀积在它上方的诸如聚酰亚胺树脂之类的有机材料的绝缘层组成的叠层.在保护层1Lp的部分中形成孔2，并且焊盘1LB、1LBt通过该孔而部分地暴露.焊盘1LB沿着芯片1C的外缘排列并且通过布线与芯片1C的集成电路器件电连接.
测试焊盘1LBt和对准目标Am位于芯片1C的切割区域CR中。例如，测试焊盘1LBt从上面看为矩形，并且通过上述的布线与TEG元件电连接。对准目标Am是一个图形，用于使晶片1W的芯片1C与诸如曝光装置之类的制造装置对准，并且从上面看例如是十字形。可选地，该对准目标可以是L形状或点状。
接下来，在图1中的测试工艺101中，用探针在晶片1W的每个芯片1C的焊盘1LB和切割区域CR中的测试焊盘1LBt上执行各种电特性测试。这种测试工艺，也称作G/W(良好芯片/晶片)检查工艺，其主要目的是通过电方法来确定在晶片1W上方形成的每个芯片1C是否良好。
在图1中的随后的后端工艺102中，将芯片1C封装到管壳中以完成其制作。该工艺包括背表面加工阶段102A、划片阶段102B和装配阶段102C。
首先，在背表面加工阶段102A中，将晶片1W的主表面(芯片形成表面)用胶带粘住(步骤102A1)，然后测量晶片1W的厚度，并且根据所测厚度对晶片1W的背表面进行适量的研磨和抛光(步骤102A2、102A3)。图7是在这些步骤之后的晶片1W的特征部分的截面视图。胶带3a通过其粘着层牢固地粘附到晶片1W的主表面上。对于胶带3a，理想的是使用UV胶带。UV胶带应当具有UV硬化树脂的粘着层，并且具有较强的粘着力。当用紫外线照射UV胶带时，粘着层的粘着力迅速变弱。
其背表面已经研磨和抛光的晶片1W应当非常薄(超薄)，例如厚度是100微米或更小(在这种情况下大约为90微米)。如果芯片厚度是100微米或更小，则由背表面研磨步骤所引起的对背表面的损坏或应力可能会使芯片的弯曲强度变差，使得更可能由于在芯片安装期间施加到芯片上的压力产生芯片碎裂。作为对以上问题的解决方案，背表面抛光步骤对于防止对晶片1W的背表面的损坏或应力来说是很重要的。可以利用抛光垫和硅石(silica)或通过化学机械抛光(CMP)或通过例如使用硝酸和氟化酸(fluorinated acid)的刻蚀技术对背表面进行抛光。如果晶片1W的厚度大于150微米，则在某些情况下可以不需要背表面抛光步骤。图7中的虚线表示其背表面没有研磨和抛光的衬底1S。
接下来是划片阶段102B。在此，如图8所示，首先将其主表面粘附有胶带3a的极薄晶片1W传送到激光划片设备的装载装置，并放置在该激光划片设备的吸台5上(图2中的102B1-1)。图8是激光照射步骤中的晶片1W的特征部分的截面视图。吸台5可以通过真空接触临时固定晶片1W，并且还可以通过内置的冷却元件5a将晶片1W冷却到低于室温的温度，例如大约-40℃至5℃。该冷却元件5a可以是例如珀耳帖设备。珀耳帖设备使得晶片可以在干燥的气氛中被冷却。不需要担心凝露现象(dew condensation)。在图8中，箭头A示意性地示出了热辐射。吸台5可以在图8中的水平方向(晶片1W的直径方向)上移动。
然后，在冷却元件5a开始冷却晶片1W之后，通过红外摄像机(下文中称为IR摄像机)从晶片1W的背表面识别晶片1W的主表面上的图形(芯片1C和切割区域CR、该切割区域中的测试焊盘1LBt和对准目标Am以及芯片1C内部的焊盘1LB的图形).然后，根据从IR摄像机获得的图形信息，定位(对准)切削线CL(图2中的102B1-2).
接下来，用从激光束发生器发射出的激光束(能量束)LB照射同时被冷却的晶片1W，其中从晶片1W的背表面将光聚焦于晶片1W的内部，并通过沿着根据图形信息定位的切割线CL的相对运动来进行激光照射(图2中的102B1-3)。因此，通过多光子吸收在晶片1W内部形成改型区域(光损坏区域)。
这种通过用多光子吸收对晶片1W的内部进行加热和熔化形成的改型区域PL在随后的划片步骤中用作对晶片1W进行切割的起始点。熔化区域可以是一个曾经熔化然后重新固化的区域，或者是一个处于熔化状态的区域，或者是一个处于从熔化状态到重新固化状态的转变状态中的区域，并且还可以看作是一个已相变或晶体结构已经变化的区域。同样，熔化区域可以看作是一个其结构已经变为不同结构(单晶体、非晶体或多晶体)的区域。例如，对于衬底1S来说，意味着区域的结构从单晶体变为非晶体，或从单晶体变为多晶体，或从单晶体变为非晶体和多晶体结构的组合。例如，衬底1S中形成的改型区域PL是非晶硅。
由于晶片1W的背表面是激光束LB的入射平面，因此优选地其应当是平坦且光滑的，以避免或减小激光束LB的散射。同样，在改型区域PL的形成中，晶片1W的背表面几乎不吸收激光束LB，并且因此不熔化。激光束LB照射条件如下所述，但是并不限制为这样的条件。例如，激光类型是LD泵浦的固态脉冲激光；光源是波长为1064nm、频率为400kHz、激光功率为1W或更小以及激光点直径为1-2微米的YAG激光器；激光振荡器是高循环类型的；并且激光束移动速度为300mm/s。
图9是示出了改型区域PL的截面形状的一个例子的晶片1W的特征部分的放大截面视图。如图9中的左边所示，改型区域PL从衬底1S的部分通过层间绝缘层1Li1延伸到层间绝缘层1Li2的低介电常数层Lk1的部分。更具体地说，改型区域PL的纵向一端进入衬底1S中，另一端进入层间绝缘层1Li2的低介电常数层Lk1的部分中。改型区域PL在衬底内部的一部分在后续的划片步骤中用作对于衬底1S的分割起始点(在该处进行断裂)。另一方面，改型区域在层间绝缘层1Li2的低介电常数层Lk1内部的一部分在后续的划片步骤中用作对于层间绝缘层1Li2的低介电常数层Lk1的分割起始点。换言之，改型区域PL同时用作衬底1S和低介电常数层Lk1的分割起始点。这意味着，在后续的划片步骤中利用改型区域PL作为分割起始点，衬底1S和低介电常数层Lk1都可以被整齐地切割。因此，在非接触划片工艺中，减少了或防止了诸如有缺陷形状之类的低介电常数层Lk1的断裂的较差外观的发生。
当进行激光束LB照射以使改型区域PL接触或进入低介电常数层Lk1时，层Lk1会由于其较低的热传导率和在层Lk1中保留了激光束LB的热量而变色。因此，在该第一实施例中，在激光照射步骤中，在通过冷却元件5a对晶片1W的主表面进行冷却的同时进行激光束LB照射。因此，在激光照射步骤中减少或防止了低介电常数层Lk1的温度升高，由此减少或防止了其变色。因此，在非接触划片工艺中，减少了或防止了诸如变色之类的低介电常数层Lk1的断裂的较差外观的发生。
改型区域PL在衬底1S厚度方向上的尺寸D1大于在衬底1S半径方向(垂直于衬底1S的厚度方向)上的尺寸D2.这使得可以将分割起始点缩窄到很小的面积，并且还允许改型区域PL沿着应当进行断裂的方向延伸，使得可以整齐地切割晶片1W(衬底1S和低介电常数层).改型区域PL的较长尺寸D1(在衬底1S的厚度方向上)例如为20-40微米.改型区域PL的较短尺寸D2(在宽度方向上，或在衬底1S的垂直于其厚度方向的半径方向上)例如为2-5微米.
如果改型区域PL的端部太深地进入低介电常数层Lk1中，则低介电常数层Lk1可能会由于激光束LB的热量而变色。理想的是改型区域PL在低介电常数层Lk1内部的部分的尺寸D3为5微米或更小，但是这取决于激光束照射中的冷却温度或其他因素。更优选地，D3应当为大约3微米。因此，减少或避免了在改型区域PL的形成中低介电常数层LK1的变色，并且可以整齐地切割低介电常数层Lk1。
然而，如果改型区域PL的端部距离低介电常数层Lk1太远，固然可以防止低介电常数层Lk1的变色，但是改型区域PL就不能用作对于低介电常数层Lk1的分割起始点。因此，如图9中的右边所示，优选地改型区域PL的端部应当至少接触到低介电常数层Lk1。在这种情况下，也减少或避免了在改型区域PL的形成中低介电常数层Lk1的变色，并且改型区域PL可以用作对于低介电常数层Lk1的分割起始点。
图10和图11是示出了如上所述的改型区域PL的平面排列的一个例子的晶片1W的特征部分的放大平面图。为了更容易理解，在图10和图11中用阴影线标出了改型区域PL。
如图10所示，沿着切割线CL以形成点状线的方式排列改型区域PL。换言之，改型区域PL沿着切割线CL以规则间隔隔开。在这种情况下，由于可以减小为了形成改型区域PL而需要用激光束LB照射的区域，因此可以使激光束LB照射的热量产生最小化，并且减少或防止了由于热量引起的低介电常数层Lk1的变色。
图11示出了改型区域PL集中在划片可能困难的区域，诸如相互正交的切割线CL的交叉点和精细TEG图形的集中位置。这意味着可以容易地切割那些切割可能困难的区域，并且可以整齐地切割晶片1W。改型区域PL的平面排列并不限于上述的情况，而是可以有所变化；例如，可以沿着切割线呈线性排列。
在完成上述的激光照射步骤之后，将晶片1W传送到激光划片设备的卸载装置并设置在夹具中(图2中的102B1-4)。
接下来，如图12和图13所示，将从激光划片设备卸下的晶片1W粘附到夹具8的胶带8a上(图1中的晶片安装步骤102B2)，然后从晶片1W的主表面剥离胶带3a(图1中的102B3)。
图12是其上粘附有晶片1W的夹具8的总体平面图，图13是沿着图12中的线X2-X2所取的截面视图。夹具8具有胶带8a和环状物(框架)8b。胶带8a的基底8a1例如由弹性塑料制成，并且其主表面具有粘着层8a2。胶带8a牢固地固定在晶片1W的背表面上。换言之，晶片1W粘附到胶带8a上，其中晶片1W的主表面向上。对于胶带8a，理想地是使用UV胶带。UV胶带是具有UV硬化树脂的粘着层8a2并具有强粘着力的粘着胶带。当用紫外线照射它时，粘着层8a2的粘着力迅速变弱。
环状物8b是支撑胶带8a以免其松开的加固部件.就加固而言，理想地是用诸如不锈钢之类的金属来制作环状物8b，但是也可以用其厚度设计为可达到与金属相同程度的硬度的塑料来制成.在环状物的外缘上有槽口8b1、8b2.这些槽口8b1、8b2用于握持夹具并用于在夹具8与其中设置夹具8的制造装置之间的对准，并且还用于将夹具8钩挂到制造装置.
然后，如图14所示，在将夹具8放在夹具台架10上的情况下，沿着箭头E的方向将夹具8的环状物8b向下推，以使胶带8a在箭头F的方向上伸展。随着胶带8a的伸展，沿着晶片1W的厚度方向以改型区域PL作为分割起始点出现断裂，并且如图14和图15所示晶片1W被分为单独的芯片(图1中的102B4)。图14是在划片步骤102B4之后的晶片1W的截面视图，图15是图14中所示的晶片1W的特征部分的放大截面视图。
根据该第一实施例，由于形成了改型区域PL，使其端部在衬底1S和低介电常数层Lk1的内部，因此可以以改型区域PL作为分割起始点整齐地切割衬底1S和低介电常数层Lk1。因此，可以提高半导体器件的成品率。相反，在使用划片刀片切割晶片1W的刀片划片方法的情况下，为了避免芯片1C的质量变差，当晶片1W很薄时，必须降低切割速度(例如，降至60mm/s，或根据晶片1W的厚度降至低于60mm/s)，原因是否则将容易由于产生芯片弯曲强度的降低而在切割期间发生碎裂。另一方面，在该第一实施例中，由于只切割晶片1W的内部而不损坏其表面，因此可以使芯片1C表面上的碎裂最小化。因此，增大了芯片1C的弯曲强度。此外，由于作为用于切割的准备步骤，以300nm/s的速度迅速形成改型区域，因此提高了生产量。此外，由于如上所述晶片1W的主表面的切割区域CR中存在不传送激光束的测试焊盘1LBt，因此如果要用激光束从晶片1W的主表面照射晶片1W，测试焊盘1LBt就会妨碍改型(改型区域的形成)。另一方面，在本实施例中，由于是用激光束从晶片1W的背表面来照射晶片1W，因此可以在不引起上述问题的情况下适当地形成改型区域PL，并可以适当地切割晶片1W。
接下来是装配阶段102C。在此，将其上保持有多个芯片1C的夹具3传送到拾取装置。然后，在通过真空吸力保持住胶带8a的背面的情况下，通过推进栓(thrust pin)将芯片1C从胶带8a的背面推起。在胶带8a是如上所述的UV胶带的情况下，用紫外线照射胶带8a的粘着层8a2使该层硬化并使其粘着力变弱。然后，拾取装置的夹头通过真空吸力拾取芯片1C(图1中的拾取步骤102C1)。
接下来，例如将每个被如此拾取的芯片1C传送到印刷电路板或引线框的芯片安装区域，并通过粘结剂安装在印刷电路板等的芯片安装区域上。结果，芯片1C的背表面被粘合到印刷电路板等(图1中的芯片粘合(die bonding)步骤102C2)。可选地，可以将拾取的芯片放在传送盘中并将其运送到另一个制造工厂(例如，装配厂)以在那里进行后续的装配步骤(图1中的103A)。
接下来，通过键合导线(在下文中称为导线)将芯片1C的主表面上的焊盘1LB与印刷电路板等的电极相连接(图1中的102C3)。然后，利用传递模塑技术将芯片1C封装在如环氧树脂的塑料的管壳中(图1中的102C4)。
如果芯片1C具有凸块(bump)电极，则在拾取步骤102C中使芯片1C的主表面向下地将芯片1C传送到印刷电路板等的芯片安装区域，并在通过回流处理(热处理)将芯片1C的凸块电极与印刷电路板15的电极键合(倒装芯片键合)在一起之前，利用膏剂将芯片1C的凸块电极临时地固定到芯片安装区域中的电极上。在此之后，用底层填料填满芯片1C与印刷电路板等的两个相对面之间的空间并以与上述方法相同的方式对芯片1C进行封装。
图16是通过根据第一实施例的半导体器件制造方法制造的半导体器件14的一个例子的截面图。半导体器件14是在管壳中引入了所需功能的SIP(***级封装)。作为半导体器件14的组成部分，在印刷电路板15的背表面上具有凸块电极16的矩阵。多个薄芯片1C1至1C3(1C)叠置在印刷电路板15的主表面上。底部的芯片1C1通过其主表面上的凸块电极BMP安装在印刷电路板15的主表面上方。在芯片1C1的主表面上形成诸如CPU(中央处理器)和DSP(数字信号处理器)之类的逻辑电路。芯片1C2通过芯片粘附薄膜安装在芯片1C1的背表面上方。在芯片1C2的主表面上方形成诸如SRAM(静态随机存取存储器)和闪存之类的存储电路。芯片1C2的主表面上的焊盘1LB通过导线18与印刷电路板15的主表面上的电极电连接。芯片1C3通过间隔层19和芯片粘附薄膜17安装在芯片1C2的主表面上方。在芯片1C3的主表面上方形成诸如SRAM和闪存之类的存储电路，并且芯片1C3的主表面上的焊盘1LB通过导线18与印刷电路板15的主表面上的电极电连接。将芯片1C1至1C3和导线18例如封装在环氧树脂的管壳20中。
第二实施例
在第二实施例中，主要用作对于衬底1S的分割起始点的改型区域和主要用作对于低介电常数层Lk1的分割起始点的改型区域彼此是独立的。以下将结合图17至图20对此进行描述。
图17是沿着图5中的线X1-X1所取的、在图1中的激光照射步骤102B 1之后的晶片1W的截面视图；图18是沿着图5中垂直于线X1-X1的线Y1-Y1所取的、在图1中的激光照射步骤102B1之后的晶片1W的截面视图；图19是图17中的区域R2的放大截面视图。
在第二实施例中，通过激光照射在晶片1W中形成两种类型的改型区域PL1、PL2(PL)。改型区域PL1主要用作对于衬底1S的分割起始点。从截面看，改型区域PL1位于衬底1S的厚度方向的中心位置。这使得在划片步骤102B4中可以整齐地对衬底1S进行划片。改型区域PL1沿着从上面看为直线的切割线CL连续延伸。改型区域PL1在衬底1S厚度方向上的尺寸D4例如为20-40微米，并且其宽度与第一实施例中的宽度大致相同。
另一方面，每个主要用作低介电常数层Lk1的分割起始点的改型区域PL2与改型区域PL1分开。当从截面看时，改型区域PL2的截面面积小于改型区域PL1的截面面积，并且部分地位于低介电常数层Lk1内部。改型区域PL2相对于低介电常数层Lk1的位置与第一实施例中的改型区域PL相对于低介电常数层Lk1的位置相同。当从上面看时，改型区域PL2是不连续的，其沿着切割线CL取虚线形状。因此，无论是从截面还是从上面看，改型区域PL2的面积都小于改型区域PL1的面积。因此，可以减小为了形成改型区域PL2而需要用激光束LB照射的面积，并且可以使激光束LB照射的热量产生最小化，并且减少或防止了低介电常数层Lk1的变色。改型区域PL2在衬底1S厚度方向上的尺寸D5例如为10-20微米，并且其宽度与第一实施例中的宽度大致相同。通过一次双焦点激光照射或通过多次单独激光照射(沿着同一条线的两次扫描)可以形成改型区域PL1、PL2。如第一实施例中那样，在对晶片1W进行冷却的同时进行激光照射以形成改型区域PL1、PL2。
图20是根据第二实施例的在图1中的划片步骤102B4之后的晶片1W的特征部分的放大截面视图.该划片工艺与参考图14和图15对第一实施例所进行的描述基本相同，除了下面的几点.在第二实施例中，如图14所示，夹具8在夹具台架10上，在箭头E的方向上将夹具8的环状物8b向下推，以使胶带8a在箭头F的方向上伸展；随着胶带8a的伸展，衬底1S以改型区域PL1作为分割起始点沿着晶片1W的厚度方向断裂，并且低介电常数层Lk1以改型区域PL2作为分割起始点断裂.因此，晶片1W被分成单独的芯片1C，其中如图20所示，衬底1S和低介电常数层Lk1被整齐地切割.
第三实施例
以下将描述根据第三实施例的激光照射步骤中所用的冷却方法的变型。
图21和图22是激光照射步骤中的晶片1W的截面视图。图21示出了在用激光束照射背表面的同时通过喷嘴25将冷却水喷洒在晶片1W的背表面上方。由此对晶片1W进行冷却，并且冷却温度例如为-40℃至5℃。
图22示出了将整个晶片1W浸没在冷却槽26中的冷却水CW中，并用激光束LB从其背表面对其进行照射。在此，将用于激光束LB的束发射器27浸没在冷却水CW中。这减少或消除了由于折射系数不同而可能发生的激光束LB的失真。冷却温度例如为-40℃至5℃。
在上述两种冷却方法中，都是在用激光束LB进行照射的期间进行冷却。然而，本发明并不限于此，还可以是在刚刚冷却晶片1W之后用激光束LB对其进行照射。图23是激光照射的后一种情况的流程图，并且图24示出了如何进行冷却。
在此，如同第一实施例那样，在将其主表面上具有胶带3a的晶片1W传送到激光划片设备的装载装置(图23中的102B1-1)之后，如图24所示，打开制冷器28的遮板28a，以将晶片1W装入制冷器28中，并将遮板28a关闭，以使晶片1W冷却期望的持续时间(图23中的102B 1-C)。冷却温度例如为-30℃至5℃。然后，在将晶片1W冷却到期望的温度之后，打开遮板28a将晶片1W取出并放置在激光划片设备的吸台5上。随后的步骤与第一实施例中相同。
第四实施例
以下将参考图25和图26描述如何根据第四实施例将芯片粘附薄膜17粘附到芯片1C的背表面上。其他的步骤与第一实施例至第三实施例中相同。
图25是在图1中的晶片安装步骤102B2之后的夹具8和晶片1W的截面视图，图26是在划片步骤102B4之后的夹具8和晶片1W的截面视图。
如同第一实施例和第二实施例那样，在完成从前端工艺100直到激光照射步骤102B1的工序之后的晶片安装步骤102B2中，制备以芯片粘附薄膜17粘附到胶带8a的粘着层8a2上的夹具8，并通过芯片粘附薄膜17将晶片1W粘附到胶带8a上。换言之，在第四实施例中，在晶片安装步骤102B2中将芯片粘附薄膜17粘合到晶片1W的背表面。芯片粘附薄膜17在伸展时足够软以便被切削，并且其例如是由聚酰亚胺树脂制成。在此之后，如图26中所示，如同在第一实施例中那样，将晶片1W划片成单独的芯片，并且也一起对芯片粘附薄膜17进行划片。由此，制备了在其背表面上具有芯片粘附薄膜17的芯片1C。
第五实施例
以下将参考图27至图29描述如何根据第五实施例在切割区域CR中的导体图形(测试焊盘1LBt等)中形成切口。其他的步骤与第一实施例至第四实施例中相同。
图27和图28是在图1中的前端工艺100之后的晶片1W的主表面的特征部分的放大平面图；图29是沿着图27和图28中的线X3-X3所取的截面视图。
在第五实施例中，在每个切割区域CR的测试焊盘1LBt和对准目标Am的顶表面上形成用于划片的切口S.当通过非接触划片将晶片1W划片成单独的芯片1C时，这些用于划片的切口S便于划片或用作分割起始点，使得可以沿着切割线CL(用虚线示出)整齐地切开切割区域CR中的焊盘1LBt和对准目标Am.
从上面看，切口S如图27中所示的直线(连续的)或如图28中所示的虚线(不连续的)那样延伸；并且从截面看，其深度位于如图29所示的焊盘1LBt和对准目标Am的厚度的中间位置。尽管在此示出的切口S的截面形状是V形，但是其并不限于这种形状并且可以是诸如U形或凹形之类的其他形状。
利用光刻胶图形作为刻蚀掩膜，通过刻蚀(湿法刻蚀或干法刻蚀)形成切口S。然而，形成切口S的方法不限于此，而是可以有所不同。例如，可以使用其中将加工工具压靠焊盘1LBt和对准目标Am的顶表面的机械方法或类似的方法，或可以使用其中沿着切割线CL投射诸如激光束或聚焦离子束之类的能量束的方法。由于不需要生成光刻胶图形，因此这些方法有助于简化制造方法。
当将切口S如图28所示的虚线那样排列时，在图2中的测试工艺101中改善了测试焊盘1LBt与探针(将放在测试焊盘1LBt上)之间的接触，从而提高了测试可靠性。
由于这些切口S，在如同第一实施例和第二实施例中那样将晶片1W划片成单独的芯片1C的步骤中，可以沿着测试焊盘1LBt和对准目标Am中的切口对测试焊盘1LBt和对准目标Am进行整齐的切割，其减少了导体碎屑，从而改善了半导体器件的可靠性。
第六实施例
以下将根据图30中的流程图，结合图31至图35来描述根据第六实施例的半导体器件制造方法。
如同第一实施例中那样，在完成了从前端工艺100直到背表面加工步骤102A3的工序之后，接着进行划片工艺102B。在划片工艺中，如同在第一实施例中那样，将晶片1W放置在激光划片设备的吸台5上(图2中的102B1-1)，并根据从IR摄像机获得的图形信息使切割线CL对准(图2中的102B1-2)。接着，如图31所示，用从激光束发生器中发出的激光束LB对晶片1W进行照射，其中光从晶片1W的背表面聚焦于晶片1W的内部，并且使光束沿着切割线CL进行相对移动(图2中的102B1-3)。结果，在晶片1W内部形成改型区域PL3。
图31是激光照射步骤中的晶片1W的特征部分的截面视图。改型区域PL3用作在划片步骤102B4中的对于衬底1S的分割起始点，并且其大致在衬底1S的厚度上的中心位置。然而，改型区域PL3没有任何部分在层间绝缘层1Li2的低介电常数层Lk1内部或与之接触。在第六实施例中，在激光照射步骤中不需要对晶片1W进行冷却。
接下来，如同第一实施例中那样，在完成了图30中的晶片安装步骤102B2和胶带剥离步骤102B3之后，如图32、图33和图34所示，在晶片1W的主表面上沿着晶片1W的切割区域CR中的切割线CL形成切口30。图32是晶片1W的一个例子的特征部分的放大平面图；图33是沿着图32中的线X4-X4所取的截面视图；图34是沿着图32中的线X5-X5所取的截面视图。
切口30用作划片步骤102B4中对于层间绝缘层1Li2的低介电常数层Lk1的分割起始点，并且其从保护层1Lp和焊盘1Lbt的顶部向下延伸直到接触到低介电常数层Lk1或部分地进入低介电常数层Lk1.由于切口30可以用作分割起始点，因此其越窄越好(例如，大约5微米).例如可以通过划片机或切割机形成切口30.作为替代，例如可以通过使用相对于表面保护层或层间绝缘层具有刻蚀选择性的硬掩膜的干法刻蚀或湿法刻蚀来形成切口30.
如上所述，在第六实施例中，由于每个切口30都与层间绝缘层1Li2的低介电常数层Lk1接触或部分地进入到层间绝缘层1Li2的低介电常数层Lk1中，所以减少或防止了诸如有缺陷形状之类的低介电常数层Lk1的断裂的较差外观的发生。此外，由于不是改型区域而是切口30用作对于低介电常数层Lk1的分割起始点，因此在分割起始点的形成中不会发生低介电常数层Lk1的变色。因此，提高了半导体器件的成品率。同样，在第六实施例中，由于在激光照射步骤中不需要对晶片1W进行冷却，因此可以缩短半导体器件制造时间。
接下来，如同第一实施例中那样，如图35所示将晶片1W划片成单独的芯片1C(图30中的102B4)。图35是在划片步骤102B4之后的晶片1W的特征部分的放大截面视图。在第六实施例中，以改型区域PL3作为分割起始点切割衬底1S，并以切口30作为分割起始点切割低介电常数层Lk1。由此，可以整齐地对晶片1W进行划片。随后的步骤与第一实施例中相同并省略对这些步骤的描述。
第七实施例
根据第七实施例，以下将描述在前端工艺中沿着切割线CL去除晶片1W的主表面的切割区域CR中的保护层1Lp以形成切口的方法。
图36是根据第七实施例在前端工艺100之后的晶片1W的特征部分的放大平面图；图37和图38分别是沿着图36中的线X6-X6和线X7-X7所取的截面视图。在第七实施例中，在前端工艺100之后，沿着切割线CL部分地去除晶片1W的主表面的切割区域CR中的保护层1Lp，并且在保护层1Lp中形成切口31。
从上面看，切口31沿着中间有孔2的切割线CL呈直线地延伸。从截面看，切口31从保护层1Lp的顶部一直延伸到接触到层间绝缘层1Li3的顶部或部分地进入到层间绝缘层1Li3中。切口31的目的是使得可以在划片步骤102B4中整齐地切割保护层1Lp。在划片步骤102B4中，在保护层1Lp中整齐地形成断裂。与用于形成孔2的刻蚀工作同时地形成切口31，这减化了该工艺。其他步骤与第一至第六实施例中相同。当将在保护层1Lp中形成切口31与第六实施例相结合时，可以比较容易地形成部分进入低介电常数层Lk1中的切口30。
用于形成接触层间绝缘层1Li2的低介电常数层Lk1或部分地进入层间绝缘层1Li2的低介电常数层Lk1的切口31的可选方法是在前端工艺100中将导线嵌入切口31中并在最后将所有嵌入导线从切口31中去除。在这种情况下，切口31在划片步骤102B4中用作对于低介电常数层Lk1的分割起始点。这确保了在低介电常数层Lk1中整齐地形成断裂。
用于形成改型区域的激光照射步骤与第六实施例中相同。换言之，在激光照射步骤中形成用作对于衬底1S的分割起始点的改型区域PL3。因此，在激光照射期间不会发生低介电常数层Lk1的变色。因此提高了半导体器件的成品率。
至此，已经参考本发明人所作出的本发明的优选实施例对本发明进行了具体的说明。然而，本发明并不限于此，并且很显然，在不偏离本发明的精神和范围的情况下可以以其他的各种方式来实施本发明。
虽然上述说明假定将本发明应用于半导体器件的制造，即本发明所适合的应用领域，但是本发明的应用领域并不限于此，而是可以应用于包括微机械制造的其他各种领域.
本发明可以应用于半导体器件的制造。

Claims (3)

1.一种半导体器件制造方法，包括以下步骤：
(a)制备晶片，所述晶片具有半导体衬底和布线层，所述半导体衬底具有主表面和与所述主表面相对的背表面，所述布线层具有形成在所述半导体衬底的主表面上的低介电常数层和层间绝缘层；
(b)通过从所述晶片的背表面沿着所述晶片的每个芯片的切割区域，将激光束聚焦在所述晶片的内部，形成改型区域；以及
(c)在所述步骤(b)之后，基于所述改型区域，将所述晶片分割成多个半导体芯片，
其中在所述步骤(b)中，对所述晶片进行冷却；
其中所述层间绝缘层形成在所述半导体衬底的主表面上；
其中所述低介电常数层形成在所述层间绝缘层上；以及
其中在所述步骤(b)中，将所述激光束照射到所述晶片，使得通过所述激光束照射到所述晶片而形成的所述改型区域与所述低介电常数层的部分、所述层间绝缘层的部分以及所述半导体衬底的部分接触。
2.根据权利要求1所述的半导体器件制造方法，其中所述改型区域是通过对所述晶片的内部进行加热和熔化而形成。
3.根据权利要求1所述的半导体器件制造方法，其中所述改型区域形成为从所述半导体衬底的内部、在所述半导体衬底的厚度方向上延伸，并使得与所述低介电常数层的部分接触。
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