CN1866340B - Active matrix display device, method for driving the same, and electronic device - Google Patents

Active matrix display device, method for driving the same, and electronic device Download PDF

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Publication number
CN1866340B
CN1866340B CN2006100824416A CN200610082441A CN1866340B CN 1866340 B CN1866340 B CN 1866340B CN 2006100824416 A CN2006100824416 A CN 2006100824416A CN 200610082441 A CN200610082441 A CN 200610082441A CN 1866340 B CN1866340 B CN 1866340B
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signal
pixel
pixel column
circuit
display device
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CN2006100824416A
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CN1866340A (en
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木村肇
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

An object of the invention is to provide a display device which can reduce the number of times signal writing to a pixel is carried out and power consumption. A display device which can reduce the number of times signal writing to a pixel is carried out and power consumption can be provided. According to an active matrix display device of the invention, in the case a signal to be written to a pixel row is identical with a signal stored in the pixel row, the scan line driver circuit does not output a selecting pulse to a scan line corresponding to the pixel row, and the signal line driver circuit makes the signal lines in a floating state or keeps without changing the state of the signal line from the previous state.

Description

Actire matrix display device and driving method thereof and electronic equipment
Technical field
The present invention relates to have through transistor controls be transported to load electric current function semiconductor devices with comprise pixel and the display device of signal line drive circuit and scan line driver circuit thereof that is formed with the pixel of its brightness through the display element of the current drives of signal change, is formed with the display element of the driven that its brightness changes through voltage.The present invention also relates to their driving method.The invention further relates to the electronic equipment that in the display part, comprises this display device.
Background technology
In recent years, so-called self-emitting display spare has caused showing great attention to of people, and it uses the display element by for example light emitting diode (LED) to form pixel.As the display element that is used for such self-emitting display spare, Organic Light Emitting Diode (being also referred to as OLED, organic EL, electroluminescence (EL) element etc.) has caused people's attention, and they have been used to EL display etc.Because such as the display element of OLED is self luminous, therefore, it has many advantages with respect to LCD, for example higher pixel visibility, does not require backlight, higher response speed.Notice that the brightness of display element is flowed into the current value of this display element and controls.
As driving such display device, have digital gray scale method and analog gray scale method to express the method for gray scale.The analog gray scale method comprises the method for controlling the fluorescent lifetime of display element with the method for the luminous intensity of simulated mode control display element with simulated mode.As the analog gray scale method, often use method with the luminous intensity of analog form control display element.Yet, receiving the influence of characteristic variations of the thin film transistor (TFT) (hereinafter is also referred to as TFT) of each pixel easily with the method for analog form control luminous intensity, the characteristic variations of TFT also causes the variation of the brightness of each pixel.On the other hand, in the digital gray scale method, through expressing gray scale with the connection/cut-out of digital form control display element.Under the situation of digital gray scale method, the brightness uniformity of each pixel is very good.Yet, have only two states, promptly therefore luminance and non-luminance only can express two gray levels.Therefore, use another method to attempt to realize that multi-stage grey scale shows through combination.As the multi-stage grey scale technique for displaying, the light-emitting area that wherein weighting has been arranged and selected pixel with the area gray level method carrying out gray scale and show with weighting wherein and select fluorescent lifetime to carry out the time gray level method of gray scale demonstration.Under the situation of digital gray scale method, use also is suitable for obtaining the more time gray level method of high definition usually.
The open No.784615 of (references 1) Jap.P.
At this, can realize the improvement of sharpness through the time gray level method in the use digital gray scale method.Yet along with the raising of sharpness, the quantity of pixel increases.Therefore, the pixel quantity that is written into signal also increases.
In addition, the number needs of subframe will increase to carry out senior gray scale demonstration.Therefore, the number of times of signal being write in the pixel increases.
Therefore, along with the raising of sharpness and gray scale display level, the number of times (it is relevant with signal writing operation) of implementing charging and discharge also increases.The power consumption increase becomes problem.
Summary of the invention
Based on above-mentioned consideration, an object of the present invention is to provide a kind of can the minimizing signal is written to the number of times of pixel and the display device of power consumption.
Display device of the present invention is included in the signal that is written to pixel the device that stops when identical with the signal that is written to this pixel the signal input of this pixel.
In other words, do not selecting this pixel column when identical to being used for the signal that is written to this pixel column with the signal of the pixel that is performed the pixel column that writes.In other words, do not select the signal of pixel to continue to be input to the sweep trace that is connected with this pixel column, perhaps this sweep trace is placed quick condition.
Display device of the present invention comprises the signal line drive circuit of pixel portion that wherein a plurality of pixels arrange with matrix-style with respect to line direction and column direction, and non-luminous signal luminous to signal wire input control pixel and selects to be written into the scan line driver circuit of the pixel of signal; Wherein each pixel comprises that storage is written to the device of signal wherein, and scan line driver circuit is included in the signal that is written to pixel and stops the device that the signal to this pixel writes when identical with signal in being stored in this pixel.
Display device of the present invention comprises the signal line drive circuit of pixel portion that wherein a plurality of pixels arrange with matrix-style with respect to line direction and column direction, and non-luminous signal luminous to signal wire input control pixel and selects to be written into the scan line driver circuit of the pixel of signal; Wherein each pixel comprises that storage is written to the device of signal wherein, and scan line driver circuit is included in the signal that is written to pixel the device that stops to select this pixel when identical with signal in being stored in this pixel.
Display device of the present invention comprises the signal line drive circuit of pixel portion that wherein a plurality of pixels arrange with matrix-style with respect to line direction and column direction, and non-luminous signal luminous to signal wire input control pixel and selects to be written into the scan line driver circuit of the pixel column of signal; Wherein each pixel comprises that storage is written to the device of signal wherein, and scan line driver circuit is included in the signal that is written to pixel column and stops the device that the signal to this pixel column writes when identical with signal in being stored in this pixel column.
Display device of the present invention comprises the signal line drive circuit of pixel portion that wherein a plurality of pixels arrange with matrix-style with respect to line direction and column direction, and non-luminous signal luminous to signal wire input control pixel and selects to be written into the scan line driver circuit of the pixel column of signal; Wherein each pixel comprises that storage is written to the device of signal wherein, and scan line driver circuit is included in the signal that is written to pixel column the device that stops to select this pixel column when identical with signal in being stored in this pixel column.
Display device of the present invention comprises the signal line drive circuit of pixel portion that wherein a plurality of pixels arrange with matrix-style with respect to line direction and column direction, and non-luminous vision signal luminous to signal wire input control pixel and selects to be written into the scan line driver circuit of the pixel column of vision signal; Wherein each pixel comprises that storage is written to the device of vision signal wherein, and scan line driver circuit is included in the vision signal that is written to pixel column and stops the device that the vision signal to this pixel column writes when identical with vision signal in being stored in this pixel column.
Display device of the present invention comprises the signal line drive circuit of pixel portion that wherein a plurality of pixels arrange with matrix-style with respect to line direction and column direction, and non-luminous vision signal luminous to signal wire input control pixel and selects to be written into the scan line driver circuit of the pixel column of vision signal; Wherein each pixel comprises that storage is written to the device of vision signal wherein, and scan line driver circuit is included in the vision signal that is written to pixel column the device that stops to select this pixel column when identical with vision signal in being stored in this pixel column.
Display device of the present invention comprise pixel portion that wherein a plurality of pixels arrange with matrix-style with respect to line direction and column direction, and non-luminous vision signal luminous to signal wire input control pixel the signal line drive circuit, select to be written into vision signal pixel column scan line driver circuit and transmit signal to the controller of signal line drive circuit and scan line driver circuit; Wherein each pixel comprises that storage is written to the device of vision signal wherein; Scan line driver circuit is included in the vision signal that is written to pixel column and stops the device that the vision signal to this pixel column writes when identical with vision signal in being stored in this pixel column, and controller is included in the vision signal that will be written to this pixel column and stops the device to signal line drive circuit incoming video signal when identical with the vision signal of in pixel column, storing.
Display device of the present invention is a kind of through being divided into the display device of expressing gray scale during a plurality of subframes an image duration; Comprise the signal line drive circuit of pixel portion that wherein a plurality of pixels arrange with matrix-style with respect to line direction and column direction, and non-luminous digital video signal luminous and select to be written into the scan line driver circuit of the pixel column of digital video signal signal wire input control pixel; Wherein each pixel comprises that storage is written to the device of digital video signal wherein, and scan line driver circuit comprises and stops the device that the digital video signal to this pixel column writes when the digital video signal of this pixel column is identical during the digital video signal of pixel column and the subframe formerly with during a certain subframe, being written to.
Display device of the present invention is a kind of through being divided into the display device of expressing gray scale during a plurality of subframes an image duration; Comprise the signal line drive circuit of pixel portion that wherein a plurality of pixels arrange with matrix-style with respect to line direction and column direction, and non-luminous digital video signal luminous and select to be written into the scan line driver circuit of the pixel column of digital video signal signal wire input control pixel; Wherein each pixel comprises that storage is written to the device of digital video signal wherein, and scan line driver circuit comprises the device that stops to select this pixel column when the digital video signal of this pixel column is identical during the digital video signal of pixel column and the subframe formerly with during a certain subframe, being written to.
Display device of the present invention is a kind of through being divided into the display device of expressing gray scale during a plurality of subframes an image duration; Comprise pixel portion that wherein a plurality of pixels arrange with matrix-style with respect to line direction and column direction, and non-luminous digital video signal luminous to signal wire input control pixel the signal line drive circuit, select to be written into digital video signal pixel column scan line driver circuit and transmit signal to the controller of signal line drive circuit and scan line driver circuit; Wherein each pixel comprises that storage is written to the device of digital video signal wherein; Scan line driver circuit comprises and stops the device that the digital video signal to this pixel column writes when the digital video signal of this pixel column is identical during the digital video signal of pixel column and the subframe formerly with during a certain subframe, being written to, and controller is included in the digital video signal that is written to pixel column and stops the device to signal line drive circuit input digital video signal when identical with digital video signal in being stored in this pixel column.
Display device of the present invention comprises scan line driver circuit, signal line drive circuit, follow the pixel portion that a plurality of sweep traces, a plurality of signal wires that extend along column direction from the signal line drive circuit and wherein a plurality of pixel that direction extends from scan line driver circuit are arranged with matrix-style with respect to a plurality of sweep traces and a plurality of signal wire; Wherein each pixel comprises that storage is written to the device of signal wherein; Scan line driver circuit comprises output control circuit, and this output control circuit is used to cancel the signal of selecting this pixel column when the signal that will be written to pixel column is identical with signal in being stored in this pixel column, for the sweep trace input that is connected to this pixel column.
Display device of the present invention comprises scan line driver circuit, signal line drive circuit, follow the pixel portion that a plurality of sweep traces, a plurality of signal wires that extend along column direction from the signal line drive circuit and wherein a plurality of pixel that direction extends from scan line driver circuit are arranged with matrix-style with respect to a plurality of sweep traces and a plurality of signal wire; Wherein each pixel comprises that storage is written to the device of signal wherein; Scan line driver circuit comprises output control circuit, and this output control circuit will be connected to this pixel column when the signal that will be written to pixel column is identical with signal in being stored in this pixel column sweep trace places quick condition.
Display device of the present invention comprises the signal line drive circuit of pixel portion that wherein a plurality of pixels arrange with matrix-style with respect to line direction and column direction, and non-luminous vision signal luminous to signal wire input control pixel and selects to be written into the scan line driver circuit of the pixel column of vision signal; Wherein each pixel comprises that storage is written to the device of vision signal wherein; Scan line driver circuit comprises impulse output circuit and output control circuit; This impulse output circuit is input as the output control circuit input and is used for definite pulse of selecting the timing of pixel column, and whether the output control circuit gating pulse is exported to the sweep trace that is connected to this pixel column.
Display device of the present invention comprises the signal line drive circuit of pixel portion that wherein a plurality of pixels arrange with matrix-style with respect to line direction and column direction, and non-luminous vision signal luminous to signal wire input control pixel and selects to be written into the scan line driver circuit of the pixel column of vision signal; Wherein each pixel comprises that storage is written to the device of vision signal wherein; Scan line driver circuit comprises impulse output circuit and pulse output control circuit; The signal line drive circuit comprises the signal output control circuit; Input is used for definite pulse of selecting the timing of pixel column to this impulse output circuit to output control circuit; Whether pulse output control circuit gating pulse exports the sweep trace that is connected to this pixel column to, and the signal output control circuit does not place quick condition with signal wire when pulse is exported.
In addition, hereinafter is described the concrete structure of the method that drives display device of the present invention.
First kind of structure is such display device, will be performed under the data of vision signal of the pixel column that the signal to pixel the writes situation identical with the data of the pixel that writes pixel column wherein this display device in during a certain subframe of an image duration and be the sweep trace input and be used for preventing that scan line driver circuit from selecting the signal of this pixel column in horizontal period.
Second kind of structure is such display device, will be performed that this display device places quick condition with the sweep trace of pixel column under the data of vision signal of the pixel column that the signal to pixel the writes situation identical with the data of the pixel that writes pixel column wherein in horizontal period in during a certain subframe of an image duration.
The third structure is such display device, will be performed under the data of vision signal of the pixel column that the signal to pixel the writes situation identical with the data of the pixel that writes pixel column wherein this display device input in during a certain subframe of an image duration and be used for preventing that scan line driver circuit from selecting the signal of this pixel column and setting fixing current potential for all signal wires in the write time at this pixel column in horizontal period.
The 4th kind of structure is such display device, will be performed that this display device places the sweep trace of pixel column quick condition and sets fixing current potential for all signal wires in the write time of this pixel column in horizontal period under the data of vision signal of the pixel column that the signal to pixel the writes situation identical with the data of the pixel that writes pixel column wherein in during a certain subframe of an image duration.
The 5th kind of structure is such display device, will be performed under the data of vision signal of the pixel column that the signal to pixel the writes situation identical with the data of the pixel that writes pixel column wherein this display device input in during a certain subframe of an image duration and be used for preventing that scan line driver circuit from selecting the signal of this pixel column and in the write time at this pixel column all signal wires being placed quick condition in horizontal period.
The 6th kind of structure is such display device, will be performed that this display device places the sweep trace of pixel column quick condition and in the write time of this pixel column all signal wires placed quick condition in horizontal period under the data of vision signal of the pixel column that the signal to pixel the writes situation identical with the data of the pixel that writes pixel column wherein in during a certain subframe of an image duration.
The 7th kind of structure is such display device, is used under the identical situation of the data of pixel of pixel column this display device input in will being performed in during a certain subframe of an image duration during data and the subframe in the end of vision signal of the pixel column that the signal to pixel writes and is used to prevent that scan line driver circuit from selecting the signal of this pixel column in horizontal period.
The 8th kind of structure is such display device, is used for this display device under the identical situation of the data of vision signal of pixel column in will being performed in during a certain subframe of an image duration during data and the last subframe of vision signal of the pixel column that the signal to pixel writes and in horizontal period the sweep trace of pixel column placed quick condition.
The 9th kind of structure is such display device, is used under the identical situation of the data of vision signal of pixel column this display device input in will being performed in during a certain subframe of an image duration during data and the last subframe of vision signal of the pixel column that the signal to pixel writes and is used for preventing that scan line driver circuit from selecting the signal of this pixel column and setting fixing current potential for all signal wires in the write time of pixel column in horizontal period.
The tenth kind of structure is such display device, is used for that this display device places quick condition and sets fixing current potential in the write time of pixel column for all signal wires at the sweep trace of horizontal period with pixel column under the identical situation of the data of vision signal of pixel column in will being performed in during a certain subframe of an image duration during data and the last subframe of vision signal of the pixel column that the signal to pixel writes.
The 11 kind of structure is such display device, is used for this display device input under the identical situation of the data of vision signal of pixel column in will being performed in during a certain subframe of an image duration during data and the last subframe of vision signal of the pixel column that the signal to pixel writes and is used for preventing that scan line driver circuit from selecting the signal of this pixel column and during the writing of pixel column, all signal wires being placed quick condition in horizontal period.
The 12 kind of structure is such display device, is used for that this display device places quick condition and in the write time of pixel column all signal wires placed quick condition at the sweep trace of horizontal period with pixel column under the identical situation of the data of vision signal of single row in will being performed in during a certain subframe of an image duration during data and the last subframe of vision signal of the pixel column that the signal to pixel writes.
Notice that the switch that will describe in this manual can be various types of, an instance is electric switch, mechanical switch etc.In other words, can use can Control current any switch, it is had no particular limits.Can use various switches.For example, switch can be transistor, diode (transistor that connects such as PN diode, PIN diode, schottky diode or diode mode), the perhaps logical circuit of its combination.Using under the situation of transistor as switch, transistor uses as just switch.Therefore, transistorized polarity (conductivity type) is had no particular limits.Yet, under the situation of the low cut-off current of hope, it is desirable to use the transistor of polarity with low cut-off current.As the transistor with low cut-off current, having the transistor in LDD district, the transistor with multi grid etc. can use.In addition; As the transistor of switching manipulation the current potential of its source terminal near the state of low potential side power supply (such as Vss, GND or 0V) under during operation; It is desirable to use the n channel transistor; Yet the current potential of its source terminal near the state of hot side power supply (such as Vdd) under during operation, it is desirable to use the p channel transistor.This is because can increase the absolute value of gate source voltage, so transistor is easily as switching manipulation.Notice that switch can be to use the CMOS type of n channel transistor and p channel transistor.If switch is the CMOS type, though then at condition changing for example the voltage (in other words, the input voltage of switch) through switch output it still can correctly be operated when being higher or lower than output voltage.
Notice that in the present invention, term " connection " means the situation and the direct-connected situation of electrical connection.Therefore, in structure disclosed by the invention, can realize that other element (such as switch, transistor, capacitor, inductor, resistor or diode) that is electrically connected can insert with predetermined connection.Replacedly, can be in this configuration direct link and needn't insert other element betwixt.Note, only therein directly the situation (situation that does not comprise electrical connection) of link and inserting betwixt other element of realizing being electrically connected be called as " directly connecting ".Should also be noted that term " electrical connection " means situation and the direct-connected two kinds of situation of parts that parts are electrically connected.
Notice that the display element that in pixel, is provided with is not limited to specific a kind of.Instance as the display element that in pixel, is provided with; The display media that can use contrast wherein to change through electromagnetic action is such as EL element (organic EL, inorganic EL element or comprise organic material and the EL element of inorganic material), electronic emission element, liquid crystal cell, electronic ink, diffractive-optical element, arresting element, DMD (DMD), piezoelectric element or CNT.Note, use the instance of display device of above-mentioned display element following: the EL display, as the EL panel display device that uses EL element; Field Emission Display (FED) or SED flat-panel monitor (SED: surface conduction electron emitter display), as the display device that uses electronic emission element; LCD is as the liquid crystal flat panel display spare that uses liquid crystal cell; Electronic Paper is as the digital paper display device that uses electronic ink; Grid light valve (GLV) display is as the display device that uses diffractive-optical element; Plasma scope is as PDP (plasma display panel) display that uses arresting element; Digital light is handled (DLP) display device, as the dmd panel display device that uses DMD; The piezoelectric ceramics display is as the display device that uses piezoelectric element; Nanometer emission display (NED) is as the display device that uses CNT; Or the like.Notice that display element of the present invention is suitable for gray level method or comprise pixel with memory character display device of (in pixel, comprise SRAM, DRAM etc. or comprise the memory cell element of storage signal (can)) service time.
Note,, can use various types of transistors in the present invention as transistor.Therefore, to not restriction of transistorized kind applicatory.Therefore, can use following transistor: use with amorphous silicon film or polysilicon film as the thin film transistor (TFT) (TFT) of the non-single crystal semiconductor film of representative, use MOS transistor that Semiconductor substrate or SOI substrate form, junction transistor, bipolar transistor, use compound semiconductor (such as ZnO or InGaZnO) transistor, use transistor or other transistor of organic semiconductor or CNT.Notice that non-single crystal semiconductor film can comprise hydrogen or halogen.In addition, transistor can be positioned on the various substrates, the type of substrate is not limited to specific a kind of.Therefore, transistor for example can be positioned on single crystalline substrate, SOI substrate, glass substrate, quartz substrate, plastic, paper substrate, viscose paper substrate, the stone substrate etc.In addition, transistor can be formed on a certain substrate, can shift and be positioned on another substrate subsequently.
Note, can use various types of transistorized structures, it is not limited to specific a kind of.For example, can use multi-gate structure with two or more grids.When using multi-gate structure; Can reduce cut-off current; Transistorized voltage endurance capability can be increased improving reliability, and when transistor is worked in the saturation region, can change by rejection characteristic, even because drain electrode-source current can not change too big yet when drain electrode-source voltage changes.Replacedly, gate electrode can be provided on the raceway groove with under.Wherein gate electrode be provided on the raceway groove with under structure allow to increase channel region; Therefore, current value can increase and form easily dissipation layer to increase the S value.In addition, gate electrode may be provided on the raceway groove or raceway groove under.Cross structure or reverse interleaved structure can adopt.Channel region can be divided into a plurality of districts, and these districts all walk abreast or serial ground connects.Source electrode or drain electrode can be overlapping with raceway groove (or its part).Wherein the overlapping structure of source electrode or drain electrode and raceway groove (or its part) can prevent that electric charge is accumulated on the part of raceway groove, and this electric charge accumulation possibly cause unsettled operation.In addition, the LDD district can be provided.When the LDD district is provided; Can reduce cut-off current; Can increase transistorized voltage endurance capability improving reliability, and variation that can rejection characteristic when transistor is operated in the saturation region, even because drain electrode-source current still changes not quite when drain electrode-source voltage changes.
Notice that as indicated above, transistor of the present invention can be any kind and can be formed on the substrate of any kind.Therefore, all circuit can be formed on glass substrate, plastic, single crystalline substrate, SOI substrate or any other the substrate.Replacedly, a part of circuit can be formed on the substrate, and another part circuit can be formed on another substrate.In other words, all circuit needn't be formed on same substrate.For example, a part of circuit is formed on the glass substrate of using TFT, and another part circuit can be used as the IC chip and is formed on the single crystalline substrate, and the IC chip can be connected on the glass substrate through COG (glass top chip).Replacedly, the IC chip can or use printed circuit board (PCB) to be connected to glass substrate through TAB (carrier band weldering automatically).
Notice that transistor can be to have at least three terminals element of (comprising grid, drain electrode and source electrode).Grid means all or part of gate electrode and gate wirings (being also referred to as gate line, signal line etc.).Gate electrode means semi-conductive a part of conducting film that covering has wherein formed channel region, LDD (lightly doped drain electrode) district etc., and is inserted with gate insulating film betwixt.Gate wirings means the gate electrode that connects pixel or gate electrode is connected to the distribution of another distribution.
Yet, also had the part of gate electrode and two kinds of effects of gate wirings.This part can be called as gate electrode or gate wirings.In other words, in some zone, between gate electrode and gate wirings, there is not boundary clearly.For example, under the overlapping situation of the gate wirings of channel region and extension, gate wirings and two kinds of effects of gate electrode are played in this zone.Therefore, this zone can be called as gate electrode or gate wirings.
In addition, by also being called as gate electrode with gate electrode identical materials zone that form and that be connected to gate electrode.Similarly, by also being called as gate wirings with gate wirings identical materials zone that form and that be connected to gate wirings.Say on the stricti jurise, possibly have so a kind of situation: wherein this zone and channel region are not overlapping or do not have a function that a gate electrode is connected to another gate electrode.Yet some zones are by forming with gate electrode or gate wirings identical materials and being connected to gate electrode or gate wirings according to making surplus etc.Therefore, this zone can be called as gate electrode or gate wirings.
For example, in multi-gated transistor, a transistorized gate electrode is usually through being connected to another transistorized gate electrode with the conducting film with the formation of gate electrode identical materials.This zone can be called as gate wirings, because it is connected to each other gate electrode, perhaps it can be called as gate electrode, because multi-gated transistor can be counted as a transistor.In other words, can be called as gate electrode or gate wirings by the zone that forms with gate electrode or gate wirings identical materials and be connected to wherein.In addition, its part of conducting film that for example connects gate electrode and gate wirings can be called as gate electrode or gate wirings.
Notice that gate terminal means the part of gate electrode area or is electrically connected to the part in the zone of gate electrode.
Notice that source electrode means all or part of source area, source electrode and source electrode distribution (also being called as source electrode line, source signal line etc.).Source area means the p-type impurity (such as boron and gallium) that comprises high concentration or the semiconductor region of n-type impurity (such as phosphorus and arsenic).Therefore, source area does not comprise the p-type impurity that comprises low concentration or the zone of n-type impurity, promptly so-called LDD (lightly doped drain electrode) district.Source electrode mean by with the part of the material material different conductive layer that form and that be electrically connected to source area of source area.Source electrode comprises source area in some cases.The source electrode distribution means the source electrode that connects pixel or source electrode is connected to the distribution of another distribution.
Yet, also had the part of source electrode electrode and two kinds of effects of source electrode distribution.This part is called as source electrode or source electrode distribution.In other words, in some zone, between source electrode and source electrode distribution, there is not boundary clearly.For example, when the source electrode distribution of source area and extension was overlapping, source electrode distribution and two kinds of effects of source electrode were played in this zone.Therefore, this zone can be called as source electrode or source electrode distribution.
In addition, perhaps source electrode part connected to one another also can be called as source electrode by the zone that forms with the source electrode identical materials and be connected to source electrode.In addition, also can be called as source electrode with the overlapping part of source area.Similarly, by also being called as the source electrode distribution with source electrode distribution identical materials zone that form and that be connected to the source electrode distribution.Say on the stricti jurise, possibly have so a kind of situation: wherein this zone does not have the function that a source electrode is connected to another source electrode.Yet some zones are by forming with source electrode or source electrode distribution identical materials and being connected to source electrode or source electrode distribution according to making surplus etc.Therefore, this zone can be called as source electrode or source electrode distribution.
In addition, for example, the conducting film part that connects source electrode and source electrode distribution can be called as source electrode or source electrode distribution.
Notice that source terminal means source area, the source electrode of a part or is electrically connected to the zone of source electrode.
Description to source electrode is applicable to drain electrode.
In the present invention, term " on (on) " " is formed on the something " situation about directly contacting with something of being not limited to such as phrase, and comprises not the directly situation of contact, promptly wherein inserts the situation of another thing.Therefore, phrase " layer B be formed on layer A " comprises that layer B is formed directly into situation on layer A and is formed directly on layer A with another layer (such as a layer C and a layer D) wherein and a layer B is formed directly into the situation on this another layer.Identical situation is applied to term " top (over) ", and this term is not limited to direct situation about contacting with something, comprises that also another thing inserts situation wherein.Therefore, phrase " layer B is formed on layer A top " comprises that layer B is formed directly into situation on layer A and is formed directly on layer A with another layer (such as a layer C and a layer D) wherein and a layer B is formed directly into the situation on this another layer.Notice that identical situation is applicable to term " under (under) " or term " below (below) ", these terms comprise situation about directly contacting with something and situation about directly not contacting.
In the present invention, a pixel means an element can controlling brightness.As an example, a pixel means a kind of color-element (colour cell), and it expresses brightness.Therefore, comprising that (under the situation of the chromatic display of R (red), G (green) and B (indigo plant) color-element, the least unit of image is made up of three pixels: R pixel, G pixel and B pixel.Notice that the quantity of color-element is not limited to three, can use more color-element.White), the RGB of, cyan yellow or magenta etc. for example, can adopt RGBW (W: to wherein increasing.As another instance, when using the brightness of a color-element of a plurality of Region control, one in these zones is called as a pixel.Under the situation of carrying out the area gray scale, (use the brightness of a plurality of each color-element of Region control in this case, and gray scale is expressed through all zones), pixel means of a plurality of zones of being used for controlling brightness.In this case, a color-element is made up of a plurality of pixels.In addition, in this case, each pixel can be of different sizes area, and this has contribution to display.In addition, slight various signals can flow to a plurality of zones of the brightness of a color-element of control, promptly constitutes a plurality of pixels of a color-element, has increased the visual angle thus.
In the present invention, pixel can be arranged (array) with matrix form.Phrase " pixel is arranged (array) with matrix form " comprises the situation that pixel is arranged with the strip grid grid pattern.It also comprises wherein three kinds of color-element, and (point that for example, RGB) is used to panchromatic demonstration and three kinds of color-element is with the δ pattern or visit a situation of (Bayer) arranged in patterns.For each point of color-element, the size of luminous zone can be all different.
Notice that term in this manual " semiconductor devices " means the device that comprises the circuit that contains semiconductor element (transistor or diode).
Can provide a kind of can the minimizing that pixel is implemented the number of times that signal writes and the display device of power consumption.
In other words, through reducing charging and discharge time in the process that writes at the signal to pixel, display device of the present invention can reduce power consumption.
Description of drawings
Accompanying drawing 1 is an accompanying drawing of explaining display device of the present invention.
Accompanying drawing 2 is accompanying drawings of explaining the primary structure of display device of the present invention.
Accompanying drawing 3 is accompanying drawings of explaining display device of the present invention.
Accompanying drawing 4 is accompanying drawings of explaining display device of the present invention.
Accompanying drawing 5A to 5C is the accompanying drawing of explaining applicable to the scan line driver circuit of display device of the present invention.
Accompanying drawing 6A and 6B are the accompanying drawings of explaining applicable to the scan line driver circuit of display device of the present invention.
Accompanying drawing 7A and 7B are the accompanying drawings of explaining applicable to the scan line driver circuit of display device of the present invention.
Accompanying drawing 8A and 8B are the accompanying drawings of explaining applicable to the signal line drive circuit of display device of the present invention.
Accompanying drawing 9A and 9B are the accompanying drawings of explaining applicable to the signal line drive circuit of display device of the present invention.
Accompanying drawing 10 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 11A to 11D is the accompanying drawing of explaining applicable to the scan line driver circuit of display device of the present invention.
Accompanying drawing 12A and 12B are the accompanying drawings of explaining the method be used to drive display device of the present invention.
Accompanying drawing 13 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 14 is accompanying drawings of explaining the method be used to drive display device of the present invention.
Accompanying drawing 15 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 16 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 17 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 18 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 19 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 20A and 20B are the accompanying drawings of explaining the method be used to drive display device of the present invention.
Accompanying drawing 21 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 22A and 22B are the accompanying drawings of explaining the method be used to drive display device of the present invention.
Accompanying drawing 23 is accompanying drawings of explaining the primary structure of display device of the present invention.
Accompanying drawing 24 is accompanying drawings of explaining display device of the present invention.
Accompanying drawing 25 is accompanying drawings of explaining the primary structure of display device of the present invention.
Accompanying drawing 26A to 26H is an accompanying drawing of explaining the electronic equipment that can use display device of the present invention.
Accompanying drawing 27 is accompanying drawings of explaining the method be used to drive display device of the present invention.
Accompanying drawing 28 is accompanying drawings of explaining the method be used to drive display device of the present invention.
Accompanying drawing 29 is accompanying drawings of explaining the method be used to drive display device of the present invention.
Accompanying drawing 30A and 30B are the accompanying drawings of explaining the method be used to drive display device of the present invention.
Accompanying drawing 31A to 31C is an accompanying drawing of explaining the method be used to drive display device of the present invention.
Accompanying drawing 32 is accompanying drawings of explaining the method be used to drive display device of the present invention.
Accompanying drawing 33 is explanation accompanying drawings applicable to the operation of the scan line driver circuit of display device of the present invention.
Accompanying drawing 34 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 35A and 35B are the accompanying drawings of explaining applicable to the scan line driver circuit of display device of the present invention.
Accompanying drawing 36A and 36B are the accompanying drawings of explaining display board of the present invention.
Accompanying drawing 37 is accompanying drawings of explaining the method be used to drive display device of the present invention.
Accompanying drawing 38 is the accompanying drawings that show the instance of confirming circuit.
Accompanying drawing 39 is accompanying drawings of explaining the operation of confirming circuit.
Accompanying drawing 40 is accompanying drawings of explaining the operation of confirming circuit.
Accompanying drawing 41A and 41B are the accompanying drawings of explaining display board of the present invention.
Accompanying drawing 42A and 42B are the accompanying drawings of explaining display board of the present invention.
Accompanying drawing 43A and 43B are the accompanying drawings of explaining display board of the present invention.
Accompanying drawing 44A and 44B are the accompanying drawings of explaining applicable to the light-emitting component of display device of the present invention.
Accompanying drawing 45A to 45C is an accompanying drawing of explaining display board of the present invention.
Accompanying drawing 46 is accompanying drawings of explaining display board of the present invention.
Accompanying drawing 47 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 48 is accompanying drawings of explaining the electronic equipment that can use display device of the present invention.
Accompanying drawing 49 is accompanying drawings of explaining the electronic equipment that can use display device of the present invention.
Accompanying drawing 50 is accompanying drawings of explaining the electronic equipment that can use display device of the present invention.
Accompanying drawing 51 is accompanying drawings of explaining applicable to the scan line driver circuit of display device of the present invention.
Accompanying drawing 52 is accompanying drawings of explaining applicable to the signal line drive circuit of display device of the present invention.
Accompanying drawing 53 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 54 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 55 is accompanying drawings of explaining display device of the present invention.
Accompanying drawing 56 is accompanying drawings of explaining display device of the present invention.
Accompanying drawing 57 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 58A and 58B are the accompanying drawing of explanation applicable to the operation of the dot structure of display device of the present invention.
Accompanying drawing 59 is explanation accompanying drawings applicable to the operation of the dot structure of display device of the present invention.
Accompanying drawing 60 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 61 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 62 is explanation accompanying drawings applicable to the operation of the dot structure of display device of the present invention.
Accompanying drawing 63A to 63D is the accompanying drawing of explanation applicable to the operation of the dot structure of display device of the present invention.
Accompanying drawing 64 is accompanying drawings of explaining display device of the present invention.
Accompanying drawing 65A and 65B are the accompanying drawings of explaining the method be used to drive display device of the present invention.
Accompanying drawing 66A and 66B are the accompanying drawings of explaining the method be used to drive display device of the present invention.
Accompanying drawing 67 is accompanying drawings of explaining applicable to the dot structure of display device of the present invention.
Accompanying drawing 68 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 69 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 70 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 71 is accompanying drawings of explaining display device of the present invention.
Accompanying drawing 72 is accompanying drawings of explaining display device of the present invention.
Accompanying drawing 73 is the accompanying drawings that show the instance of confirming circuit.
Accompanying drawing 74 is accompanying drawings of explaining display device of the present invention.
Accompanying drawing 75 is accompanying drawings of explaining display device of the present invention.
Accompanying drawing 76A to 76C is the accompanying drawing of explaining in display packing of the present invention.
Accompanying drawing 77A and 77B are the accompanying drawings of explaining applicable to the signal line drive circuit of display device of the present invention.
Accompanying drawing 78A and 78B are the accompanying drawings of explaining applicable to the signal line drive circuit of display device of the present invention.
Accompanying drawing 79 is accompanying drawings of explaining display device of the present invention.
Accompanying drawing 80 is accompanying drawings of explaining display board of the present invention.
Accompanying drawing 81 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 82 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 83 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 84 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 85 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 86 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 87 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 88 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 89 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 90 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 91 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 92 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 93 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 94 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 95 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 96 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 97 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 98 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 99 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 100 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 101 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 102 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 103 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Accompanying drawing 104 is explanation accompanying drawings applicable to the operation of the signal line drive circuit of display device of the present invention.
Embodiment
After this, with reference to explained embodiments of the invention pattern.Yet the present invention is not limited to following description.Can carry out various changes to pattern of the present invention and details as it is readily appreciated by a person skilled in the art that under the premise without departing from the spirit and scope of the present invention.Therefore, the present invention should not be interpreted as the description that is limited to following embodiment pattern.
Display device of the present invention comprises scan line driver circuit, signal line drive circuit and wherein a plurality of pixel with the pixel portion of matrix-style with respect to sweep trace and signal wire arrangement, and each pixel comprises that storage writes the device of signal wherein.
The signal that scan line driver circuit will select to be written into the pixel column of signal is input in the sweep trace.The signal that this signal line drive circuit just is written in the pixel is input to signal wire.
Hereinafter is explained the operation of display device of the present invention.In (address period), scan line driver circuit selects to be connected to the pixel column of such sweep trace: promptly select the signal of pixel to be imported in this sweep trace during writing.Signal is written to each pixel of selected pixel column from the signal wire of every row.Then, each pixel storage writes signal wherein.Like this, between light emission period in (during keeping) pixel keep state (luminance, non-luminance etc.) through being written to signal controlling wherein.
Through repeating this operation, can rewrite and move image demonstration and still image demonstration.
In addition, display device of the present invention comprises: will have signal to write the device that data and the data that write pixel wherein (in other words, be stored in this pixel data) of the signal of pixel are not wherein given this pixel input signal when identical.
Notice that a plurality of pixels are connected to a sweep trace.Then, through these pixels of this scanning line selection the time, signal can be written in this pixel.Therefore, display device of the present invention is included in the device that the data of the data of the signal that will be written to pixel column that links to each other with sweep trace and the signal that has been written to this pixel column are not input to signal pixel column when identical.In other words; This display device comprise a plurality of pixels through being connected to a sweep trace confirm to carry out the pixel that writes signal data whether with the device of the Data Matching that is written to the signal in this pixel; If their couplings then stop the signal of this pixel is write.
In addition, scan line driver circuit is included in signal and will be written into the data of data and the signal that is written to this pixel column of signal of pixel column wherein and will select when identical the signal of this pixel column to be input to the device of the sweep trace that is connected with this pixel column.
The basic structure of display device of the present invention is shown in the accompanying drawing 71.Display device of the present invention comprises signal line drive circuit 7101, scan line driver circuit 7102 and pixel portion 7103.In pixel portion 7103, pixel 7104 is arranged with matrix-style with respect to sweep trace G1 to Gm and signal wire S1 to Sn.Notice that each pixel 7104 comprises that storage is written to the device of signal wherein.
Scan line driver circuit 7102 selects to have signal to be written to pixel wherein through any one the sweep trace Gi that signal is input among the sweep trace G1 to Gm.In other words, select the pixel column that links to each other with the sweep trace Gi (any one among the sweep trace G1 to Gm) of the signal that is input for selecting pixel.
Vision signal (Video Data) is imported into signal line drive circuit 7101.Then, signal line drive circuit 7101 will be input to signal wire S1 to Sn corresponding to the vision signal of the pixel of respective column.Notice that the signal that is input to signal wire S1 to Sn from signal line drive circuit 7101 is not limited to vision signal.For example, the signal of luminance (erase signal) can be imported in this pixel to force the pixel of all row all to be in not.
Hereinafter is explained the operation of display device.
In time, select the pixel column that will have signal to be written into through scan line driver circuit 7102 to the signal writing operation of pixel.Then, this signal is written to the pixel 7104 of the every row the selected pixel column through signal wire S1 to Sn from signal line drive circuit 7101.Notice that when this signal was written in the pixel 7104, each pixel storage write signal wherein.
In a similar fashion, sequentially select pixel 7104, and this signal is written to pixel 7104.When signal is written to all pixel 7104 in the pixel portion 7103, accomplish during the writing of pixel 7104.
Pixel 7104 storage be written to wherein signal certain during.Therefore, in the time of the light emission operation of pixel, can keep the state (luminous or not luminous) of each pixel that depends on the signal that is written to this pixel.
Can show mobile image through repeating write operation and light emission operation.Also be under the situation that shows still image, when rewriteeing image, carry out write operation and light emission operation at every turn.
At this, under the situation of the data data of the signal of pixel (that is: will be written to) that will have signal to be written to the signal of pixel wherein and the Data Matching of the signal that has been written to this pixel, display device of the present invention stops the signal of this pixel is write.In other words, when in the time of the signal writing operation of giving pixel column, not selecting this pixel column, the sweep trace that this display device continuation will not select the signal of this pixel column to be input to pixel column perhaps places quick condition with the sweep trace of pixel column.Therefore, stopped the signal of this pixel column is write.In other words, only stop the signal of this pixel is write during all with the Data Matching of the signal that will be written to this pixel in the data of the signal that is written to the pixel that links to each other with a sweep trace.Therefore, under the data of the signal of any one pixel situation inequality, this signal is written to all pixels that link to each other with this sweep trace.This is because when the signal of selecting this pixel is imported into sweep trace, force the current potential of this signal wire to be input to this pixel.Then, rewrite the data of pixel.Therefore, only under the situation that the data of all signals are all mated, prevent to select this sweep trace.
At this, when the signal of selecting pixel is imported into sweep trace, be that the load capacitance of representative is through charge charging or discharge with the distribution cross capacitance of sweep trace or the transistorized grid capacitance that is connected to this sweep trace.Therefore; Similar with display device of the present invention; When the data of the data of the signal that will be written to pixel column that links to each other with sweep trace and the signal that has been written to this pixel column are identical, prevent to be used to select the signal of this pixel column to be imported into the sweep trace that is connected with this pixel column.Then, the number of times of implementing charging and discharge can be reduced, therefore power consumption can be reduced.
Under the data of the signal that will be written to pixel column that links to each other with the sweep trace situation identical, through in to the time of the signal writing operation of this pixel column, placing quick condition can further greatly reduce power consumption the signal wire of pixel column with the data of the signal that has been written to this pixel column.This is charging and discharge because of the distribution cross capacitance of the signal wire of the pixel equal number that can save and be connected to a sweep trace.Note, can the previous state of holding signal line and need not this signal wire be placed quick condition.This is because of the charging of distribution cross capacitance and discharge has accomplished and signal wire does not consume a large amount of power.If power consumption can be suppressed, then can set another current potential.For example, can import this current potential that makes the signal that is written to this pixel cause leakage hardly.
In addition, when the data of the data of the vision signal that the pixel column that vision signal is transfused to will be arranged that links to each other with sweep trace and the signal that has been written to this pixel column are identical, can stop the input of vision signal to the signal line drive circuit.Even without incoming video signal, identical vision signal has been stored in the pixel column and has not needed and rewritten.Therefore, the signal line drive circuit can be worked no problemly.This can further reduce power consumption.If vision signal is imported into signal line drive circuit 7101 as serial data, the vision signal that then has high frequency is imported in the video signal cable of transmission video signal; Therefore, power consumption uprises.Therefore, through reducing the input operation of vision signal, can further reduce power consumption.
Particularly, the display device of the present invention's be suitable for having VGA (640 * 480) or higher resolution (vertical * level).This is because along with resolution increases, the quantity of pixel increases and the quantity of sweep trace and the also therefore increase of quantity of pixel column.In other words, when 640 pixels were connected to a sweep trace, except the distribution cross capacitance of sweep trace, for example 640 transistorized grid capacitances were charged according to the order of sequence with electric charge and are discharged to select pixel.In addition, when a pixel comprises the color-element of R (redness), G (green) and B (blueness), need charge and discharge the individual transistorized grid capacitance in 1920 (640 * 3).In addition, the quantity of signal wire is 640 (comprising that in single pixel under the situation of color-element of RGB be 1920).
If reduce the charging of enforcement sweep trace and the number of times of discharge, then power consumption can greatly reduce.At this moment, can further greatly reduce power consumption through signal wire being placed quick condition or input have been imported at the signal of going ahead of the rest.
The instance of VGA or higher resolution (vertical * level) is following: SVGA (800 * 600), XGA (1024 * 768), standard-VGA (1380 * 960); SXGA (1280 * 1024), SXGA+ (1400 * 1050), UXGA (1600 * 1200); QXGA (2048 * 1536); QUXGA (3200 * 2400), QUXGA wide (3840 * 2400), or the like.Notice that resolution described herein all is that the present invention is not limited to this for example.
Note; In pixel portion, have at the display device of the pixel of arranging with matrix-style on line direction and the column direction it and comprise and be used for selecting under the situation of pixel with a plurality of sweep traces of the pixel that signal is input to single row that the data that will in this single row of pixels, be connected to the pixel of each sweep trace compare each other.For example, comprise select pixel with the situation of two sweep traces signal being input to single row of pixels shown in the accompanying drawing 79.Display device comprises signal line drive circuit 7901, first scan line driver circuit 7902, second scan line driver circuit 7906 and the pixel portion, and this pixel portion comprises first pixel region 7903 and second pixel region 7907.Signal wire S1 to Sn and signal wire S ' 1 to S ' n extend to pixel portion from signal line drive circuit 7901.Sweep trace G1 to Gm extends to first pixel region 7903 from first scan line driver circuit 7902.Sweep trace G ' 1 to G ' m extends to second pixel region 7907 from second scan line driver circuit 7906.In other words, in first pixel region 7903, select the pixel column of first pixel region 7903 through any one that will select from first scan line driver circuit 7902 that the signal of pixel inputs to the sweep trace G1 to Gm.At this moment, the signal that is input to signal wire S1 to Sn from signal line drive circuit 7901 is written to each pixel 7904.In second pixel region 7907, select the pixel column of second pixel region 7907 through any one that will select from second scan line driver circuit 7906 that the signal of pixel is input to sweep trace G ' 1 to the G ' m.At this moment, the signal that is input to signal wire S ' 1 to S ' n from signal line drive circuit 7901 is written to each pixel 7904.Under the situation of this structure, whether the data that in each pixel region, relatively will be written to pixel column are identical with the data that are input to pixel column.If these data are identical, then stop the signal of pixel column is write.
In other words, when the signal of the pixel column that will be written to first pixel region 7903 was identical with the data that are written to this pixel column, display device of the present invention stopped the signal input to this pixel column.In addition, when the data of the signal of the pixel column that will be written to second pixel region 7907 were identical with the data that are written to this pixel column, this display device stopped the signal input to this pixel column.Therefore, in the single row of pixels of pixel portion, the data of signal of pixel column that will be input to pixel column or second pixel region 7907 of first pixel region 7903 compare with the data that have been written to each pixel column.When only the data with the data of the signal that is written into and the signal that has write in the pixel column of first pixel region 7903 are identical, do not select the pixel column of first pixel region 7903, and select the pixel column of second pixel region 7907.On the contrary, when the data of the data of the signal that will be written in the pixel column of second pixel region 7907 only and the signal that has write are identical, do not select the pixel column of second pixel region 7907, and select the pixel column of first pixel region 7903.
Notice that the quantity of the sweep trace G1 to Gm in first pixel region needn't be identical with the quantity of sweep trace G ' 1 to G ' m in second pixel region.In addition, the quantity of signal wire S1 to Sn also needn't be identical with the quantity of signal wire S ' 1 to S ' n.In addition, pixel portion is not limited to comprise the situation of two pixel regions.In other words, pixel portion can comprise three or more pixel region.
As indicated above, when the data of the data of the signal that will be input to the pixel column that links to each other with the one scan line and the signal that has been input to this pixel column were identical, display device of the present invention stopped the signal input to this pixel column.
Therefore, use to select pixel when signal being written to two sweep traces of single row of pixels, the frequency gets higher of stop signal input.This be because, the quantity of pixel has reduced, the data that wherein have been input to wherein compare to find whether they identical with the data that will be input to wherein.Because quantity is less, so data become identical easily.Therefore, reduce power consumption easily.
(embodiment pattern 1)
In the present embodiment pattern, illustrated in detail display device and operation thereof under the situation that applies the present invention to the time gray level method.
Display device in accompanying drawing 1 comprises signal line drive circuit 101, scan line driver circuit 102 and pixel portion 103.In addition, a plurality of pixels 104 in pixel portion 103 with respect to along column direction from the signal line drive circuit the 101 signal wire S1 to Sn that extend with follow the sweep trace G1 to Gm that direction extends from scan line driver circuit 102 and arrange with matrix-style.In addition, scan line driver circuit 102 comprises output control circuit 105.
Signal all is imported into scan line driver circuit 102 such as clock signal (G_CLK), inversion clock signal (G_CLKB), initial pulse signal (G_SP) and output control signal (G_ENABLE).
Clock signal (G_CLK) is an alternating signals between H (height) and L (low) at regular intervals, and inversion clock signal (G_CLKB) is the signal that has with the reverse polarity of clock signal (G_CLK).According to these signals, make the scan line driver circuit 102 also timing (sequential) of control and treatment execution synchronously.Therefore; When initial pulse signal (G_SP) is input in the scan line driver circuit 102, in being connected to each sweep trace G1 to Gm of pixel column, produce the sweep signal of selecting each pixel column according to clock signal (G_CLK) and inversion clock signal (G_CLKB).In other words, sweep signal is sequentially to select the signal of pixel column seriatim through the sweep trace that is connected to scan line driver circuit 102.
Signal is input to signal line drive circuit 101 such as clock signal (G_CLK), inversion clock signal (G_CLKB), initial pulse signal (G_SP) and vision signal (Video Data).
Clock signal (S_CLK) is an alternating signals between H (height) and L (low) at regular intervals, and inversion clock signal (S_CLKB) is the signal that has with the reverse polarity of clock signal (S_CLK).According to these signals, make the signal line drive circuit 101 also timing of control and treatment execution synchronously.Therefore, when initial pulse signal (S_SP) is input in the signal line drive circuit 101, produce sampling pulse corresponding to the row of pixel according to clock signal (S_CLK) and inversion clock signal (S_CLKB).In other words, sampling pulse is when vision signal is input in the signal line drive circuit 101, to control this timing converts the data of a row pixel into the vision signal that will be written to this pixel signal.Therefore, according to this sampling pulse, will convert parallel data into as the vision signal (Video Data) that serial data is input in the signal line drive circuit 101.Notice that under the situation of the sequential display spare of being expert at, this parallel data of vision signal is stored in the signal line drive circuit 101 and is input to simultaneously among each signal wire S1 to Sn.In addition, under the situation of dot sequency display device, the serial data of vision signal is converted into the parallel data of vision signal, and is input to each signal wire S1 to Sn according to the timing of sampling pulse.Like this, signal line drive circuit 101 will be input to corresponding to the vision signal of every row pixel among each signal wire S1 to Sn.
Therefore, the pixel column that selection will have signal to be written in the time of the sweep signal that produces through scan line driver circuit 102 usually.Then, the vision signal that is input to signal wire S1 to Sn from signal line drive circuit 101 is written to every row pixel 104 of selected pixel column.Each pixel 104 will be written to the data storage of vision signal wherein certain during.
Sequentially select pixel column, and the signal of when the vision signal corresponding to each pixel 104 is written in all pixels 104, accomplishing this pixel writes.Notice that each pixel 104 can keep can keeping during certain luminous through the data that will be written to signal wherein or luminance not.
Each pixel 104 of Data Control of vision signal through being written to each pixel 104 is luminous and not luminous, expresses gray scale with the length according to fluorescent lifetime.Note, show fully a viewing area (frame) image during be called as an image duration, the display device of present embodiment pattern comprises a plurality of subframes in an image duration during.Length during the subframe in an image duration can roughly be equal to each other or can not wait.In other words, luminous and not luminous according to each pixel 104 of control during each subframe during the sub-frame, to express the different gray scale of total fluorescent lifetime of each pixel 104.
As indicated above, normally select to be connected to all pixel columns of corresponding sweep trace through the sweep trace G1 to Gm that is connected to scan line driver circuit 102.Yet when the signal that will be written to a certain pixel was identical with the signal that is written to this pixel, display device of the present invention did not select to be connected to the pixel of this sweep trace.In other words, during a certain subframe in an image duration in, when the data of the signal of the pixel column that writes at the signal that will be performed pixel were identical with the data of the signal that is written to single pixel column wherein, signal was not input to this pixel column.Even input signal is still not no problem, because this signal is identical with the signal that has write.
Then; Output control signal (G_ENABLE) is imported into scan line driver circuit 102, will be performed during this signal has shown during an image duration a certain subframe the single pixel column that the signal to pixel writes signal data whether with the Data Matching of the signal of the single row that is written to this pixel column.When the output control signal (G_ENABLE) that shows coupling was input in the scan line driver circuit 102, anti-stop signal was input in the pixel column.Therefore, prevent that scan line driver circuit 102 from will select the signal of pixel column to be input to the sweep trace that is connected with this pixel column.In other words, the L signal of not selecting pixel column is input to the sweep trace of pixel column, perhaps the sweep trace with this pixel column places quick condition.As a result, signal is not input to the pixel that connects this sweep trace.
In addition; When the data of the signal of the single pixel column that writes at the signal that will be performed pixel in during the subframe in an image duration were identical with the data of the signal that is written to this pixel column, preferred video signal (Video Data) was not input to the signal line drive circuit.This can further reduce power consumption.This is because vision signal is input in the signal line drive circuit 101 through video signal cable as serial data, so high-frequency signal is input in the video signal cable.Therefore, power consumption uprises.Therefore, can further reduce power consumption through the input that reduces this vision signal.Notice that vision signal etc. are transferred to the signal line drive circuit through FPC etc. usually.At this, the instance of the structure of the display board of display device of the present invention is shown in the accompanying drawing 72.Signal line drive circuit 7201, scan line driver circuit 7202 and pixel portion 7203 all are formed on the substrate 7200, and pixel 7204 is arranged with matrix-style in pixel portion 7203 with respect to sweep trace and signal wire.In addition, FPC 7205 is connected to display board.In other words; From FPC 7205; Clock signal (G_CLK), inversion clock signal (G_CLKB), initial pulse signal (G_SP) etc. are input in the scan line driver circuit 7202 of display board, and clock signal (S_CLK), inversion clock signal (S_CLKB), initial pulse signal (S_SP), vision signal (Video Data) etc. are input in the signal line drive circuit 7201.In other words, the data of the vision signal through preventing not have the pixel column that signal writes are input to signal line drive circuit 7201 from FPC 7205, can reduce power consumption.
At this, applicable to the instance of the scan line driver circuit of the scan line driver circuit 102 of the display device in the present embodiment pattern shown in the accompanying drawing 6A.
At first, comprise impulse output circuit 601, output control circuit 602 and buffering circuit 603 in the scan line driver circuit shown in the accompanying drawing 6A.Clock signal (G_CLK), inversion clock signal (G_CLKB), initial pulse signal (G_SP) etc. are input to impulse output circuit 601.Then, sweep signal (SC.1 to SC.m) is input in the output control circuit 602 according to the timing of these signals.
At this, will export control signal (G_ENABLE) and be input in the output control circuit 602.Then, output control signal (G_ENABLE) is carried out control so that the pixel column that stops to select will stop signal writing.Be converted into pixel selection signal (G.1 to G.m) and be entered into sweep trace G1 to Gm through buffer circuit 603 from the sweep signal (SC.1 to SC.m) of output control circuit 602 outputs with high electric current transport capacity.
Subsequently, the more detailed structure example of accompanying drawing 6A is shown in the accompanying drawing 6B.In addition, use the operation of this scan line driver circuit of timing diagram explanation of accompanying drawing 33.
Impulse output circuit 611 comprises multistage trigger circuit (FF) 614 and AND door 615, and two input terminals of AND door 615 are connected respectively to the lead-out terminal of adjacent trigger circuit (FF) 614.In other words, the trigger circuit (FF) 614 with respect to a redundancy of AND door 615 are provided in every grade, and will be input to every grade the AND door 615 that provides relatively with sweep trace G1 to Gm from the output of adjacent trigger circuits (FF) 614.
Clock signal (G_CLK) and inversion clock signal (G_CLKB) are input to each trigger circuit (FF) 614, and initial pulse signal (G_SP) is input to the trigger circuit 614 of the first order.Pulse 3301 is initial pulse signals in accompanying drawing 33.In the time of in the trigger circuit that are input to next stage 614, make a pulse of pulse 3301 delay clock signals.The output of AND door 615 of the first order of output of trigger circuit 614 of trigger circuit 614 and next stage of redundancy that therefore, will be transfused to the first order is by ratio of pulse length to the total cycle length of delayed clock pulse such as pulse 3302.Pulse 3302 is input to an input terminal corresponding to the AND door 615 of the output control circuit 612 of the first order as sweep signal SC.1.The output of the AND door 615 that the output of the AND door 615 that similarly, i is capable and m are capable is input to a corresponding input terminal of every grade AND door 615 of output control circuit 612 respectively as sweep signal SC.i and SC.m (such as pulse 3303 and 3304).
In addition, output control signal (G_ENABLE) is input in the output control circuit 612 in other input terminal of AND door 616 of every grade.Be controlled at whether select pixel when sweep signal SC.1 to SC.m is input to the AND door 616 of corresponding stage according to the output control signal.In other words; In the time of the sweep signal SC.1 to SC.m that is input to AND door 616, select under the situation of pixel, the buffer circuit 617 through each grade buffer circuit 613 with sweep signal SC.1 to SC.m convert into have high electric current transport capacity pixel selection signal G.1 to G.m.Then, G.1 pixel selection signal is input to corresponding sweep trace G1 to Gm to G.m.
On the other hand; Under the situation of not exporting the sweep signal SC.1 to SC.m that is used to be input to AND door 616; When the capable sweep signal SC.i of i is exported, pulse 3308 is input to output control signal (G_ENABLE); Do not export the pulse of the pixel selection signal G.i that is used to select the capable pixel of i, shown in accompanying drawing 33.Note; Pulse 3308 is L level signals, and be have in during a certain subframe of an image duration signal be written to its pixel the capable pixel of i signal data be written to the signal that i is transfused under the identical situation of the data of signal of pixel in capable.Therefore, the pulse of pixel selection signal G.i is not input to the sweep trace that links to each other with pixel during i is capable, and is not chosen in the pixel of i in capable.
Notice that the structure that is suitable for the scan line driver circuit 102 of present embodiment pattern is not limited to the structure in accompanying drawing 6A and 6B.It can be such structure: wherein this sweep trace is placed quick condition non-selected when being connected to the pixel of a certain sweep trace.
Noting, when the signal that will select pixel is input to sweep trace, is that the load capacitance of representative is charged with electric charge and discharged with the distribution cross capacitance of the transistorized grid capacitance that is connected to sweep trace or sweep trace.Therefore; As the display device of describing in the present embodiment pattern; When the data of the data of the signal that will be written to pixel column that links to each other with sweep trace and the signal that has been written to this pixel column are identical, prevent to be used to select the signal of pixel column to be input to the sweep trace that is connected with this pixel column.Therefore, the number of times of implementing charging and discharge can be reduced, therefore power consumption can be reduced.
In display device of the present invention, preferred signals line driver circuit 101 also comprises output control circuit.In addition; Be used for single pixel column and will under the data that are written to the signal of pixel wherein during a certain subframe of the image duration situation identical, preferably also prevent the output control circuit outputting video signal of signal line drive circuit 101 with the data of the signal that is written to this pixel column.In the output of signal line drive circuit 101 at this moment can be that pixel is placed the signal of luminance or pixel is placed the not signal of luminance.Also can import and before the identical signal of delegation's signal.Owing under the situation of same signal, do not carry out charging and discharge, therefore consumed power not.Can the signal that consume the least possible power be input in the signal wire.In addition, can signal wire S1 to Sn be placed quick condition.This is because signal is not imported in the pixel, so the current potential of signal wire can be any value.Therefore, this state comparative optimization that has lowest power consumption.
Therefore, place quick condition can further greatly reduce power consumption through signal wire with pixel column.This is because can be removed with the charging and the discharge of its distribution cross capacitance of signal wire of the pixel equal number that is connected to signal wire.Note, can directly export just in time before be input to the signal of this signal wire and be not interposing at quick condition.Owing to accomplished the charging and the discharge of distribution cross capacitance, so signal wire does not consume very big power.
Note; Display device of the present invention can utilize two kinds of following methods: wherein vision signal is imported into every column signal line and signal is written to the some preface method of each pixel seriatim from the signal line drive circuit, perhaps wherein signal is written to simultaneously the capable preface method of all pixels in the selected pixel column.
Note, under the situation that operating part shows, also can use the driving method of in the present embodiment pattern, explaining.Accompanying drawing 76A has shown the situation of on entire display screen, carrying out demonstration; Accompanying drawing 76B shown on top part carry out show and in the bottom part do not carry out the situation of demonstration, accompanying drawing 76C has shown the situation of in top part and bottom part, not carrying out demonstration but partly carrying out demonstration at the middle part.In case the signal that is used for not showing is written to the pixel of non-display area,, then can reduce power consumption if under the situation that signal repeatedly is written to the pixel in the viewing area, do not select the pixel in the non-display area.Note, as refresh operation, signal is written in the viewing area pixel repeatedly after, the signal that does not show can be written in the pixel in the non-display area.
(embodiment pattern 2)
In the present embodiment pattern, explain capable sequential display spare of the present invention and operation thereof.
Accompanying drawing 3 is depicted as the synoptic diagram of capable sequential display spare.Signal line drive circuit 301 is corresponding to the signal line drive circuit 101 of the display device in the accompanying drawing 1.Other common means through with accompanying drawing 1 in the identical Reference numeral of Reference numeral represent, therefore save explanation to them.
Signal line drive circuit 301 comprises impulse output circuit 302, first latch cicuit 303, second latch cicuit 304 and output control circuit 305.
Clock signal (S_CLK), inversion clock signal (S_CLKB), initial pulse signal (S_SP) etc. all are imported into impulse output circuit 302.Then, export sampling pulse according to the timing of these signals.
Be imported into first latch cicuit 303 from the sampling pulse of impulse output circuit 302 outputs.Vision signal (Video Data) is imported into first latch cicuit 303, and according to the timing that is used for the input sample pulse data of vision signal is remained on every grade of first latch cicuit 303.
When the data of vision signal keep being accomplished to the afterbody in first latch cicuit 303; During horizontal flyback sweep latch pulse signal (Latch Pulse) is input in second latch cicuit 304, the data of the vision signal that in first latch cicuit 303, keeps are passed to second latch cicuit 304 simultaneously.The data of the vision signal that is used for single pixel column that after this, in second latch cicuit 304, keeps are exported to output control circuit 305 simultaneously.
Output control signal (S_ENABLE) is imported into output control circuit 305.Then, confirm whether outputting video signal of output control circuit 305 according to the level of output control signal.In other words, confirm whether vision signal is transfused to signal wire S1 to Sn.Notice that even the display device of present embodiment pattern does not comprise output control circuit 305 in the signal line drive circuit, it still can reduce power consumption.Yet, when display device comprises output control circuit 305, can further reduce power consumption.At output control circuit 305 not under the situation of outputting video signal; Can signal wire S1 to Sn be placed quick condition; Can export fixing current potential to signal wire S1 to Sn, perhaps can be held and continue output with the identical signal of signal that is imported into the pixel in advance.In other words, can export this current potential that is used to reduce power consumption.In order to reduce power consumption, preferably do not charge and discharge through electric charge.Owing to when changing current potential, just carry out charging and discharge, therefore preferably do not change current potential through electric charge.
At this, accompanying drawing 18A has shown the instance of the signal line drive circuit of the signal line drive circuit 301 that can be suitable for the capable sequential display spare in the present embodiment pattern.
Comprise impulse output circuit 801, first latch cicuit 802, second latch cicuit 803 and output control circuit 804 at the signal line drive circuit shown in the accompanying drawing 18A.Clock signal (S_CLK), inversion clock signal (S_CLKB) and initial pulse signal (S_SP) all are imported in the impulse output circuit 801.According to these signal sequence ground output sampling pulses.
The sampling pulse of output is imported in first latch cicuit 802 from impulse output circuit 801, and vision signal (Video Data) is maintained in first latch cicuit 802 according to the timing of this signal.
When the data of vision signal keep being accomplished to the afterbody in first latch cicuit 802; During horizontal flyback sweep latch pulse (Latch Pulse) is input in second latch cicuit 803, the vision signal that in first latch cicuit 802, keeps is passed to second latch cicuit 803 simultaneously.
The vision signal that is passed to second latch cicuit 803 is imported into output control circuit 804.In addition, output control signal (S_ENABLE) is imported into output control circuit 804, and whether this signal controlling vision signal is outputed to signal wire S1 to Sn.
Note, not during outputting video signal, can signal wire S1 to Sn placed quick condition or can set fixing current potential at output control circuit 804.As fixing current potential, can set this current potential that is used to reduce power consumption.
Note; Be used for the data of vision signal of single row in during the data that are used for single pixel column and will during the subframe of an image duration, be written to the vision signal of pixel wherein and the last subframe when identical; Output control signal (S_ENABLE) is in the L level, and the output control signal is in the H level when any part of the data of this single row is inequality.
In other words, output control signal (S_ENABLE) when being in the L level not from output control circuit 804 outputting video signals, and when output control signal (S_ENABLE) is in the H level from output control circuit 804 outputting video signals.
Accompanying drawing 8B shows the more detailed structure of signal line drive circuit.In addition, use
The timing diagram of accompanying drawing 34 is explained the operation of signal line drive circuit.
Use multistage trigger circuit (FF) 815 grades to form impulse output circuit 811, clock signal (S_CLK), inversion clock signal (S_CLKB) and initial pulse signal (S_SP) all are input to wherein.
Note the T in accompanying drawing 34 Gi-1, T Gi, T Gi+1And T Gi+2During in first latch cicuit 812 that be input in being illustrated respectively in during a certain subframe that (i-1) row, i are capable, the vision signal of (i+1) row pixel in capable with (i+2) is latched at the signal line drive circuit.In other words, select corresponding to grid during these during.Then, the data 3406 of the data 3405 of the data 3404 of vision signal, vision signal and vision signal are respectively at T Gi-1, T GiAnd T Gi+1In be imported into first latch cicuit 812.
At first, explain T Gi-1Operation.Clock signal (S_CLK) and inversion clock signal (S_CLKB) are imported into each trigger circuit (FF) 815, and initial pulse signal (S_SP) is imported into the trigger circuit 815 of the first order.In accompanying drawing 34, pulse 3401 is corresponding to T Gi-1 initial pulse signal.
In the time of in the trigger circuit that are input to next stage 815, make a pulse of pulse 3401 delay clock signals.This pulse 3402 is imported into the LAT1 corresponding to the pixel of first row in first latch cicuit 812 as sampling pulse Samp.1.Similarly, the output of the trigger circuit 815 of n level as sampling pulse Samp.n be input to first latch cicuit 812 in the corresponding LAT1 of pixel of n row.
At T Gi-1During this time, the data 3404 of vision signal are transfused in first latch cicuit 812, and according to the timing that is used for the input sample pulse vision signal are remained on each grade LAT1 corresponding to the pixel of every row.Notice that the timing of input sample pulse means that sampling pulse drops to the timing of L level from the H level.At this moment, being input to vision signal in first latch cicuit 812 remains in every grade of first latch cicuit 812.
When the completion vision signal keeps the last level in first latch cicuit 812; During horizontal flyback sweep latch pulse (Latch Pulse) 3407 is input in second latch cicuit 813; After this vision signal that in first latch cicuit 812, keeps is passed to second latch cicuit 813. simultaneously, and the vision signal that is used for single pixel column that in second latch cicuit 813, keeps is transfused to output control circuit 814 simultaneously.
Notice that output control signal (S_ENABLE) is imported into output control circuit 814, whether outputed to signal wire S1 to Sn through the level control of video signal of exporting control signal.
Note; Be used for single pixel column and will be during the subframe of an image duration in be written to the vision signal of pixel wherein data and last subframe during in be used for the data of vision signal of single row when identical; Output control signal (S_ENABLE) is in the L level, and the output control signal is in the H level when any part of the data of this single row is inequality.
In other words; Output control signal (S_ENABLE) when being in the L level not from output control circuit 814 outputting video signals; Because the analog switch that in every grade of output control circuit 814, provides is blocked; And output control signal (S_ENABLE) when being in the H level from output control circuit 814 outputting video signals, because the analog switch that in every grade, provides is switched on.
Subsequently, operation proceeds to T GiBecause output control signal (S_ENABLE) is in the H level, the data 3404 of the vision signal that therefore in second latch cicuit 813, keeps are outputed to signal wire S1 to Sn through output control circuit 814.Then, initial pulse signal (S_SP) is input to the trigger circuit 815 of the first order once more.Pulse 3408 is T GiInitial pulse signal.After this, export sampling pulse once more.According to the timing of sampling pulse, the data 3405 of vision signal are maintained in every grade of first latch cicuit 812.When input and latch pulse 3409, the data 3405 of vision signal are passed to second latch cicuit 813 simultaneously.The data 3405 of the vision signal of single pixel column are imported in the output control circuit 814 simultaneously.
Subsequently, operation proceeds to T Gi+1Because output control signal (S_ENABLE) is in the L level, the not output from output control circuit 814 of the data 3405 of the vision signal that therefore in second latch cicuit 813, keeps.In other words, signal wire S1 to Sn is placed quick condition.Then, initial pulse signal (S_SP) is input in the trigger circuit 815 of the first order once more.Pulse 3410 is T Gi+1Initial pulse signal.After this, export sampling pulse once more.According to the timing of sampling pulse, the data 3406 of vision signal are maintained in every grade of first latch cicuit 812.When input and latch pulse 3412, the data 3406 of vision signal are passed to second latch cicuit 813 simultaneously.The data 3406 of the vision signal of single pixel column are transfused to output control circuit 814 simultaneously.
Subsequently, operation proceeds to T Gi+2. because output control signal (S_ENABLE) is in the H level, the vision signal 3406 that therefore in second latch cicuit 813, keeps is outputed to signal wire S1 to Sn through output control circuit 814.Then, initial pulse signal (S_SP) is input to the trigger circuit 815 of the first order once more.Pulse 3413 is T Gi+2Initial pulse signal.
During writing, repeat above-mentioned operation to handle the vision signal of subframe.In addition, through can show the image of a frame to the re-treatment of subframe.
Note, during the signal to the capable pixel of i writes in (in other words, at T Gi+1In) signal wire S1 to Sn is placed quick condition, because it is identical with the data that are written to the pixel of i in capable to write the data of vision signal of the pixel of i in capable.Therefore, charging and discharge can be saved, therefore power consumption can be reduced this signal wire.
The vision signal of the pixel column that writes of stop signal for during parallel, can prevent to import the pulse of the initial pulse signal (S_SP) that is used to trigger beginning holding signal data from serial conversion therein.In other words, at the T shown in accompanying drawing 68 GiIn do not import the pulse of initial pulse signal (S_SP).Because correspondingly not from impulse output circuit 811 output sampling pulses, so the data 3405 of vision signal are not maintained in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.Therefore, can further reduce power consumption.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion can stopping the input of vision signal to the signal line drive circuit for during parallel.In other words, at T GiCan prevent that during this time vision signal (Video Data) is imported in the signal line drive circuit, shown in accompanying drawing 69.This be because, at T GiThe vision signal that keeps does not during this time export signal wire S1 to Sn to, does not therefore need incoming video signal at first.Owing to can save through charging and the discharge of electric charge through the input that stops vision signal, therefore can reduce power consumption to video line.At T GiDuring this time, can be used to reduce this current potential of power consumption to the video line input.Replacedly, can vision signal be placed quick condition.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.Note, from the outside with signal be input to wherein splicing ear and signal line drive circuit when all being formed with the pixel portion that is inserted in therebetween this situation be effective especially.This structure is shown in the accompanying drawing 80.In accompanying drawing 80, signal line drive circuit 8001, scan line driver circuit 8002, pixel portion 8003 and splicing ear part 8005 all are provided on the substrate 8000.On pixel portion 8003, opposite electrode 8004 is formed and covers pixel portion 8003.Opposite electrode 8004 is connected to the wideer distribution of pad than a plurality of splicing ears 8007 that stretch out from splicing ear 8007 through contact hole 8008, and the low power supply terminal of the opposite electrode that in the splicing ear part, forms is imported in the splicing ear 8007.The splicing ear 8006 that is transfused to vision signal is connected to signal line drive circuit 8001 through video line 8009.Under the situation of using this structure, the resistance of power lead to opposite electrode 8004 (such as the contact resistance of splicing ear 8007 and FPC terminal or the wiring resistance between opposite electrode 8004 and splicing ear 8007) can be reduced.Therefore, the voltage drop in power lead can be lowered, and the current potential of opposite electrode can be set to normally.Even lead-in wire becomes and resembles that video line 8009 is to be grown, still can reduce charging and discharge to vision signal 8009.Can reduce power consumption like this.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion can stopping input clock signal (S_CLK), inversion clock signal (S_CLKB) etc. for during parallel.In other words, shown in accompanying drawing 70, at T GiCan prevent that during this time clock signal (S_CLK) or inversion clock signal (S_CLKB) are imported in the signal line drive circuit.For example, can import between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is in the H level, and another is in the L level) by the fixing current potential of anti-phase.This is because under the situation of the fixing current potential of input, do not charge through electric charge and discharge, so can reduce power consumption.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion can stopping input from latching pulse for during parallel.In other words, at the T shown in accompanying drawing 104 GiIn, can prevent that latch pulse (Latch Pulse) is imported in the signal line drive circuit.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812, then can saves with electric charge and charge and discharge in this case.Can reduce power consumption like this.Because other class signal is similar to the signal at accompanying drawing 34, therefore saved description of them.
Be used for the vision signal that is stopped the pixel column that signal writes by from serial conversion for during parallel, can prevent to import the pulse of the initial pulse signal (S_SP) that is used to trigger beginning holding signal data.In addition, can stop signal line drive circuit incoming video signal.In other words, at T GiDo not import the pulse of initial pulse signal (S_SP) during this time, shown in accompanying drawing 82.Owing to correspondingly from impulse output circuit 811, do not export sampling pulse, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.In addition, vision signal (VideoData) is not input in the signal line drive circuit.This is because at T GiThe vision signal that is kept does not during this time output to signal wire S1 to Sn, does not therefore need incoming video signal at first.Owing to can save with electric charge through the input that stops vision signal and video line to be charged and discharge, so can reduce power consumption.At T GiDuring this time, can this current potential that be used to reduce power consumption be input to video line.Can reduce power consumption like this.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion for during parallel, can preventing to import the pulse of the initial pulse signal (S_SP) that is used to trigger beginning holding signal data.In addition, can stop input clock signal (S_CLK), inversion clock signal (S_CLKB) etc.In other words, shown in accompanying drawing 83, at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Owing to correspondingly from impulse output circuit 811, do not export sampling pulse, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.Can reduce power consumption like this.In addition, clock signal (S_CLK) and inversion clock signal (S_CLKB) are not input in the signal line drive circuit.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is the H level, and another is the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge.Can reduce power consumption like this.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion for during parallel, can preventing to import the pulse of the initial pulse signal (S_SP) that is used to trigger beginning holding signal data.In other words, shown in accompanying drawing 84, at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Owing to correspondingly from impulse output circuit 811, do not export sampling pulse, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.In addition, latch pulse (Latch Pulse) is not input in the signal line drive circuit.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Therefore, can further reduce power consumption.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Can stop signal line drive circuit incoming video signal for during parallel being used for the vision signal that is stopped the pixel column that signal writes from serial conversion.In addition, can stop input clock signal (S_CLK), inversion clock signal (S_CLKB) etc.In other words, shown in accompanying drawing 85, at T GiCan prevent that during this time incoming video signal (VideoData) is input to the signal line drive circuit.This be because, at T GiThe vision signal that keeps does not during this time output among the signal wire S1 to Sn, does not therefore need incoming video signal at first.Owing to can save with electric charge through the input that stops vision signal and video line to be charged and discharge, so can reduce power consumption.At T GiCan this current potential that be used to reduce power consumption be input to video line during this time.In addition, at T GiClock signal (S_CLK) and inversion clock signal (S_CLKB) are not input in the signal line drive circuit during this time.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (at the H level, another is at the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge.Can reduce power consumption like this.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Can stop signal line drive circuit incoming video signal for during parallel being used for the vision signal that is stopped the pixel column that signal writes from serial conversion.In addition, can stop the input of latch pulse.In other words, shown in accompanying drawing 86, at T GiCan prevent that during this time vision signal (Video Data) is imported in the signal line drive circuit.This be because, at T GiThe vision signal that keeps does not during this time output among the signal wire S1 to Sn, does not therefore need incoming video signal at first.Owing to can save with electric charge through the input that stops vision signal and video line to be charged and discharge, so can reduce power consumption.At T GiDuring this time, can this current potential that be used for reducing power consumption be input to video line.In addition, at T GiLatch pulse (Latch Pulse) is not input in the signal line drive circuit during this time.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion can stopping input clock signal (S_CLK), inversion clock signal (S_CLKB) etc. for during parallel.In addition, can stop the input of latch pulse.In other words, shown in accompanying drawing 87, at T GiCan prevent that during this time clock signal (S_CLK) and inversion clock signal (S_CLKB) are imported in the signal line drive circuit.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is the H level, and another is the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge.In addition, at T GiCan prevent that during this time latch pulse (Latch Pulse) is imported in the signal line drive circuit.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion for during parallel, can preventing to import the pulse of the initial pulse signal (S_SP) that is used to trigger beginning holding signal data.In addition, can stop signal line drive circuit incoming video signal.In addition, can stop input clock signal (S_CLK), inversion clock signal (S_CLKB) etc.In other words, shown in accompanying drawing 88, at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Because sampling pulse is not correspondingly from impulse output circuit 811 outputs, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.In addition, vision signal (Video Data) is not input in the signal line drive circuit.This be because, at T GiThe vision signal that keeps does not during this time output among the signal wire S1 to Sn, does not therefore need incoming video signal at first.Owing to can save with electric charge through the input that stops vision signal and video line to be charged and discharge, so can reduce power consumption.At T GiDuring this time, can this current potential that be used for reducing power consumption be input to video line.Can reduce power consumption like this.In addition, at T GiCan prevent that during this time clock signal (S_CLK) and inversion clock signal (S_CLKB) are imported in the signal line drive circuit.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is the H level, and another is the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge.Can reduce power consumption like this.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion for during parallel, can preventing to import the pulse of the initial pulse signal (S_SP) that is used to trigger beginning holding signal data.In addition, can prevent that clock signal (S_CLK), inversion clock signal (S_CLKB) are transfused to.In addition, can stop the input of latch pulse.In other words, shown in accompanying drawing 89, at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Because sampling pulse is not correspondingly from impulse output circuit 811 outputs, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.Can reduce power consumption like this.In addition, clock signal (S_CLK) and inversion clock signal (S_CLKB) are not imported in the signal line drive circuit.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is the H level, and another is the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge, so can reduce power consumption.In addition, at T GiCan prevent that during this time latch pulse (Latch Pulse) is imported in the signal line drive circuit.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Can stop vision signal being input to the signal line drive circuit for during parallel being used for the vision signal that is stopped the pixel column that signal writes from serial conversion.In addition, can stop input clock signal (S_CLK), inversion clock signal (S_CLKB) etc.In addition, can stop the input of latch pulse.In other words, shown in accompanying drawing 90, at T GiCan prevent that during this time vision signal (Video Data) is imported in the signal line drive circuit.This be because, at T GiThe vision signal that keeps does not during this time output among the signal wire S1 to Sn, does not therefore need incoming video signal at first.Owing to can save with electric charge through the input that stops vision signal and video line to be charged and discharge, so can reduce power consumption.At T GiDuring this time, can this current potential that be used for reducing power consumption be input to video line.In addition, at T GiClock signal (S_CLK) and inversion clock signal (S_CLKB) are not imported in the signal line drive circuit during this time.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is the H level, and another is the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge.Can reduce power consumption like this.In addition, at T GiCan prevent that during this time latch pulse (LatchPulse) is imported in the signal line drive circuit.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion for during parallel, can preventing to import the pulse of the initial pulse signal (S_SP) that is used to trigger beginning holding signal data.In addition, can stop vision signal being input to the signal line drive circuit.In addition, can stop input clock signal (S_CLK), inversion clock signal (S_CLKB) etc.In addition, can stop the input of latch pulse.In other words, shown in accompanying drawing 91, at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Because sampling pulse is not correspondingly from impulse output circuit 811 outputs, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.In addition, vision signal (Video Data) is not input in the signal line drive circuit.This be because, at T GiThe vision signal that keeps does not during this time output among the signal wire S1 to Sn, does not therefore need incoming video signal at first.Owing to can save with electric charge through the input that stops vision signal and video line to be charged and discharge, so can reduce power consumption.At T GiDuring this time, can this current potential that be used for reducing power consumption be input to video line.Can reduce power consumption like this.In addition, at T GiCan prevent that during this time clock signal (S_CLK) and inversion clock signal (S_CLKB) are imported in the signal line drive circuit.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is the H level, and another is the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge, so can reduce power consumption.In addition, at T GiCan prevent that during this time latch pulse (Latch Pulse) is imported in the signal line drive circuit.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Note, be not limited to these applicable to the signal line drive circuit of display device of the present invention.In other words; Be used for single pixel column pixel and will be under the data that are written to the vision signal of pixel wherein during a certain subframe of the image duration situation identical with the data of the signal that is written to this pixel column, when non-selected this pixel column, signal is not written to this pixel column.Therefore, can use such structure, wherein can this current potential maintenance that the signal maintenance that be imported into the pixel in advance is input to this signal wire or will be used to reduce power consumption be input to this signal wire.
Therefore, output control circuit 814 needn't be provided.Yet; Can further reduce power consumption owing to be imported into the signal of the pixel in advance through output, therefore it is desirable in first latch cicuit 812, latch and be used for stopping the input of latch pulse during the vision signal that is stopped the pixel column that signal writes or preventing to be used to trigger the input of pulse of the initial pulse signal (S_SP) of beginning holding signal data.
In other words, be used for the vision signal that is stopped the pixel column that signal writes from serial conversion stopping the input of latch pulse for during parallel.In other words, shown in accompanying drawing 92, at T GiCan prevent that during this time latch pulse (Latch Pulse) is imported in the signal line drive circuit.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because at T GiThe data 3405 of not input and latch pulse, so vision signal during this time are not passed to second latch cicuit 813 from first latch cicuit 812.Therefore, the data 3404 with vision signal continue to remain in second latch cicuit 813.Then, at T Gi+1This signal is also outputed to signal wire S1 to Sn during this time.Correspondingly, therefore can reduce power consumption owing to do not need to carry out once more charging and the discharge of signal wire S1 to Sn.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion stopping the input of latch pulse for during parallel.In addition, can prevent to import the pulse that is used to trigger the initial pulse signal (S_SP) that begins the holding signal data.In other words, shown in accompanying drawing 93, at T GiCan prevent during this time latch pulse (Latch Pulse) is input in the signal line drive circuit.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because at T GiThe data 3405 of not input and latch pulse, so vision signal during this time are not passed to second latch cicuit 813 from first latch cicuit 812.Therefore, the data 3404 with vision signal continue to remain in second latch cicuit 813.Then, at T Gi+1This signal is also outputed to signal wire S1 to Sn during this time.Correspondingly, therefore can reduce power consumption owing to do not need to carry out once more charging and the discharge of signal wire S1 to Sn.Because at T GiSignal is not delivered to second latch cicuit 813 from first latch cicuit 812 during this time, therefore at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Because sampling pulse is not correspondingly from impulse output circuit 811 outputs, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
In other words, be used for the vision signal that is stopped the pixel column that signal writes from serial conversion stopping the input of latch pulse for during parallel.In addition, can stop signal line drive circuit incoming video signal.In other words, shown in accompanying drawing 94, at T GiLatch pulse (Latch Pulse) is not input in the signal line drive circuit during this time.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because at T GiThe data 3405 of not input and latch pulse, so vision signal during this time are not passed to second latch cicuit 813 from first latch cicuit 812.Therefore, the data 3404 with vision signal continue to remain in second latch cicuit 813.Then, at T Gi+1This signal is also outputed to signal wire S1 to Sn during this time.Correspondingly, therefore can reduce power consumption owing to do not need to carry out once more charging and the discharge of signal wire S1 to Sn.At T GiDuring this time, can prevent that vision signal (VideoData) is imported in the signal line drive circuit.This be because, at T GiThe vision signal that keeps does not during this time output among the signal wire S1 to Sn, does not therefore need incoming video signal at first.Owing to can save with electric charge through the input that stops vision signal and video line to be charged and discharge, so can reduce power consumption.At T GiDuring this time, can this current potential that be used for reducing power consumption be input to video line.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
In other words, be used for the vision signal that is stopped the pixel column that signal writes from serial conversion stopping the input of latch pulse for during parallel.In addition, stop the input of clock signal (S_CLK), inversion clock signal (S_CLKB) etc.In other words, shown in accompanying drawing 95, at T GiPrevent that during this time latch pulse (Latch Pulse) is input in the signal line drive circuit.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because at T GiThe data 3405 of not input and latch pulse, so vision signal during this time are not passed to second latch cicuit 813 from first latch cicuit 812.Therefore, the data 3404 with vision signal continue to remain in second latch cicuit 813.Then, at T Gi+1This signal is also outputed to signal wire S1 to Sn during this time.Correspondingly, therefore can reduce power consumption owing to do not need to carry out once more charging and the discharge of signal wire S1 to Sn.At T GiDuring this time, can prevent that clock signal (S_CLK) and inversion clock signal (S_CLKB) are imported in the signal line drive circuit.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is the H level, and another is the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge, so can reduce power consumption.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion stopping the input of latch pulse for during parallel.In addition, can prevent to import the pulse that is used to trigger the initial pulse signal (S_SP) that begins the holding signal data.In addition, stop signal line drive circuit incoming video signal.In other words, shown in accompanying drawing 96, at T GiCan prevent that during this time latch pulse (Latch Pulse) is input in the signal line drive circuit.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because at T GiThe data 3405 of not input and latch pulse, so vision signal during this time are not passed to second latch cicuit 813 from first latch cicuit 812.Therefore, the data 3404 with vision signal continue to remain in second latch cicuit 813.Then, at T Gi+1This signal is also outputed to signal wire S1 to Sn during this time.Correspondingly, therefore can reduce power consumption owing to do not need to carry out once more charging and the discharge of signal wire S1 to Sn.At T GiSignal is not delivered to second latch cicuit 813 from first latch cicuit 812 during this time, therefore at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Because sampling pulse is not correspondingly from impulse output circuit 811 outputs, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.At T GiCan prevent that during this time vision signal (Video Data) is imported in the signal line drive circuit.This be because, at T GiThe vision signal that keeps does not during this time output among the signal wire S1 to Sn, does not therefore need incoming video signal at first.Owing to can save with electric charge through the input that stops vision signal and video line to be charged and discharge, so can reduce power consumption.At T GiDuring this time, can this current potential that be used for reducing power consumption be input to video line.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion stopping the input of latch pulse for during parallel.In addition, can prevent to import the pulse that is used to trigger the initial pulse signal (S_SP) that begins the holding signal data.In addition, stop the input of clock signal (S_CLK), clock signal (S_CLK) etc.In other words, shown in accompanying drawing 97, at T GiCan prevent that during this time latch pulse (Latch Pulse) is input in the signal line drive circuit.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because at T GiThe data 3405 of not input and latch pulse, so vision signal during this time are not passed to second latch cicuit 813 from first latch cicuit 812.Therefore, the data 3404 with vision signal continue to remain in second latch cicuit 813.Then, at T Gi+1This signal is also outputed to signal wire S1 to Sn during this time.Correspondingly, therefore can reduce power consumption owing to do not need to carry out once more charging and the discharge of signal wire S1 to Sn.Because at T GiSignal is not delivered to second latch cicuit 813 from first latch cicuit 812 during this time, therefore at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Because sampling pulse is not correspondingly from impulse output circuit 811 outputs, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.At T GiDuring this time, can prevent that clock signal (S_CLK) and inversion clock signal (S_CLKB) are imported in the signal line drive circuit.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is the H level, and another is the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge, so can reduce power consumption.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
In other words, be used for the vision signal that is stopped the pixel column that signal writes from serial conversion stopping the input of latch pulse for during parallel.In addition, can stop signal line drive circuit incoming video signal.In addition, stop the input of clock signal (S_CLK), clock signal (S_CLK) etc.In other words, shown in accompanying drawing 98, at T GiLatch pulse (Latch Pulse) is not input in the signal line drive circuit during this time.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because at T GiThe data 3405 of not input and latch pulse, so vision signal during this time are not passed to second latch cicuit 813 from first latch cicuit 812.Therefore, the data 3404 with vision signal continue to remain in second latch cicuit 813.Then, at T Gi+1This signal is also outputed to signal wire S1 to Sn during this time.Correspondingly, therefore can reduce power consumption owing to do not need to carry out once more charging and the discharge of signal wire S1 to Sn.At T GiCan prevent that during this time vision signal (Video Data) is imported in the signal line drive circuit.This be because, at T GiThe vision signal that keeps does not during this time output among the signal wire S1 to Sn, does not therefore need incoming video signal at first.Owing to can save with electric charge through the input that stops vision signal and video line to be charged and discharge, so can reduce power consumption.At T GiDuring this time, can this current potential that be used for reducing power consumption be input to video line.At T GiDuring this time, can prevent that clock signal (S_CLK) and inversion clock signal (S_CLKB) are imported in the signal line drive circuit.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is the H level, and another is the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge, so can reduce power consumption.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion stopping the input of latch pulse for during parallel.In addition, can prevent to import the pulse that is used to trigger the initial pulse signal (S_SP) that begins the holding signal data.In addition, can stop signal line drive circuit incoming video signal.In addition, stop the input of clock signal (S_CLK), clock signal (S_CLK) etc.In other words, shown in accompanying drawing 99, at T GiCan prevent that during this time latch pulse (Latch Pulse) is input in the signal line drive circuit.Because signal is not passed to second latch cicuit 813 from first latch cicuit 812 in this case, therefore can saves with electric charge and charge and discharge.Can reduce power consumption like this.Because at T GiThe data 3405 of not input and latch pulse, so vision signal during this time are not passed to second latch cicuit 813 from first latch cicuit 812.Therefore, the data 3404 with vision signal continue to remain in second latch cicuit 813.Then, at T Gi+1This signal is also outputed to signal wire S1 to Sn during this time.Correspondingly, therefore can reduce power consumption owing to do not need to carry out once more charging and the discharge of signal wire S1 to Sn.Because at T GiSignal is not delivered to second latch cicuit 813 from first latch cicuit 812 during this time, therefore at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Because sampling pulse is not correspondingly from impulse output circuit 811 outputs, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.At T GiDuring this time, can prevent that vision signal (Video Data) is imported in the signal line drive circuit.This be because, at T GiThe vision signal that keeps does not during this time output among the signal wire S1 to Sn, does not therefore need incoming video signal at first.Owing to can save with electric charge through the input that stops vision signal and video line to be charged and discharge, so can reduce power consumption.At T GiDuring this time, can this current potential that be used for reducing power consumption be input to video line.At T GiDuring this time, can prevent that clock signal (S_CLK) and inversion clock signal (S_CLKB) are imported in the signal line drive circuit.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is the H level, and another is the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge, so can reduce power consumption.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion for during parallel, can preventing to import the pulse of the initial pulse signal (S_SP) that is used to trigger beginning holding signal data.In other words, shown in accompanying drawing 100, at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Because sampling pulse is not correspondingly from impulse output circuit 811 outputs, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.Because it is identical with data in remaining on second latch cicuit 813 at first to be delivered to the data of signal of second latch cicuit 813, so when input and latch pulse 3409, carry out the charging and the discharge of second latch cicuit 813 hardly.In addition, because at T Gi+1The data that output to the signal among the signal wire S1 to Sn during this time are at T GiOutput to the data 3404 of the vision signal among the signal wire S1 to Sn during this time, therefore carry out hardly with the charging and the discharge of electric charge to signal wire S1 to Sn.Can reduce power consumption like this.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion for during parallel, can preventing to import the pulse of the initial pulse signal (S_SP) that is used to trigger beginning holding signal data.In addition, stop signal line drive circuit incoming video signal.In other words, shown in accompanying drawing 101, at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Because sampling pulse is not correspondingly from impulse output circuit 811 outputs, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.Because it is identical with data in remaining on second latch cicuit 813 at first to be delivered to the data of signal of second latch cicuit 813, so when input and latch pulse 3409, carry out the charging and the discharge of second latch cicuit 813 hardly.In addition, because at T Gi+1The data that output to the signal among the signal wire S1 to Sn during this time are the data 3404 that output to the vision signal among the signal wire S1 to Sn, therefore carry out hardly with charging and the discharge of electric charge to signal wire S1 to Sn.Can reduce power consumption like this.At T GiDuring this time, can prevent that vision signal (Video Data) is imported in the signal line drive circuit.This be because, at T GiThe vision signal that keeps does not during this time output among the signal wire S1 to Sn, does not therefore need incoming video signal at first.Owing to can save with electric charge through the input that stops vision signal and video line to be charged and discharge, so can reduce power consumption.At T GiDuring this time, can this current potential that be used for reducing power consumption be input to video line.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion for during parallel, can preventing to import the pulse of the initial pulse signal (S_SP) that is used to trigger beginning holding signal data.In addition, stop the input of clock signal (S_CLK), inversion clock signal (S_CLKB) etc.In other words, shown in accompanying drawing 102, at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Because sampling pulse is not correspondingly from impulse output circuit 811 outputs, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.Because it is identical with data in remaining on second latch cicuit 813 at first to be delivered to the data of signal of second latch cicuit 813, so when input and latch pulse 3409, carry out the charging and the discharge of second latch cicuit 813 hardly.In addition, because at T Gi+1The data that output to the signal among the signal wire S1 to Sn during this time are the data 3404 that output to the vision signal among the signal wire S1 to Sn, therefore carry out charging and the discharge of signal wire S1 to Sn hardly.Can reduce power consumption like this.At T GiDuring this time, can prevent that clock signal (S_CLK) and inversion clock signal (S_CLKB) are imported in the signal line drive circuit.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is the H level, and another is the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge, so can reduce power consumption.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
Be used for the vision signal that is stopped the pixel column that signal writes from serial conversion for during parallel, can preventing to import the pulse of the initial pulse signal (S_SP) that is used to trigger beginning holding signal data.In addition, stop signal line drive circuit incoming video signal.In addition, stop the input of clock signal (S_CLK), inversion clock signal (S_CLKB) etc.In other words, show like accompanying drawing 103, at T GiDo not import the pulse of initial pulse signal (S_SP) during this time.Because sampling pulse is not correspondingly from impulse output circuit 811 outputs, so the data 3405 of vision signal do not remain in first latch cicuit 812.Can save like this with electric charge and first latch cicuit 812 is charged and discharge.Because it is identical with data in remaining on second latch cicuit 813 at first to be delivered to the data of signal of second latch cicuit 813, so when input and latch pulse 3409, carry out the charging and the discharge of second latch cicuit 813 hardly.In addition, because at T Gi+1The data that output to the signal among the signal wire S1 to Sn during this time are the data 3404 that output to the vision signal among the signal wire S1 to Sn, therefore carry out hardly with charging and the discharge of electric charge to signal wire S1 to Sn.Can reduce power consumption like this.At T GiDuring this time, can prevent that vision signal (Video Data) is imported in the signal line drive circuit.This be because, at T GiThe vision signal that keeps does not during this time output among the signal wire S1 to Sn, does not therefore need incoming video signal at first.Owing to can save with electric charge through the input that stops vision signal and video line to be charged and discharge, so can reduce power consumption.At T GiDuring this time, can this current potential that be used for reducing power consumption be input to video line.At T GiDuring this time, can prevent that clock signal (S_CLK) and inversion clock signal (S_CLKB) are imported in the signal line drive circuit.For example, can import the set potential of anti-phase between clock signal (S_CLK) and inversion clock signal (S_CLKB) (is the H level, and another is the L level).This is because under the situation of input set potential, do not charge through electric charge and discharge, so can reduce power consumption.Because other class signal is similar to the signal in the accompanying drawing 34, therefore save explanation to them.
(embodiment mode 3)
Subsequently, accompanying drawing 4 is depicted as the synoptic diagram of dot sequency display device.Signal line drive circuit 401 is corresponding to the signal line drive circuit 101 of the display device in the accompanying drawing 1.Therefore other identical parts save the explanation to them through representing with the Reference numeral that Reference numeral is identical in accompanying drawing 1.
Signal line drive circuit 401 comprises impulse output circuit 402, switches set 403 and output control circuit 404.
Clock signal (S_CLK), inversion clock signal (S_CLKB), initial pulse signal (S_SP) etc. all are imported into impulse output circuit 402.Then, export sampling pulse according to the timing of these signals.
Be imported into the switches set 403 from the sampling pulse of impulse output circuit 402 outputs.Vision signal (Video Data) is imported in the corresponding terminal of each switch in switches set 403, and other terminal is connected among corresponding among the signal wire S1 to Sn through output control circuit 404 accordingly.In switches set 403, the switch of corresponding stage is sequentially connected according to the timing of input sample pulse.
Output control signal (S_ENABLE) is imported in the output control circuit 404.Then, confirm whether outputting video signal of output control circuit 404 according to the level of output control signal.Do not outputing to vision signal under the situation of signal wire S1 to Sn from output control circuit 404; Can signal wire S1 to Sn be placed quick condition; Predetermined current potential can be outputed to signal wire S1 to Sn, perhaps can import and the identical signal of signal that is imported into pixel in advance.In other words, can set the current potential that reduces power consumption.In order to reduce power consumption, preferably do not carry out charging and the discharge of signal wire being carried out with electric charge.Because execution is charged with electric charge and discharged when changing current potential, therefore preferably do not change current potential.
Note; When the data that are used for single pixel column and will during the subframe of an image duration, be written to the vision signal of pixel wherein are identical with the data of the vision signal that is written to this pixel column; The output control signal is the signal that is in the L level of outputting video signal not, and the output control signal is the signal that is in the H level of outputting video signal when any part of the data of this pixel column is inequality.
Replacedly, can utilize the structure that output control circuit 404 wherein is not provided.In this case; Be used for single pixel column and will under the data that are written to the vision signal of pixel wherein during the subframe of the image duration situation identical, prevent to be transfused to output and sequentially select the initial pulse signal (S_SP) of the signal of sampling switch to be imported in the switches set 403 with the data of the vision signal that is written to this pixel column.Then, sampling pulse is not from impulse output circuit 402 outputs.Therefore, switches set 403 is not switched on and in all levels, all is in dissengaged positions.Therefore, can signal wire S1 to Sn be placed quick condition.Like this, can save and be used for connecting switches set 403 every grade of charging and discharges that switch is required, therefore can reduce power consumption.In addition, at this moment, the data that preferably prevent to be used for the vision signal of this pixel column are imported into switches set 403, because can reduce power consumption like this.
At this, accompanying drawing 9A has shown applicable to the instance at the signal line drive circuit of the signal line drive circuit 401 of present embodiment pattern mid point sequential display spare.
Comprise impulse output circuit 901, switches set 902 and output control circuit 903 at the signal line drive circuit shown in the accompanying drawing 9A.Clock signal (S_CLK), inversion clock signal (S_CLKB) and initial pulse signal (S_SP) are imported into impulse output circuit 901.According to these signal sequence ground output sampling pulses.
Be input to switches set 902 from the sampling pulse of impulse output circuit 901 outputs, vision signal (Video Data) is input to output control circuit 903 according to the timing of this signal.
In addition, output control signal (S_ENABLE) is imported into output control circuit 903, and whether this signal controlling vision signal is outputed to signal wire S1 to Sn.
Note, not during outputting video signal, can signal wire S1 to Sn placed quick condition or can set set potential at output control circuit 903.As set potential, can set this current potential that is used to reduce power consumption.
Note; Be used for the data of vision signal of this pixel column in during the data that are used for single pixel column and will during a certain subframe of an image duration, be written to the vision signal of pixel wherein and the last subframe when identical; Output control signal (S_ENABLE) is in the L level, and this output control signal is to be in the H level when any part of the data of single row is inequality.
In other words, output control signal (S_ENABLE) when being in the L level not from output control circuit 803 outputting video signals, and when output control signal (S_ENABLE) is in the H level from output control circuit 903 outputting video signals.
Accompanying drawing 9B shows the more detailed structure of signal line drive circuit.In addition, use the operation of the timing diagram explanation signal line drive circuit of accompanying drawing 81.
Impulse output circuit 911 comprises multistage trigger circuit (FF) 914 and AND door 915, and two input terminals of AND door 915 are connected to the lead-out terminal of adjacent trigger circuit (FF) 914.In other words, the trigger circuit (FF) 914 with respect to a redundancy of AND door 915 are provided in every grade, and will be input to every grade the AND door 915 that provides relatively with signal wire S1 to Sn from the output of adjacent trigger circuits (FF) 914.
Note, in accompanying drawing 81, T Gi-1, T GiAnd T Gi+1Be illustrated respectively in during a certain subframe with vision signal be input to (i-1) row, i is capable and (i+1) row in pixel during.Then, the data 8104 of the data 8105 of the data 8106 of vision signal, vision signal and vision signal are respectively at T Gi-1, T GiAnd T Gi+1In be imported into the signal line drive circuit.
At first, explain T Gi+1Operation.Clock signal (S_CLK) and inversion clock signal (S_CLKB) are imported into each trigger circuit (FF) 914, and initial pulse signal (S_SP) is imported into the trigger circuit 914 of the first order.In accompanying drawing 81, pulse 8101 is corresponding to T Gi+1Initial pulse signal.
In the time of in the trigger circuit that are input to next stage 8914, make a pulse of pulse 8101 delay clock signals.Therefore, to output to the output of the AND door 915 of the first order wherein be the frequency of time clock (such as pulse 8102) in the output of the trigger circuit (FF) 914 of the redundant trigger circuit (FF) 914 of the first order and next stage.As sampling pulse Samp.1, in the pulse 8102 CS groups 912 corresponding to the switch connection or the cut-out of pixel in first row.Similarly, the output of the AND door 915 of n row as in sampling pulse Samp.n (such as pulse 8103) the CS group 912 corresponding to the switch connection or the cut-out of n row pixel.
At T Gi+1In, the data 8104 of vision signal are transfused in the switches set 912, connect according to the timing of input sample pulse corresponding to every grade of switch of every row pixel.
Notice that output control signal (S_ENABLE) is imported into output control circuit 913, whether vision signal is outputed to signal wire S1 to Sn is controlled through the level of output control signal.
Note; Be used for the data of vision signal of this pixel column in during the data that are used for single pixel column and will during a certain subframe of an image duration, be written to the vision signal of pixel wherein and the last subframe when identical; Output control signal (S_ENABLE) is in the L level, and this output control signal is to be in the H level when any part of the data of single row is inequality.
In other words; Output control signal (S_ENABLE) when being in the L level not from output control circuit 913 outputting video signals; Because the analog switch that in every grade of output control circuit 913, provides is cut off; And can be from output control circuit 903 outputting video signals, because the analog switch that in every grade, provides is switched on when output control signal (S_ENABLE) is in the H level.
At T Gi+1In, output control signal (S_ENABLE) is the signal that is in the H level, therefore, the analog switch in every grade of output control circuit is in on-state.The vision signal of correspondingly every row pixel is imported in the signal wire of that one-level that is switched on corresponding to switches set 912 wherein.
Attention resembles at T in accompanying drawing 81 Gi+1The same, at T Gi-1Initial pulse signal (S_SP) also is imported in the trigger circuit 914 of the first order during this time.In accompanying drawing 81, pulse 8108 is T Gi-1Initial pulse signal.Then, the data 8106 of outputting video signal from output control circuit 913.
Yet, in accompanying drawing 81 at T GiDo not import initial pulse signal during this time.Therefore, do not produce sampling pulse, cut off the switch in every grade of switches set 912, disconnect them.Therefore, the data 8105 of vision signal are not input in the output control circuit 913.
In addition, output control signal (S_ENABLE) is in the L level.Therefore, the analog switch that in every grade of output control circuit 913, provides is cut off.Therefore, signal wire S1 to Sn is placed in quick condition.
In other words, owing to the data of the signal that is input to the capable pixel of i are identical with the data 8105 of this vision signal, therefore, stop the signal of the capable pixel of i is write.Save the charging of signal wire etc. and discharge to reduce power consumption.
Note, output control circuit 913 needn't be provided.This is because at T GiDo not import initial pulse signal (S_SP) during this time, so every grade switch in the switches set 912 disconnects all, and be placed in quick condition.
In addition, can stop the vision signal that is used for being stopped the pixel column that signal writes is input to the signal line drive circuit.In other words, shown in accompanying drawing 82, at T GiCan prevent during this time vision signal (Video Data) is input in the signal line drive circuit.In addition, at T GiCan import this current potential that is used to reduce power consumption during this time.Because other class signal is similar to the signal in the accompanying drawing 81, therefore save explanation to them.
In addition, be used for the vision signal that is stopped the pixel column that signal writes can be stopped the input that clock signal is waited until the signal line drive circuit.In other words, shown in accompanying drawing 83, at T GiCan prevent during this time clock signal (S_CLK) and inversion clock signal (S_CLKB) are input in the signal line drive circuit.Because other class signal is similar to the signal in the accompanying drawing 81, therefore save explanation to them.
In addition, be used for the vision signal that is stopped the pixel column that signal writes can be stopped vision signal, clock signal etc. is input to the signal line drive circuit.In other words, shown in accompanying drawing 84, at T GiCan prevent during this time clock signal (S_CLK), inversion clock signal (S_CLKB) and vision signal (Video Data) are input in the signal line drive circuit.Because other class signal is similar to the signal in the accompanying drawing 81, therefore save explanation to them.
Note, be not limited to these applicable to the signal line drive circuit of display device of the present invention.In other words; Be used under pixel and will be in the data of the vision signal that is written to said pixel during a certain subframe of an image duration identical with the data of the signal that is written to this pixel column situation of pixel column, the signal of when non-selected this pixel column, not carrying out this pixel column writes.Therefore, can use such structure, wherein can this current potential maintenance that the signal maintenance that be imported into the pixel in advance is input to this signal wire or will be used to reduce power consumption be input to this signal wire.
(embodiment pattern 4)
In the present embodiment pattern, another structure applicable to the peripheral driver circuit (such as scan line driver circuit or signal line drive circuit) of the display device described in the embodiment pattern 1 to 3 is described.
The structure of scan line driver circuit that can be suitable for display device of the present invention is shown in the accompanying drawing 5A.
At first, comprise impulse output circuit 501 and buffering circuit 502 in the scan line driver circuit shown in the accompanying drawing 5A.Clock signal (G_CLK), inversion clock signal (G_CLKB), initial pulse signal (G_SP) etc. are input in the impulse output circuit 501.Then, sweep signal (SC.1 to SC.m) is imported in the buffer circuit 502 according to the timing of these signals.Sweep signal converts the pixel selection signal (G.1 to G.m) with high electric current deliverability into and is imported into sweep trace G1 to Gm through buffer circuit 502.At this, output control signal (G_ENABLE) is imported in the buffer circuit 502.Then, output control signal (G_ENABLE) is carried out control so that stop the sweep trace input that will be stopped the pixel column that signal writes at the pixel selection signal signal to the G.m G.1.
More detailed structure example is shown in the accompanying drawing 5B.
Impulse output circuit 511 comprises multistage trigger circuit (FF) 513 and AND door 514, and two input terminals of AND door 514 are connected to the lead-out terminal of adjacent trigger circuit (FF) 513.In other words, the trigger circuit (FF) 513 with respect to a redundancy of AND door 514 are provided in every grade, and will be input to the AND door 514 of the corresponding stage that provides relatively with sweep trace G1 to Gm from the output of adjacent trigger circuits (FF) 513.
Clock signal (G_CLK) and inversion clock signal (G_CLKB) are input to each trigger circuit (FF) 513, and initial pulse signal (G_SP) is input to the trigger circuit 513 of the first order.In the time of in the trigger circuit that are input to next stage 513, make a pulse of initial pulse signal delay clock signals.The pulse of AND door 514 its outputs of first row of output of trigger circuit 513 that therefore, will be transfused to redundant trigger circuit 513 and the next stage of the first order is a pulse of clock signal.This pulse is input to the input terminal with the output control circuit 512 corresponding buffer circuits 515 of the first order as sweep signal SC.1.The output of the AND door 514 that the output of the AND door 514 that similarly, i is capable and m are capable is input to a corresponding input terminal of every grade the buffer circuit 515 of output control circuit 512 respectively as sweep signal.
In addition, every grade the buffer circuit 515 of output control circuit 512 comprises that the output control terminal that output control signal (G_ENABLE) is input to wherein is sub.The output control signal converts the pixel selection signal (G.1 to G.m) with high electric current deliverability into through output control circuit 512, and these signals are imported among the sweep trace G1 to Gm.At this, output control signal (G_ENABLE) is imported in every grade of output control circuit 512.Then, confirm according to the output control signal whether the pixel selection signal (G.1 to G.m) of the electric current deliverability generation through improving sweep signal (SC.1 to SC.m) outputs in every grade of output control circuit 512.
Notice that the instance of buffer circuit with output control circuit is shown in the accompanying drawing 5C.P channel transistor 521 is connected in series with p channel transistor 522 and n channel transistor 523 and n channel transistor 524.High power supply potential Vdd is set the source terminal that can get at p channel transistor 521, and low power supply potential Vss is set to the source terminal of n channel transistor 524.Output control signal (G_ENABLE) is input to the gate terminal of n channel transistor 524, and the inversion signal of the output control signal (G_ENABLE) that produces through phase inverter 525 is input to the gate terminal of p channel transistor 521.In addition, the gate terminal of p channel transistor 522 and n channel transistor 523 is connected to each other, and sweep signal (any signal among the SC.1 to SC.m) is input to wherein.At this; Because n channel transistor 524 is switched on p channel transistor 521 when output control signal (G_ENABLE) is in the H level, so inversion signal any output from p channel transistor 522 or n channel transistor 523 of sweep signal (any signal among the SC.1 to SC.m).On the other hand and since output control signal (G_ENABLE) when being in the L level n channel transistor 524 be cut off with p channel transistor 521, signal is not exported from the buffering circuit, and the sweep trace that is connected to buffer circuit is placed in quick condition.Notice that the level of sweep signal (SC.1 to SC.m) and pixel selection signal under the situation of accompanying drawing 5C (G.1 to G.m) is by anti-phase.Therefore, in every grade, can additionally provide the odd number phase inverter such as a phase inverter.In this case, the phase inverter that additionally provides can be positioned on the input side of the buffer circuit shown in the accompanying drawing 5C.This is because in the time of on the outgoing side that is positioned at the buffer circuit shown in the accompanying drawing 5C, when the input of the phase inverter that additionally provides is placed in quick condition, the output of sweep trace is become unstable.
In addition, explanation is applicable to the structure example of another scan line driver circuit of display device of the present invention.
At first, comprise impulse output circuit 701, buffer circuit 702 and output control circuit 703 in the scan line driver circuit shown in the accompanying drawing 7A.Clock signal (G_CLK), inversion clock signal (G_CLKB), initial pulse signal (G_SP) etc. are input to impulse output circuit 701.Then, sweep signal (SC.1 to SC.m) is input in the buffer circuit 702 according to the timing of these signals.Sweep signal (SC.1 to SC.m) converts the pixel selection signal (G.1 to G.m) with electric current deliverability into through buffer circuit 702, and these signals are imported into output control circuit 703.At this, output control signal (G_ENABLE) is input to output control circuit 703.Then, output control signal (G_ENABLE) is carried out control and so that stop the sweep trace output pixel that will be stopped the pixel column that signal writes is selected the G.1 signal to the G.m of signal.
More detailed structure is shown in the accompanying drawing 7B.Impulse output circuit 711 comprises multistage trigger circuit (FF) 714 and AND door 715, and two input terminals of AND door 715 are connected to the lead-out terminal of adjacent trigger circuit (FF) 714.In other words, the trigger circuit (FF) 714 with respect to a redundancy of AND door 715 are provided in every grade, and will be input to every grade the AND door 715 that provides relatively with sweep trace G1 to Gm from the output of adjacent trigger circuits (FF) 714.
Clock signal (G_CLK) and inversion clock signal (G_CLKB) are input to each trigger circuit (FF) 714, and initial pulse signal (G_SP) is input to the trigger circuit 714 of the first order.In the time of in the trigger circuit that are input to next stage 714, make a pulse of initial pulse signal delay clock signals.The pulse of AND door 715 its outputs of first row of output of trigger circuit 714 of trigger circuit 714 and next stage that therefore, will be transfused to the redundancy of the first order is a pulse of clock signal.This pulse is input to the input terminal corresponding to the buffer circuit (Buf.) 716 of first order output control circuit 712 as sweep signal SC.1.The output of the AND door 715 that the output of the AND door 714 that similarly, i is capable and m are capable is input to a corresponding input terminal of every grade the buffer circuit 716 of buffer circuit 712 respectively as sweep signal.
The buffer circuit 716 of the corresponding stage in buffer circuit 712 and be connected to each other through the switch 717 of the corresponding stage in output control circuit 713 with its corresponding scanning line G1 to Gm.Each switch 717 comprises control terminal, and output control signal (G_ENABLE) is input to this control terminal.Then, confirm whether outputed in the impact damper 712 of corresponding stage according to output control signal (G_ENABLE) through the pixel selection signal (G.1 to G.m) that the electric current deliverability that improves sweep signal (SC.1 to SC.m) produces.At this, for example, when the buffer circuit 716 of the first order is exported, control signal (G_ENABLE) in pixel selection signal pulse G.1 and be under the situation of L level, first order switch 717 is cut off.Therefore, the sweep trace G1 that is connected to first order switch is placed in quick condition.On the other hand, the pulse of pixel selection signal (G.1 to G.m) during from buffer circuit 716 outputs of all grades output control signal (G_ENABLE) be under the situation of H level, one vertical during in the switch 717 of all grades of connection.Therefore, pixel selection signal (G.1 to G.m) sequentially is input to sweep trace G1 to Gm.
Replacedly, can be used as scan line driver circuit in the structure shown in the accompanying drawing 35A.
The scanning line selection data are imported into decoder circuit 3501, are exported corresponding to the pulse signal of the pixel column of selecting through these data.Then, the signal that has improved the electric current deliverability through buffer circuit 3502 is outputed to any one among the G1 to Gm as pixel selection signal.
More detailed structure is shown in the accompanying drawing 35B.At this, select the instance of the situation of 16 sweep traces according to four scanning line selection data descriptions.
Decoder circuit 3511 comprises the AND door 3513 that provides corresponding to the sweep trace G1 to G16 that selects pixel column.In addition, four scanning line selection data (Input 1 to 4) are input in the decoder circuit 3511.Each AND door 3513 is selected the various combination be made up of Input 1 or its oppisite phase data, Input 2 or its oppisite phase data, Input 3 or its oppisite phase data and Input 4 or its oppisite phase data.Like this, can at random select 16 sweep trace G1 to G16 according to four inputs.
Notice that the scan line driver circuit of display device of the present invention is not limited to above-mentioned structure.For example, it can comprise level shifter.Note the level of level shifter movable signal.
For example; In the structure of accompanying drawing 11A; Output from impulse output circuit 501 is imported into level shifter 1101, and the output of level shifter 1101 is imported into buffer circuit 502, selects the signal of pixel sequentially to be input to sweep trace G1 to Gm from buffering circuit 502.This structure is through level shifter 1101 being increased to the structure that obtains in the structure of accompanying drawing 5A.For illustrated in detail, 5A makes an explanation with reference to accompanying drawing.
In addition; In the structure of accompanying drawing 11B; Output from impulse output circuit 601 is imported into output control circuit 602; The output of output control circuit 602 is imported into level shifter 1102, and the output of level shifter 1102 is imported into buffer circuit 603, selects the signal of pixel sequentially to be input to sweep trace G1 to Gm from buffering circuit 603.This structure is through level shifter 1102 being increased to the structure that obtains in the structure of accompanying drawing 6A.For illustrated in detail, 6A makes an explanation with reference to accompanying drawing.
In addition; In the structure of accompanying drawing 11C; Output from impulse output circuit 701 is imported into level shifter 1103; The output of level shifter 1103 is imported into buffer circuit 702, and the output of buffer circuit 702 is imported into output control circuit 703, selects the signal of pixel sequentially to be input to sweep trace G1 to Gm from output control circuit 703.This structure is through level shifter 1103 being increased to the structure that obtains in the structure of accompanying drawing 7A.For illustrated in detail, 7A makes an explanation with reference to accompanying drawing.
In addition; In the structure of accompanying drawing 11D; Output from decoder circuit 3501 is imported into level shifter 1104, and the output of level shifter 1104 is imported into buffer circuit 3502, selects the signal of pixel sequentially to be input to sweep trace G1 to Gm from buffering circuit 3502.This structure is through level shifter 1104 being increased to the structure that obtains in the structure of accompanying drawing 35A.For illustrated in detail, 35A makes an explanation with reference to accompanying drawing.
As indicated above, the scan line driver circuit of various structures can be applicable in the display device of the present invention.In other words, scan line driver circuit can have any structure, as long as when the signal that will be input to pixel column is identical with the signal that is input to this pixel column, do not select to be connected to the pixel column of a sweep trace.In other words, the signal that is input to the sweep trace that is connected with pixel column can be the signal that is in the L level that is used for not selecting pixel, perhaps can sweep trace be placed quick condition.
In addition, accompanying drawing 77A and 77B have shown the signal line drive circuit that has with embodiment pattern 2 described accompanying drawing 8 structure various structure, and the sort signal line driver circuit can be suitable for capable sequential display spare of the present invention.
The signal line drive circuit that in accompanying drawing 77A, shows comprises impulse output circuit 7701, output control circuit 7702, first latch cicuit 7703 and second latch cicuit 7704.Clock signal (S_CLK), inversion clock signal (S_CLKB) and initial pulse signal (S_SP) are input to impulse output circuit 7701.According to these signal sequence ground output sampling pulses.
Be input to output control circuit 7702 from the sampling pulse of impulse output circuit 7701 outputs.In addition, output control signal (S_ENABLE) is imported into output control circuit 7702, and whether this signal controlling is input to first latch cicuit 7703 with sampling pulse.
At this; When be used for single pixel column and will a certain subframe an image duration during be written to the vision signal of pixel wherein data and last subframe during in be used for the data of vision signal of this pixel column when identical; Output control signal (S_ENABLE) is in the L level, and the output control signal is in the H level when any part of the data of single row is inequality.
Then, when the output control signal (S_ENABLE) that is imported into output control circuit 7702 is in the H level, the output sampling pulse.Therefore, sampling pulse is imported into first latch cicuit 7703, according to the timing of this signal vision signal (Video Data) is remained in first latch cicuit 7703.When the maintenance of vision signal is accomplished to the afterbody in first latch cicuit 7703; During horizontal flyback sweep latch pulse (Latch Pulse) is input in second latch cicuit 7704, the vision signal that will in first latch cicuit 7703, keep simultaneously is passed to second latch cicuit 7704.
On the other hand, sampling pulse is not exported from output control circuit 7702 when output control signal (S_ENABLE) is in the L level, and this vision signal is not latched in first latch cicuit 7703.Can reduce power consumption like this.
After this, the signal that is input to second latch cicuit 7704 is imported into signal wire S1 to Sn.
Notice that vision signal is not latched in first latch cicuit 7703 when output control signal (S_ENABLE) is in the L level.After this, still keep input to be used for the vision signal of going ahead of the rest.Therefore, the data that keep at second latch cicuit 7704 are also identical with the vision signal that is used for going ahead of the rest.Yet at this moment signal is not written in the pixel, because scan line driver circuit is not selected this pixel.Can reduce power consumption like this.In addition, because each signal wire is recharged and discharges, the signal that therefore from second latch cicuit 7704, is input to signal wire S1 to Sn does not consume very big power.
Accompanying drawing 77B has shown the more detailed structure of signal line drive circuit.
Impulse output circuit 7711 passes through to use multistage trigger circuit (FF) 7715 formation such as grade, and clock signal (S_CLK), inversion clock signal (S_CLKB) and initial pulse signal (S_SP) are input to wherein.Sampling pulse is sequentially exported in timing according to these signals.Note, in the structure of accompanying drawing 77B, form impulse output circuit 7711 with trigger circuit 7715: wherein when being input to the trigger circuit of next stage, make initial pulse signal (S_SP) postpone a pulse at every turn with this spline structure; Yet, can use the structure of above-mentioned texture ratio like the impulse output circuit in accompanying drawing 52 5211.
Be imported into output control circuit 7712 from the sampling pulse of impulse output circuit 7711 outputs.In addition, output control signal (S_ENABLE) is imported into output control circuit 7712, and whether this signal controlling is input to first latch cicuit 7713 with sampling pulse.
At this; When be used for single pixel column and will a certain subframe an image duration during be written to the vision signal of pixel wherein data and last subframe during in be used for the data of vision signal of this pixel column when identical; Output control signal (S_ENABLE) is in the L level, and the output control signal is in the H level when any part of the data of single row is inequality.
Then, when the output control signal (S_ENABLE) that is imported into output control circuit 7712 is in the H level, the output sampling pulse.Therefore, sampling pulse is imported among every grade the LAT 1 of first latch cicuit 7713, according to the timing of this signal vision signal (Video Data) is remained in first latch cicuit 7713.When the maintenance of vision signal is accomplished to the afterbody in first latch cicuit 7713; During horizontal flyback sweep latch pulse (Latch Pulse) is input in second latch cicuit 7714, the vision signal that will in first latch cicuit 7713, keep simultaneously is passed to second latch cicuit 7714.
On the other hand, sampling pulse is not exported from output control circuit 7712 when output control signal (S_ENABLE) is in the L level, and this vision signal is not latched in first latch cicuit 7713.Can reduce power consumption like this.
After this, the signal that is input to second latch cicuit 7714 is imported into signal wire S1 to Sn.
Notice that vision signal is not latched in first latch cicuit 7713 when output control signal (S_ENABLE) is in the L level.After this, still keep input to be used for the vision signal of going ahead of the rest.Therefore, the data of second latch cicuit, 7714 maintenances are also identical with the vision signal that is used for going ahead of the rest.Yet at this moment signal is not written in the pixel, because scan line driver circuit is not selected this pixel.Can reduce power consumption like this.In addition, because each signal wire is recharged and discharges, the signal that therefore from second latch cicuit 7714, is input to signal wire S1 to Sn does not consume very big power.
In addition, accompanying drawing 78A and 78B show the signal line drive circuit with the structure that is different from the accompanying drawing of describing in the embodiment mode 39, and the sort signal line driver circuit can be suitable for dot sequency display device of the present invention.
The signal line drive circuit that in accompanying drawing 78A, shows comprises impulse output circuit 7801, output control circuit 7802 and switches set 7803.Clock signal (S_CLK), inversion clock signal (S_CLKB) and initial pulse signal (S_SP) are input to impulse output circuit 7801.According to these signal sequence ground output sampling pulses.
Be input to output control circuit 7802 from the sampling pulse of impulse output circuit 7801 outputs.In addition, output control signal (S_ENABLE) is imported into output control circuit 7802, and whether this signal controlling is input to switches set 7803 with sampling pulse.
At this; When be used for single pixel column and will a certain subframe an image duration during be written to the vision signal of pixel wherein data and last subframe during in be used for the data of vision signal of single row when identical; Output control signal (S_ENABLE) is in the L level, and the output control signal is in the H level when any part of the data of single row is inequality.
Then, when the output control signal (S_ENABLE) that is imported into output control circuit 7802 is in the H level, the output sampling pulse.Therefore, sampling pulse is imported into switches set 7803, according to the timing of this signal, connects every grade switch of switches set 7803.When connecting the switch of the switches set 7803 of one-level to the last, the vision signal of single pixel column is outputed to signal wire S1 to Sn.
On the other hand, sampling pulse is not exported from output control circuit 7802 when output control signal (S_ENABLE) is in the L level, and every grade switch of switches set 7803 still keeps cutting off and disconnecting.Therefore signal wire S1 to Sn is placed quick condition, and it is not charged and discharge.Can reduce power consumption like this.
Accompanying drawing 78B has shown the more detailed structure of signal line drive circuit.
Impulse output circuit 7811 forms through using multistage trigger circuit (FF) 7814 grades, and clock signal (S_CLK), inversion clock signal (S_CLKB) and initial pulse signal (S_SP) are input to wherein.Sampling pulse is sequentially exported in timing according to these signals.Note, in the structure of accompanying drawing 78B, form impulse output circuit 7811 with trigger circuit 7814: wherein when being input to the trigger circuit of next stage, make initial pulse signal (S_SP) postpone a pulse at every turn with this spline structure; Yet, can use the structure of above-mentioned texture ratio like the impulse output circuit in accompanying drawing 52 5211.
Be imported into output control circuit 7812 from the sampling pulse of impulse output circuit 7811 outputs.In addition, output control signal (S_ENABLE) is imported into output control circuit 7812, and whether this signal controlling is input to switches set 7813 with sampling pulse.
At this; When be used for single pixel column and will a certain subframe an image duration during be written to the vision signal of pixel wherein data and last subframe during in be used for the data of vision signal of this pixel column when identical; Output control signal (S_ENABLE) is in the L level, and the output control signal is in the H level when any part of the data of single row is inequality.
Then, when the output control signal (S_ENABLE) that is imported into output control circuit 7812 is in the H level, the output sampling pulse.Therefore, sampling pulse is connected every grade switch of switches set 7813.When the switch up to the last level of switches set 7813 all is switched on, the vision signal of single pixel column is outputed to signal wire S1 to Sn.
On the other hand, sampling pulse is not exported from output control circuit 7812 when output control signal (S_ENABLE) is in the L level, and the switch of each grade of switches set 7813 still keeps cutting off and disconnecting.Therefore, S1 to Sn places quick condition with signal wire, and it is not charged and discharge.Can reduce power consumption like this.
(embodiment pattern 5)
In the present embodiment pattern, explain pixel and driving method thereof applicable to the display device of describing in the embodiment pattern 1.In other words, explain the pixel and the driving method thereof of the display device of gray level method service time.
Hereinafter is explained the dot structure applicable to the display device of embodiment pattern 1.Notice that self luminous display element is suitable for conduct at accompanying drawing 10,13 such as EL element, 15,16,17,18, the display element of the pixel shown in 19,21,47,53 and 67.Notice that each in them all only shown single pixel, but in the pixel portion of display device, have a plurality of pixels on line direction and column direction, to arrange with matrix-style.
Comprise driver transistor 1001, switching transistor 1002, capacitor element 1003, display element 1004, sweep trace 1005, signal wire 1006 and power lead 1007 in the pixel shown in the accompanying drawing 10.The gate terminal of switching transistor 1002 is connected to sweep trace 1005; Its first terminal (in source terminal and the drain terminal one) is connected to signal wire 1006, and its second terminal (another in source terminal and the drain terminal) is connected to the gate terminal of driver transistor 1001.In addition, second terminal of switching transistor 1002 is connected to power lead 1007 through capacitor element 1003.In addition, the first terminal of driver transistor 1001 (in source terminal and the drain terminal) is connected to power lead 1007, and its second terminal (another in source terminal and the drain terminal) is connected to first electrode of display element 1004.Low power supply potential is set to second electrode 1008 of display element 1004.Notice that based on the high power supply potential that is set to power lead 1007, low power supply potential is the current potential that satisfies the relation of low power supply potential＜high power supply potential, GND for example, 0V etc. can be set to low power supply potential.Owing to make display element 1004 emission light through the potential difference (PD) between high power supply potential and the low power supply potential being applied to display element 1004 and making electric current flow to display element 1004, so each current potential is configured to make potential difference (PD) between high voltage potential and the low power supply potential to be equal to or greater than the forward threshold voltage of display element 1004.Notice that the grid capacitance through driver transistor 1001 alternatively can be saved capacitor element 1003.The grid capacitance of driver transistor 1001 can be formed in the zone in wherein source area, drain region and LDD district etc. and gate electrode or can be formed between channel region and the gate electrode.
When selecting pixel through sweep trace 1005, promptly when switching transistor 1002 was in on-state, vision signal was input to this pixel from signal wire 1006.Then, be accumulated in the capacitor element 1003 corresponding to the electric charge of the voltage of vision signal, capacitor element 1003 keeps these voltages.This voltage is at the gate terminal of driver transistor 1001 and the voltage between the first terminal, and it is corresponding to the gate source voltage Vgs of driver transistor 1001.
Usually, transistorized workspace is divided into linear zone and saturation region.The border is satisfied (Vgs-Vth)=Vds when, and Vds representes drain-source voltage here, and Vgs representes gate source voltage, and Vth representes threshold voltage.Under the situation that satisfies (Vgs-Vth)＞Vds, transistor is operated in linear zone, and its current value depends on the amplitude of Vds and Vgs.On the other hand, under the situation that satisfies (Vgs-Vth)＜Vds, transistor is operated in the saturation region, ideally, even its current value is also almost constant when Vds changes.In other words, current value depends on the amplitude of Vgs.
At this, under the situation of voltage input voltage driving method, vision signal is input to the gate terminal of driver transistor 1001 so that driver transistor 1001 is placed in any in the two states of connecting fully and cutting off.In other words, driver transistor 1001 is operated in linear zone.
Therefore, be that the power supply potential Vdd that is set to power lead 1007 is set to first electrode of display element 1004 ideally, and does not do any change when connecting the signal of driver transistor 1001 in vision signal.
In other words, ideally, make the voltage constant that is applied to display element 1004, therefore make the brightness constancy that obtains from display element 1004.Then, in an image duration, a plurality of subframes are provided during, therefore it is luminous and not luminous with control pixel during each subframe vision signal to be written to pixel in during each subframe, according to the summation expression gray scale during the luminous subframe of pixel wherein.
Subsequently, the dot structure of figures 13.Comprise driver transistor 1301, switching transistor 1302, current control transistor 1309, capacitor element 1303, display element 1304, sweep trace 1305, signal wire 1306, power lead 1307 and distribution 1310 in the pixel shown in the accompanying drawing 13.The gate terminal of switching transistor 1302 is connected to sweep trace 1305; Its first terminal (in source terminal and the drain terminal one) is connected to signal wire 1306, and its second terminal (another in source terminal and the drain terminal) is connected to the gate terminal of driver transistor 1301.In addition, second terminal of switching transistor 1302 is connected to power lead 1307 through capacitor element 1303.In addition; The first terminal of driver transistor 1301 (in source terminal and the drain terminal one) also is connected to power lead 1307, and its second terminal (another in source terminal and the drain terminal) is connected to the first terminal (in source terminal and the drain terminal) of current control transistor 1309.Second terminal of current control transistor 1309 (another in source terminal and the drain terminal) is connected to first electrode of display element 1304, and its gate terminal is connected to distribution 1310.In other words, driver transistor 1301 all is connected in series with current control transistor 1309.Notice that low power supply potential is set to second electrode 1308 of display element 1304.Notice that based on the high power supply potential that is set to power lead 1307, low power supply potential is the current potential that satisfies the relation of low power supply potential＜high power supply potential, GND for example, 0V etc. can be set to low power supply potential.
In this dot structure, current control transistor 1309 is operated in the saturation region when pixel is luminous, constant electric current is flowed to display element 1304.In other words, the current potential of distribution 1310, power lead 1307 and second electrode 1308 all is set to and makes gate source voltage Vgs and drain-source voltage Vds satisfy (Vgs-Vth)＜Vds.Notice that Vth representes the threshold voltage of current control transistor 1309.Therefore, ideally, even its current value is almost constant when Vds changes.In other words, current value only depends on the amplitude of Vgs; Therefore, current value is confirmed by the current potential that is set to power lead 1307 and distribution 1310.Notice that the grid capacitance through driver transistor 1301 substitutes, and can delete capacitor element 1303.
When selecting pixel through sweep trace 1305, promptly when switching transistor 1302 was in on-state, vision signal was input to this pixel from signal wire 1306.Then, be accumulated in the capacitor element 1303 corresponding to the electric charge of the voltage of vision signal, capacitor element 1303 keeps these voltages.This voltage is at the gate terminal of driver transistor 1301 and the voltage between the first terminal, and it is corresponding to the gate source voltage Vgs of driver transistor 1301.
Then, incoming video signal is so that the Vgs of driver transistor 1301 is placed in any in the two states of connecting fully and cutting off.In other words, driver transistor 1301 is operated in linear zone.
Therefore, be that the power supply potential Vdd that is set to power lead 1307 is set to the first terminal of current control transistor 1309 ideally, and does not do any change when connecting the signal of driver transistor 1301 in vision signal.At this moment, the first terminal of current control transistor 1309 is source terminals, and the electric current that is transported to display element 1304 is confirmed by the gate source voltage of the current control transistor of setting through distribution 1310 and power lead 1,307 1309.
In other words, ideally, make the current constant that is applied to display element 1304, therefore make the brightness constancy that obtains from display element 1304.Then, in an image duration, a plurality of subframes are provided during, therefore it is luminous and not luminous with control pixel during each subframe vision signal to be written to pixel in during each subframe, according to the summation expression gray scale during the luminous subframe of pixel wherein.
The dot structure of figures 15 subsequently.Comprise driver transistor 1501, switching transistor 1502, capacitor element 1503, display element 1504, first sweep trace 1505, signal wire 1506 and power lead 1507, rectifier element 1509 and second sweep trace 1510 in the pixel shown in the accompanying drawing 15.The gate terminal of switching transistor 1502 is connected to first sweep trace 1505; Its first terminal (in source terminal and the drain terminal one) is connected to signal wire 1506, and its second terminal (another in source terminal and the drain terminal) is connected to the gate terminal of driver transistor 1501.In addition, the gate terminal of driver transistor 1501 is connected to second sweep trace 1510 through rectifier element 1509.In addition, second terminal of switching transistor 1502 is connected to power lead 1507 through capacitor element 1503.In addition, the first terminal of driver transistor 1501 (in source terminal and the drain terminal) is connected to power lead 1507, and its second terminal (another in source terminal and the drain terminal) is connected to first electrode of display element 1504.Low power supply potential is set to second electrode 1508 of display element 1504.Notice that based on the high power supply potential that is set to power lead 1507, low power supply potential is the current potential that satisfies the relation of low power supply potential＜high power supply potential, GND for example, 0V etc. can be set to low power supply potential.Owing to make display element 1504 emission light through the potential difference (PD) between high power supply potential and the low power supply potential being applied to display element 1504 and making electric current flow to display element 1504, so each current potential is configured to make potential difference (PD) between high voltage potential and the low power supply potential to be equal to or greater than the forward threshold voltage of display element 1504.Notice that the grid capacitance through driver transistor 1501 alternatively can be deleted capacitor element 1503.
This dot structure is the structure that in the pixel of accompanying drawing 10, increases rectifier element 1509 and 1510 acquisitions of second sweep trace.Therefore, driver transistor 1501, switching transistor 1502, capacitor element 1503, display element 1504, first sweep trace 1505, signal wire 1506 and power lead 1507 correspond respectively to driver transistor 1001, switching transistor 1002, capacitor element 1003, display element 1004, sweep trace 1005, signal wire 1006 and the power lead 1007 of the pixel in the accompanying drawing 10.Because write operation and light emission operation are similar, therefore save explanation to them.
Hereinafter is explained erase operation.When erase operation, the H level signal is input to second sweep trace 1510.Then, electric current flows to rectifier element 1509, and the grid potential of the driver transistor 1501 that will keep through capacitor element 1503 is set to a certain current potential.In other words, the current potential of the gate terminal of driver transistor 1501 can be set to a certain current potential, forces driver transistor 1501 to cut off, and irrelevant with the vision signal that is written to this pixel.
Notice that the transistor that the diode mode connects can be used as rectifier element 1509.In addition, the transistor that the alternative diode modes such as diode that can use PN-knot or PIN-junction diode, schottky diode, form with CNT connect.The transistorized situation of the n raceway groove that application diode mode connects is shown in Figure 16.The first terminal of the transistor 1601 that the diode mode connects (in source terminal and the drain terminal one) is connected to the gate terminal of driver transistor 1501, and second terminal of the transistor 1601 that the diode mode connects (another in source terminal and the drain terminal) is connected to the gate terminal and second sweep trace 1510.Then; When second sweep trace 1510 is in the L level; Electric current does not flow, because the gate terminal of the transistor 1601 that the diode mode connects is connected with source terminal, and when the signal of H level is input to second sweep trace 1510; Electric current flow to the transistor 1601 that the diode mode connects, and this is because second terminal of the transistor 1601 that the diode mode connects is drain terminals.Therefore, the transistor that connects of diode mode 1601 performance rectified actions.
In addition, it is shown in Figure 17 to use the situation of the p channel transistor that the diode mode connects.The first terminal of the transistor 1701 that the diode mode connects (in source terminal and the drain terminal one) is connected to second sweep trace 1510.In addition, second terminal (another in source terminal and the drain terminal) of the transistor 1701 that connects of diode mode is connected to the gate terminal of its gate terminal and driver transistor 1501.Then; When second sweep trace 1510 is in the L level; Electric current does not flow, because the gate terminal of the transistor 1701 that the diode mode connects is connected with source terminal, and when the signal of H level is input to second sweep trace 1510; Electric current flows, and this is because second terminal of the transistor 1701 that the diode mode connects is drain terminals.Therefore, the transistor that connects of diode mode 1701 performance rectified actions.Note; In the time will being used for non-luminous vision signal and being written to pixel, the signal that be input to the L level of second sweep trace 1510 is set to have and does not allow electric current to flow to the current potential of the transistor 1701 that transistor 1601 that rectifier element 1509, diode mode connect is connected with the diode mode.The signal that in addition, be input to the H level of second sweep trace 1510 is set to such current potential: the current potential that cuts off driver transistor 1501 can be set to gate terminal and be irrelevant with the vision signal that is written to this pixel.
In addition, can provide erasing transistor to wipe the signal that is written to pixel.Have through adding the erasing transistor 1809 and second sweep trace 1810 to obtain in the pixel of accompanying drawing 10 structure in the pixel shown in the accompanying drawing 18.Therefore, driver transistor 1801, switching transistor 1802, capacitor element 1803, display element 1804, first sweep trace 1805, signal wire 1806 and power lead 1807 correspond respectively to driver transistor 1001, switching transistor 1002, capacitor element 1003, display element 1004, sweep trace 1005, signal wire 1006 and the power lead 1007 of the pixel in the accompanying drawing 10.Because write operation and light emission operation are similar, therefore save explanation to them.
Hereinafter is explained erase operation.When erase operation, the H level signal is input to second sweep trace 1810.Then, connect erasing transistor 1809, can make the current potential equalization of the gate terminal and the first terminal of driver transistor 1801.In other words, the gate source voltage of driver transistor 1801 can be 0V.Notice, it is desirable to that the current potential of the H level of second sweep trace 1810 is than the threshold voltage vt h of the high erasing transistor 1809 of current potential of power lead 1807 or bigger.Like this, can force driver transistor to cut off.
In addition, rectifier element and erasing transistor can be applied to the dot structure shown in accompanying drawing 13.As an example, wherein the structure that is added in the pixel of accompanying drawing 13 of rectifier element is shown in Figure 19.In the structure of accompanying drawing 19, the gate terminal of driver transistor 1301 is connected to second sweep trace 1902 through rectifier element 1901.Because write operation and light emission operation are similar to the explanation of accompanying drawing 13, therefore save its description at this.
Hereinafter is explained erase operation.When erase operation, the H level signal is input to second sweep trace 1902.Then, electric current flows to rectifier element 1901, and the grid potential of the driver transistor 1301 that will keep through capacitor element 1303 is set to a certain current potential.In other words, the current potential of the gate terminal of driver transistor 1301 can be set to a certain current potential, forces driver transistor 1301 to cut off, and irrelevant with the vision signal that is written to this pixel.Like this, force this pixel to be in not luminance.Notice that the p channel transistor that n channel transistor that the diode mode connects or diode mode connect all can be used as rectifier element 1901.
Through second sweep trace being provided and selecting second sweep trace will make pixel place the signal of luminance not to be input under the situation of gate terminal of driver transistor; Shown in accompanying drawing 15 to 19, for example can use structure at the display device shown in the accompanying drawing 74.
This display device comprises signal line drive circuit 7401, first scan line driver circuit 7402, second scan line driver circuit 7405 and pixel portion 7403.In addition, a plurality of pixels 7404 are with respect to providing with matrix-style pixel portion 7403 from the first sweep trace G1 to Gm and the second sweep trace R1 to Rm of first scan line driver circuit 7402 and 7405 extensions of second scan line driver circuit respectively from the signal wire S1 to Sn of signal line drive circuit 7401 extensions with at line direction at column direction.
Signal is imported in first scan line driver circuit 7402 such as clock signal (G_CLK), inversion clock signal (G_CLKB) and initial pulse signal (G_SP).According to these signals, a signal is outputed to the first sweep trace Gi (any one among the first sweep trace G1 to Gm) in the pixel column of selecting.Then, select wherein will carry out the pixel column that signal writes.
In addition, signal is imported in second scan line driver circuit 7405 such as clock signal (R_CLK), inversion clock signal (R_CLKB) and initial pulse signal (R_SP).According to these signals, a signal is outputed to the second sweep trace Ri (any one among the second sweep trace R1 to Rm) in the pixel column of selecting.Then, select wherein will carry out the pixel column that signal is wiped.
In addition, signal is imported in the signal line drive circuit 7401 such as clock signal (S_CLK), inversion clock signal (S_CLKB), initial pulse signal (S_SP) and vision signal (Digital Video Data).According to these signals, will output in each among the signal wire S1 to Sn corresponding to the vision signal of the pixel of every row.
Therefore, the vision signal that is input to signal wire S1 to Sn is written in the pixel 7404 of every row in the pixel column of selecting through the signal that is input to the first sweep trace Gi (any one among the first sweep trace G1 to Gm).Each pixel column is through every scanning line selection among the first sweep trace G1 to Gm, is written in all pixels 7404 corresponding to the vision signal of each pixel 7404.Each pixel 7404 keep being written to the data of vision signal wherein certain during.Then, each pixel 7404 can be through the data that keep vision signal certain during keep luminous or luminance not.
At this, the display device of present embodiment pattern is to use the display device of time gray level method, and the luminous and not luminous of each pixel 7404 controlled through the signal data that is written to each pixel 7404 in this method, and gray scale is with the length control of fluorescent lifetime.Note, be used for intactly showing a viewing area image during be called as an image duration, display device of the present invention comprises a plurality of subframes in an image duration during.Length during each subframe in a such image duration can be roughly the same or different.In other words, during each subframe of an image duration in control each pixel 7404 luminous and not luminous, gray scale is controlled through the difference of the T.T. of the fluorescent lifetime of each pixel 7404.
In addition, the display device of present embodiment pattern is included in the output control circuit in signal line drive circuit 7401, first scan line driver circuit 7402 and second scan line driver circuit 7405.In other words; When the data of the vision signal of the single pixel column that during being used for a certain subframe an image duration, pixel execution signal is write or wipes were identical with the data of the vision signal of the single row that is written to this pixel column, the output control circuit of first scan line driver circuit 7402 or second scan line driver circuit 7405 was not exported the signal that is used to select this pixel column.In other words, be used for not selecting the L signal of pixel column to be imported into the sweep trace of this pixel column, perhaps the sweep trace with this pixel column places quick condition.In addition, also outputting video signal not of the output control circuit of signal line drive circuit 7401.The output of signal line drive circuit 7401 can be with pixel place luminance signal or can be that pixel is placed the not signal of luminance.Can import the signal of the least possible power of this consumption.Replacedly, can signal wire S1 to Sn be placed quick condition.
Therefore, the display device according to the present embodiment pattern focuses on (being directed against) a certain pixel column, when the signal that is input to this pixel column is identical with the signal that will import, can prevent this signal is input to this pixel column.Therefore, can reduce sweep trace and signal wire are implemented the number of times of charging and discharge, so can reduce power consumption.
Under the situation of the dot structure of accompanying drawing 21, force this pixel to be in not luminance and rectifier element is not provided.For example, in the dot structure of accompanying drawing 13, provide second sweep trace 2101 to substitute distribution 1310, the gate terminal of current control transistor 1309 is connected to second sweep trace 2101.Irrelevant in order to make pixel be in not luminance with the vision signal that is written to this pixel, the signal of H level is input to second sweep trace 2101.Then, current control transistor 1309 is cut off; Therefore, can pixel be placed not luminance and irrelevant with the vision signal that is written to this pixel.Notice that constant current potential is set to second sweep trace 2101, and makes the current constant that flows to current control transistor 1309, but except when making pixel be in not luminance.
Subsequently, the pixel of figures 47.The pixel of accompanying drawing 47 comprises current source circuit 4701, switch 4702, display element 4703, signal holding device 4704 and power lead 4705.
The pixel electrode of display element 4703 is connected to power lead 4705 through switch 4702 and current source circuit 4701.
Notice that the luminous and non-luminous signal of control pixel is imported into the signal holding device 4704 of holding signal.Then, switch on or off by this Signal-controlled switch 4702.
In addition, set the opposite electrode 4706 be set to display element 4703 and power lead 4705 current potential in case can be normally in current source circuit 4701 supply have electric current through the current value of programming.
According to this dot structure, through in current source circuit 4701, constant current value being programmed and can steady current be continuously delivered to display element 4703.Therefore, can improve the luminous variation of each pixel.In addition, even the I-E characteristic of display element 4703 is owing to temperature variation changes, electric current that still can delivered constant.The brightness that therefore, can suppress the display element 4703 relevant with temperature variation changes.
In addition, display element 4703 is along with the time deterioration, and I-E characteristic changes.Yet, owing in this dot structure, can be transferred steady current, therefore can suppress and variation along with the brightness of the relevant display element 4703 of time deterioration.In addition, if along with the deterioration of time continues to take place, then electric current-light characteristic changes.In other words, even when the electric current with same electrical flow valuve is flow through, the brightness of the display element 4703 of deterioration is lower than the not brightness of the display element 4703 of deterioration.Therefore, in this pixel, with become along with the time that the bad brightness that is associated reduces can be through suppressing according to the current value in the display element 4703 being programmed along with change of time.
The instance of the basic structure of pixel is shown in the accompanying drawing 53 in the accompanying drawing 47.This pixel comprises driver transistor 5301, switching transistor 5302, capacitor element 5303, display element 5304, sweep trace 5305, signal wire 5306, power lead 5307 and current source circuit 5309.
The gate terminal of switching transistor 5302 is connected to sweep trace 5305; Its first terminal (in source terminal and the drain terminal one) is connected to signal wire 5306, and its second terminal (another in source terminal and the drain terminal) is connected to the gate terminal of driver transistor 5301.In addition, second terminal of switching transistor 5302 (another in source terminal and the drain terminal) is connected to power lead 5307 through capacitor element 5303.In addition; The first terminal of driver transistor 5301 (in source terminal and the drain terminal one) is connected to power lead 5307 through current source circuit 5309, and its second terminal (another in source terminal and the drain terminal) is connected to first electrode of display element 5304.Low power supply potential is set to second electrode 5308 of display element 5304.Notice that based on the high power supply potential that is set to power lead 5307, low power supply potential is the current potential that satisfies the relation of low power supply potential＜high power supply potential, GND for example, 0V etc. can be set to low power supply potential.Can make have in the current source circuit 5309 through the programming current value so that the potential setting of the electric current of proper flow is high power supply potential and low power supply potential.Notice that the grid capacitance through driver transistor 5301 alternatively can be saved capacitor element 5303.The grid capacitance of driver transistor 5301 can be formed in the zone in wherein source area, drain region and LDD district etc. and gate electrode or can be formed between channel region and the gate electrode.
Hereinafter is explained the operation of this dot structure.When selecting this pixel through sweep trace 5305, promptly when switching transistor 5302 was in on-state, vision signal was input to this pixel from signal wire 5306.Then, electric charge is accumulated in the capacitor element 5303, and capacitor element 5303 keeps the grid voltage of driver transistor 5301.
Usually, transistorized workspace is divided into linear zone and saturation region.The border is satisfied (Vgs-Vth)=Vds when, and Vds representes drain-source voltage here, and Vgs representes gate source voltage, and Vth representes threshold voltage.Under the situation that satisfies (Vgs-Vth)＞Vds, transistor is operated in linear zone, and its current value depends on the amplitude of Vds and Vgs.On the other hand, under the situation that satisfies (Vgs-Vth)＜Vds, transistor is operated in the saturation region, ideally, even its current value is also almost constant when Vds changes.In other words, current value only depends on the amplitude of Vgs.
At this, under the situation of this structure, driver transistor 5301 is operated in linear zone.Vision signal be imported into driver transistor 5301 gate terminal so that the two states that driver transistor 5301 is placed in abundant connection and cut-out in any.
Therefore, be when connecting the signal of driver transistor 5301 in vision signal, with having first electrode that is not set to display element 5304 through the electric current of the current value of programming in the current source circuit 5309 with not carrying out any change.
In other words, make the current constant that is applied to display element 5304, therefore make the brightness constancy that obtains from display element 5304.Then, in an image duration, a plurality of subframes are provided during, therefore it is luminous and not luminous with control pixel during each subframe vision signal to be written to pixel in during each subframe, according to the summation expression gray scale during the luminous subframe of pixel wherein.
In addition, detailed structure example is shown in the accompanying drawing 67.This structure comprises driver transistor 6701, switching transistor 6702, first capacitor element 6703, display element 6704, sweep trace 6705, signal wire 6706, power lead 6707, current source transistor 6712, second capacitor element 6713, first switch 6714 and second switch 6715.
The gate terminal of switching transistor 6702 is connected to sweep trace 6705; Its first terminal (in source terminal and the drain terminal one) is connected to signal wire 6706, and its second terminal (another in source terminal and the drain terminal) is connected to the gate terminal of driver transistor 6701.In addition, second terminal of switching transistor 6702 (another in source terminal and the drain terminal) is connected to power lead 6707 through first capacitor element 6703.In addition, the first terminal of driver transistor 6701 (in source terminal and the drain terminal) is connected to the first terminal (in source terminal and the drain terminal) of power transistor 6712.Then, second terminal of current source transistor 6712 (another in source terminal and the drain terminal) is connected to power lead 6707.In addition, the first terminal of current source transistor 6712 is connected to power lead 6711 through second switch 6715.Second terminal of current source transistor 6712 is connected to its gate terminal through first switch 6714.Second capacitor element 6713 is connected between the gate terminal and the first terminal of current source transistor 6712.In addition, power lead 6711 is connected to distribution 6716 through current source 6710.
In this structure, comprise the current source circuit 5309 of the current source circuit 6709 of current source transistor 6712, second capacitor element 6713, first switch 6714 and second switch 6715 corresponding to the pixel in the accompanying drawing 53.Since identical to the signal writing operation of pixel with light emission operation, therefore save its description.Therefore, explain programming at this to current source circuit 6709.
With current programmed when the current source circuit 6709, first switch 6714 is switched on second switch 6715.Then, the electric current in inflow current source 6710 is propagated to flow to second capacitor element 6713 and current source transistor 6712 instantaneously.Under steady state (SS), the electric current in inflow current source 6710 flows to current source transistor 6712.Then, make mobile being accumulated in the capacitor element 6713 of electric current at the gate terminal of current source transistor 6712 and the electric charge of the voltage between the first terminal (in other words, the voltage Vgs between gate terminal and source terminal).
In this state, first switch 6714 is cut off with second switch 6715.Like this, keep through capacitor element 6713 at the gate terminal of current source transistor 6712 and the voltage Vgs between the source terminal.Then, completion is to the programming of current source circuit 6709.In other words, when driver transistor 6701 is connected, the electric current of the electric current that is substantially equal to streaming current source 6710 is flow in the display element 6704.
Notice that various pixel can be applied in the display device of present embodiment pattern, and the invention is not restricted to above-mentioned pixel.
Subsequently, explanation is applicable to the driving method of the display device of describing in the embodiment pattern 1.
At first, explain the driving method that (during keeping) separated between (address period) and light emission period during the signal that makes to pixel write with reference to accompanying drawing 14.At this, explain the situation of 4-bit digital time gray scale as an example.
Note, be used for intactly showing a viewing area image during be called as an image duration.Comprise during a plurality of subframes an image duration, during comprising address period during the sub-frame and keeping.Address period Ta1 to Ta4 representes signal is written to the required time of pixel in all row, during Tb1 to Tb4 represent signal is written to pixel (or single pixel) required time of single row.In addition, Ts1 to Ts4 representes to keep luminous or time of luminance not according to the vision signal that is written to pixel during keeping, and its length ratio is set to and satisfies Ts1: Ts2: Ts3: Ts4=2 3: 2 2: 2 1: 2 0=8: 4: 2: 1.Gray scale according to performed keeping during luminous expression.
The hereinafter interpreter operation.At first, in address period Ta1, be about to pixel selection signal from first and sequentially be input to sweep trace to select pixel.Then, when selecting pixel, vision signal is imported this pixel from signal wire.When vision signal was written to this pixel, pixel kept this signal up to input signal once more.According to the vision signal that writes, control luminous and not luminous among the Ts1 during keeping of each pixel.In a similar fashion, at address period Ta2, Ta3 and Ta4 are input to pixel with vision signal, and according to this vision signal each pixel of control Ts2 during keeping, luminous and not luminous among Ts3 and the Ts4.During each subframe, pixel is not luminous in address period, and beginning during after address period finishes, keeping makes that the pixel that writes luminous signal is luminous.
At this; In display device of the present invention; The vision signal of in the pixel of single row, in the address period during the subframe formerly, importing with during subframe subsequently under the identical situation of the vision signal of input, stop in during subframe subsequently the signal of the pixel of single row is write.
Note the data of the same delegation pixel in during the signal data in relatively during first subframe of an image duration and the last subframe in it previous image duration.When the data of the signal of the pixel in this row are identical, this signal is not written in the pixel of this row in during first subframe of an image duration.
Therefore, can reduce with electric charge and charge and discharge, therefore can reduce power consumption.
For example; Through in image duration subsequently, preventing to be used for selecting the signal of pixel to be imported into sweep trace, can save distribution cross capacitance with the sweep trace that is connected to pixel in this row and charge through electric charge with the transistorized grid capacitance that is connected to this sweep trace and discharge.Therefore, can keep not select the signal of pixel to continue to be input in this sweep trace, perhaps this sweep trace placed quick condition.
In addition, during subframe subsequently in, charge and this current potential that discharges is input to signal wire and can reduces power consumption through signal wire being placed quick condition or will be used for reduce in during the signal to this row pixel writes with electric charge.As reducing this current potential that charges and discharge with electric charge, can the signal that just in time is written to before the pixel of single row be input in this signal wire with not doing any change.
Note, explain the situation of expressing 4-position gray scale at this, but figure place and gray level are not limited to this.In addition, luminous order needs not be Ts1, Ts2, Ts3 and Ts4, this order can be at random or through be divided into carry out during the keeping during a plurality of luminous.
Notice that this driving method can be used for for example comprising the display device of the pixel shown in pixel shown in the accompanying drawing 10 or the accompanying drawing 13.In address period Ta1 to Ta4; The current potential of second electrode 1008 of display element 1004 or second electrode 1308 of display element 1304 can be set to higher than the current potential in during keeping, and can be set at the forward threshold voltage that is equal to or less than display element 1004 or display element 1304.Replacedly, can second electrode 1308 of display element 1304 be placed quick condition.
(during keeping) indiscrete driving method between (address period) and light emission period during the hereinafter explanation wherein makes the signal of pixel write.In other words, the pixel of wherein having accomplished in the row of write operation of vision signal keeps this signal to write (or wiping) up to next signal of carrying out this pixel.During next signal writing operation, be called as data hold time from write operation to pixel.Then, in data hold time, place luminous pixel or luminance not according to the vision signal that is written to pixel.Carry out identical operations delegation to the last, then, address period finishes.Then, operation sequentially proceeds to the signal writing operation of next son image duration from the row beginning of wherein data hold time end.
Just in time pixel is placed under the situation luminous and the not driving method between light emission period according to the vision signal that is written in the pixel after beginning having accomplished signal writing operation and data hold time therein; Can not simultaneously signal be input in two row, and need prevent that address period is overlapping.Therefore, even attempt to make data hold time shorter, still can not make data hold time shorter than address period.As a result, become and be difficult to carry out senior gray scale and show.
Therefore, set data hold time shorter through providing between erasing period than address period.Use accompanying drawing 20A explain through provide between erasing period data hold time set than address period the driving method under the shorter situation.
In address period Ta1, from first row to sweep trace sequentially the input scan signal to select pixel.Then, when selecting pixel, vision signal is input to this pixel from signal wire.When vision signal was input to this pixel, pixel kept this signal up to input signal once more.According to the vision signal that writes, control Ts1 luminous and not luminous during keeping of each pixel.In other words, in the row of the write operation of having accomplished vision signal, place luminous this pixel or luminance not immediately according to the vision signal that writes.Carry out identical operations delegation to the last, address period Ta1 finishes.Then, the row beginning from wherein data hold time end proceeds to said sequence of operation the next son signal writing operation of image duration.In a similar fashion,, among Ta3 and the Ta4 vision signal is input to pixel, and according to this vision signal each pixel of control Ts2 during keeping, Ts3 and Ts4's is luminous and not luminous at address period Ta2.Then, through erase operation begin to set keep during the termination of Ts4.This be because, in the erasing time of every row Te, wipe the signal that is written to pixel, force pixel to be in not luminance and write up to next pixel is carried out signal, and with address period in to be written to the vision signal of pixel irrelevant.In other words, the pixel since the row of erasing time Te begins the data hold time end.
Therefore, can provide and have the data hold time shorter, high-grade gray level and high duty ratio the display device of (between light emission period with an image duration ratio) than address period, and need not with address period with keep during separately.Instantaneous brightness in addition, can improve the reliability of display element, because can be lowered.
At this; In display device of the present invention; When be used for single pixel column and will a certain subframe an image duration during the data of data that are written to the vision signal of pixel wherein and the vision signal that is written to this pixel column when identical, stop the signal of the pixel of this single row is write.In other words, this driving method is more suitable when the senior gray scale of execution shows.When the senior gray scale of execution shows, increase pixel is implemented the number of times that signal writes.Therefore, the same with the situation of display device of the present invention, can reduce power consumption through reducing the number of times of implementing charging and discharge.
Note, explain the situation of expressing 4-position gray scale at this, but figure place and gray level are not limited to this.In addition, luminous order needs not be Ts1, Ts2, Ts3 and Ts4, this order can be at random or through be divided into carry out during the keeping during a plurality of luminous.
Can carry out the erase operation that is used to begin the above-mentioned erasing time through second sweep trace 1902 in the structure of second sweep trace 1810 in the structure of second sweep trace 1510 in the structure that signal is input to accompanying drawing 15 to 17, accompanying drawing 18 or accompanying drawing 19 through selecting pixel.
The instance of display device with this pixel is shown in the accompanying drawing 74.This display device comprises signal line drive circuit 7401, first scan line driver circuit 7402, second scan line driver circuit 7405 and pixel portion 7403; In pixel portion 7403, pixel 7404 is arranged with matrix form with respect to the first sweep trace G1 to Gm, the second sweep trace R1 to Rm and signal wire S1 to Sn.
Notice that the first sweep trace Gi (any one among the first sweep trace G1 to Gm) is corresponding to first sweep trace 1505 of accompanying drawing 15,16 or 17, first sweep trace 1805 of accompanying drawing 18 or first sweep trace 1305 of accompanying drawing 19.The second sweep trace Ri (any one among the second sweep trace R1 to Rm) is corresponding to second sweep trace 1510 of accompanying drawing 15,16 or 17, second sweep trace 1810 of accompanying drawing 18 or second sweep trace 1902 of accompanying drawing 19.Signal wire Sj (any one among the signal wire S1 to Sn) is corresponding to first sweep trace 1506 of accompanying drawing 15,16 or 17, the signal wire 1806 of accompanying drawing 18 or the signal wire 1306 of accompanying drawing 19.
Signal is imported in first scan line driver circuit 7402 such as clock signal (G_CLK), inversion clock signal (G_CLKB), initial pulse signal (G_SP) and output control signal (G_ENABLE).According to these signals, a signal is outputed to the first sweep trace Gi (any one among the first sweep trace G1 to Gm) with selecteed pixel column.
In addition, signal is imported in second scan line driver circuit 7405 such as clock signal (R_CLK), inversion clock signal (R_CLKB), initial pulse signal (R_SP) and output control signal (R_ENABLE).According to these signals, a signal is outputed to the second sweep trace Ri (any one among the second sweep trace R1 to Rm) with selecteed pixel column.
In addition, signal is imported in the signal line drive circuit 7401 such as clock signal (S_CLK), inversion clock signal (S_CLKB), initial pulse signal (S_SP), vision signal (Digital Video Data) and output control signal (R_ENABLE).According to these signals, will output in each among the signal wire S1 to Sn corresponding to the vision signal of the pixel of every row.
Therefore, the vision signal that is input to signal wire S1 to Sn is written in the pixel 7404 in the every row of selecting through the signal that is input to the first sweep trace Gi (any one among the first sweep trace G1 to Gm) at pixel column.Then, each pixel column is selected through among the first sweep trace G1 to Gm each, is written in all pixels 7404 corresponding to the vision signal of each pixel 7404.Each pixel 7404 keep being written to the data of vision signal wherein certain during.Each pixel 7404 can be through the data that keep vision signal certain during keep luminous or luminance not.
In addition, place the signal of luminance (being also referred to as erase signal) not to be written to the pixel of selecting through the signal that is input to the second sweep trace Ri (any one of the second sweep trace R1 to Rm) 7404 pixel at every row of pixel column.Then, through each selects each pixel column can set not luminance among the second sweep trace R1 to Rm.For example, in accompanying drawing 20, erasing time Te is (horizontal period) during a gating in the second sweep trace Ri is selected.
In addition, display device of the present invention comprises the output control circuit that is arranged in signal line drive circuit 7401, first scan line driver circuit 7402 and second scan line driver circuit 7405.
In other words; Show the data be used for single pixel column and will during a certain subframe of an image duration, be written to the vision signal of pixel wherein whether with the identical information of data of the signal that is written to this pixel column (vision signal or erase signal), be sent out to first scan line driver circuit 7402 and through exporting control signal (S_ENABLE) through output control signal (G_ENABLE) and send to signal line drive circuit 7401.The pixel of the single row that this erase signal will be selected through second scan line driver circuit during the subframe formerly places not luminance.When data were identical, the output control circuit of first scan line driver circuit 7402 was not exported the signal that is used to select this pixel column.In other words, do not select the L signal of this pixel column to be imported in first sweep trace of this pixel column, perhaps first sweep trace of this pixel column is placed in quick condition.In addition, also outputting video signal not of the output control circuit of signal line drive circuit 7401.The output of signal line drive circuit 7401 can be used for pixel place luminance signal or can be that pixel is placed the not signal of luminance.Can import the signal of this power that maybe be little that runs out.In addition, can signal wire S1 to Sn be placed quick condition.
The data of signal of pixel that are wiped free of the single pixel column of signal in during being written to a certain subframe an image duration are to be used under non-luminous situation, through output control signal (G_ENABLE) this information are sent to second scan line driver circuit 7405.Then, the output control circuit that prevents second scan line driver circuit 7405 is exported the signal that is used to select this pixel column.In other words, will be used for not selecting the L signal of this pixel column to be input to second sweep trace of this pixel column, perhaps second sweep trace with this pixel column places quick condition.Also prevented the output control circuit outputting video signal of signal line drive circuit 7401.
Therefore,, focus on a certain pixel column, when the signal that is input to this pixel column is identical with the signal that will import, can prevent this signal is input to this pixel column according to display device of the present invention.Therefore, can reduce sweep trace and signal wire are implemented the number of times of charging and discharge, so can reduce power consumption.
In addition; Write time through being provided for write operation in the horizontal period shown in accompanying drawing 20B and the erasing time that is used for erase operation, data hold time is shorter than under the situation of address period gray level and can uses the dot structure expression in the accompanying drawing 10 in like accompanying drawing 20A.For example, a horizontal period is divided into during two, shown in accompanying drawing 37.At this, before supposing partly be the write time and later half be to make an explanation under the prerequisite in erasing time.In divided horizontal period, select each sweep trace 1005, at this moment, corresponding signal is input to signal wire 1006.For example, during certain level preceding half in select i capable, and selection j is capable in later half.Then, as if executable operations has selected two row the same in a horizontal period simultaneously.In other words, use preceding half the said write time, in write time Tb1 to Tb4, vision signal is written to the pixel from signal wire 1006 as each horizontal period.Then, at this moment in the later half erasing time, do not select pixel as a horizontal period.In addition, use the later half said erasing time, in erasing time Te, erase signal is input to the pixel from signal wire 1006 as another horizontal period.At this moment in preceding half write time, do not select pixel as a horizontal period.According to this mode, the display device with higher aperture ratio can be provided and can improve output.
At this; In display device of the present invention; When be used for single pixel column and will a certain subframe an image duration during be written to the vision signal of pixel wherein the data of data and the signal that is written to this pixel column (vision signal or erase signal) when identical, stop the vision signal of the pixel of this single row is write.To be when being used for that this pixel placed the signal of luminance not to the data that pixel is imported the signal (vision signal or erase signal) of the single pixel column of erase signal, stop input the erase signal of the pixel of this single row.When the senior gray scale of execution shows, increase pixel is implemented the number of times that signal writes or wipes.Yet through reducing the number of times of implementing charging and discharge, display device of the present invention can reduce power consumption.In other words, this driving method is more suitable when the senior gray scale of execution shows.
The instance of display device that comprises this pixel is shown in the accompanying drawing 75.This display device comprises signal line drive circuit 7501, first scan line driver circuit 7502, second scan line driver circuit 7505 and pixel portion 7503; In pixel portion 7503, pixel 7504 is arranged with matrix form with respect to sweep trace G1 to Gm and signal wire S1 to Sn.
First scan line driver circuit 7502 comprises impulse output circuit 7506, output control circuit 7507 and switches set 7510.
Second scan line driver circuit 7505 comprises impulse output circuit 7509, output control circuit 7508 and switches set 7511.
Notice that sweep signal Gi (any one among the sweep trace G1 to Gm) is corresponding to the sweep trace 1005 of accompanying drawing 10, signal Sj (any one among the signal wire S1 to Sn) is corresponding to the signal wire 1006 of accompanying drawing 10.
Signal is imported in first scan line driver circuit 7502 such as clock signal (G_CLK), inversion clock signal (G_CLKB), initial pulse signal (G_SP), output control signal (G_ENABLE) and control signal (WE).According to these signals, be used for selecting the signal of pixel to be outputed to the first sweep trace Gi (any one among the first sweep trace G1 to Gm) of the pixel column that will select.Note, at this moment this signal be a horizontal period in timing diagram, being shown like accompanying drawing 37 preceding half in pulse export.
In addition, signal is imported in second scan line driver circuit 7505 such as clock signal (R_CLK), inversion clock signal (R_CLKB), initial pulse signal (R_SP), output control signal (R_ENABLE) and control signal (WE).According to these signals, a signal is outputed to the second sweep trace Ri in the selecteed pixel column (any one among the second sweep trace R1 to Rm).Notice that at this moment this signal is that pulse in a horizontal period in the timing diagram like accompanying drawing 37, being shown later half is exported.
In addition, signal is imported in the signal line drive circuit 7501 such as clock signal (S_CLK), inversion clock signal (S_CLKB), initial pulse signal (S_SP), vision signal (Digital Video Data) and output control signal (S_ENABLE).According to these signals, will output to corresponding to the vision signal of every row pixel in each among the signal wire S1 to Sn.
Therefore, the vision signal that is input to signal wire S1 to Sn is written in the pixel of selecting through the signal that is input to the first sweep trace Gi (any one among the first sweep trace G1 to Gm) 7504 in every row of pixel column.Then, each pixel column is selected through among the first sweep trace G1 to Gm each, is written in all pixels 7504 corresponding to the vision signal of each pixel 7504.Each pixel 7504 keep being written to the data of vision signal wherein certain during.Each pixel 7504 can be through the data that keep vision signal certain during keep luminous or luminance not.
In addition, place the signal of luminance (being also referred to as erase signal) not to be written to the pixel 7504 of the every row of selecting through the signal that is input to sweep trace Gi (any one of sweep trace G1 to Gm) of pixel column pixel from signal wire S1 to Sn.Then, select each pixel column can set not luminance through each sweep trace G1 to Gm.For example, in accompanying drawing 20, wherein the capable pixel of i is erasing time Te through the time that is input to the signal selection the sweep trace Gi from second scan line driver circuit 7505.
In addition, display device of the present invention comprises the output control circuit that is arranged in signal line drive circuit 7501, first scan line driver circuit 7502 and second scan line driver circuit 7505.In other words; Show the data be used for single pixel column and will during a certain subframe of an image duration, be written to the vision signal of pixel wherein whether with the identical signal of data of the signal that is written to this pixel column (vision signal or erase signal); Be transfused to first scan line driver circuit 7502 through output control signal (G_ENABLE); Input to second scan line driver circuit 7505 through output control signal (R_ENABLE), and input to signal line drive circuit 7501 through output control signal (S_ENABLE).When data are identical, prevent that the output control circuit of first scan line driver circuit 7502 and second scan line driver circuit 7505 from exporting the signal that is used to select this pixel column.In other words, do not select the L signal of this pixel column to be imported in the sweep trace of this pixel column, perhaps the sweep trace of this pixel column is placed in quick condition.In addition, also prevent the output control circuit outputting video signal of signal line drive circuit 7501.The output of signal line drive circuit 7501 can be used for pixel place luminance signal or can be that pixel is placed the not signal of luminance.Can import the signal of this power that maybe be little that runs out.In addition, can signal wire S1 to Sn be placed quick condition.
Therefore,, focus on a certain pixel column, when the signal that is input to this pixel column is identical with the signal that will import, can prevent this signal is input to this pixel column according to display device of the present invention.Therefore, can reduce sweep trace and signal wire are implemented the number of times of charging and discharge, so can reduce power consumption.
Notice that the dot structure of display device of the present invention is not limited to above-mentioned structure, can also use various dot structures.In addition, driving method of the present invention also is not limited to above-described driving method, can also use various driving methods.
Note,, when the data of the data of the signal that will be written into single pixel column and the signal of the single file that is written to this pixel column are identical, stop the signal of the pixel of this single row is write according to display device of the present invention.Therefore, the number of times of implementing charging and discharge can be reduced, therefore power consumption can be reduced.
Particularly, the quantity increase in subframe can further reduce power consumption to carry out when senior gray scale shows.
Notice that the structure of accompanying drawing 51 can be applicable to the scan line driver circuit of the display device of present embodiment pattern.
Comprise impulse output circuit 5101, output control circuit 5102, buffer circuit 5103 and switches set 5104 in the scan line driver circuit shown in the accompanying drawing 51.Impulse output circuit 5101 comprises multistage trigger circuit (FF) 5105 and AND door 5106, and two input terminals of AND door 5106 are connected to the lead-out terminal of adjacent trigger circuit (FF) 5105.In other words, the trigger circuit (FF) 5105 with respect to a redundancy of AND door 5106 are provided in every grade, and will be input to every grade the AND door 5106 that provides relatively with sweep trace G1 to Gm from the output of adjacent trigger circuits (FF) 5105.
Clock signal (G_CLK) and inversion clock signal (G_CLKB) are input to each trigger circuit (FF) 5105, and initial pulse signal (G_SP) is input to the trigger circuit 5105 of the first order.In the time of in the trigger circuit that are input to next stage 5105, initial pulse signal (G_SP) is by a pulse of delay clock signals.The pulse of AND door 5106 its outputs of first row of output of trigger circuit 5105 of trigger circuit 5105 and next stage that therefore, will be transfused to the redundancy of the first order is a pulse of clock signal.This pulse is input to an input terminal corresponding to the AND door 5107 of the first order of output control circuit 5102 as sweep signal SC.1.The output of the AND door 5106 that the output of the AND door 5106 that similarly, i is capable and m are capable is input to the corresponding input terminal of AND door 5107 of the corresponding stage of output control circuit 5102 respectively as sweep signal.Output control signal (G_ENABLE) is imported into another input terminal of the AND door 5106 of output control circuit 5102.According to output control signal (G_ENABLE), determine whether the output scanning signal.At this, for example, output control signal (G_ENABLE) is under the situation of L level when the pulse of the 5106 output scanning signals of the AND door from the first order, and the output of the AND door 5107 of the first order is in the L level.On the other hand, output control signal (G_ENABLE) is under the situation of H level the pulse of output scanning signal sequentially from output control circuit 5102 when the pulse of the 5106 output scanning signals of the AND door from all grades.
Be imported into every grade the impact damper 5108 of buffer circuit 5103 from the sweep signal of output control circuit 5102 outputs, and as the pixel selection signal output with high electric current deliverability.
Partly or between latter half be transferred to sweep trace G1 to Gm at the preceding of a horizontal period from the pixel selection signal of buffering circuit 5103 outputs through switches set 5104.In other words, every grade the switch 5109 of switches set 5104 partly or between latter half is switched at the preceding of a horizontal period.
(embodiment pattern 6)
In the present embodiment pattern, explain the primary structure of display device of the present invention.At first, the calcspar with reference to accompanying drawing 2 makes an explanation.This structure be when be used for single pixel column and will a certain subframe an image duration during be written to the vision signal of pixel wherein data and last subframe during in be used for the data of vision signal of this pixel column and stop the display device that the signal to this pixel writes when identical.
At analog video signal (Analog Video Data) when being imported into analog-digital converter circuit 201; It is converted into digital video signal (Digital Video Data), and this digital video signal is input to the memory write selection circuit 202 from analog-digital converter circuit 201.
In memory write was selected circuit 202, the digital video signal of a frame was divided into the data that are used for each subframe, and according to the signal from display controller 207 inputs be written into the frame memory A 203 or frame memory B 204 in.Note, in accompanying drawing 2, SF1, SF2 and SF3 are as the subframe demonstration in each of frame memory A 203 and frame memory B 204, but the quantity of subframe is not limited to this.
In addition, confirm circuit 205 according to the signal of input from display controller 207 in each of frame memory A 203 and frame memory B 204, relatively be input to corresponding to have be used for pixel write vision signal formerly and the data of the vision signal of the pixel of the single row during the subframe regularly of back.Then, show that write control signal that whether data be input to the vision signal in the single row of pixels mate is imported into memory read and selects in circuit 206 and the display controller 207.
According to the signal from display controller 207, memory read is selected circuit 206 to read a frame of digital vision signal that is written to frame memory A 203 or frame memory B 204 and this vision signal is input in the display controller 207.At this; Demonstration be input to have the corresponding single row of pixels formerly and during the subframe regularly of back that the pixel of being used to writes vision signal in the signal of Data Matching of vision signal be imported under the situation in the memory read selection circuit 206; This memory read is selected circuit 206 being written to stop in the frame of digital vision signal among frame memory A 203 or the frame memory B 204 to the reading of the vision signal of single row of pixels in during subframe subsequently, and irrelevant with the signal from display controller 207.
In addition; Display controller 207 is with initial pulse signal (G_SP; S_SP), clock signal (G_CLK, S_CLK), the output control signal (G_ENABLE, S_ENABLE), driving voltage, vision signal (Digital Video Data) etc. are input in the display 208.
In other words; Be used in during the data that are used for pixel column and will during a certain subframe of an image duration, be written into the vision signal of pixel wherein and the last subframe under the identical situation of the data of vision signal of this pixel column; Prevent the initial pulse signal (S_SP) of display controller 207 outputs, so that prevent to export the sampling pulse that is used for the vision signal of this pixel column is converted into from serial data parallel data corresponding to this pixel column.In addition, display controller 207 will be used to control that (G_ENABLE S_ENABLE) is input in the display 208 from the sweep signal of scan line driver circuit and the output control signal of whether being exported from the vision signal of signal line drive circuit.
Note, at the display 208 of accompanying drawing 2 corresponding to wherein such display board: wherein the pixel pixel portion of arranging with matrix-style and the peripheral driver circuit (such as scan line driver circuit and signal line drive circuit) of this pixel portion all are formed on the substrate.Notice that in display board, the peripheral driver circuit can be formed on the IC chip and be installed on the substrate through COG (glass top chip) etc., perhaps the pixel portion on peripheral driver circuit and the substrate integrates.Notice that the IC chip means such chip: wherein electronic circuit is formed with on the surface that is included in Semiconductor substrate or dielectric substrate or at the element of the inner semiconductor element of Semiconductor substrate.Note, also be called as semi-conductor chip through the circuitous pattern on the silicon wafer being cured the IC chip of making.
Then, explain the primary structure of another display device.Calcspar with reference to shown in the accompanying drawing 23 makes an explanation.
At analog video signal (Analog Video Data) when being imported in the analog-digital converter circuit 2301; It is converted into digital video signal (Digital Video Data), and this digital video signal is input to the memory write selection circuit 2302 from analog-digital converter circuit 2301.
In memory write was selected circuit 2302, the digital video signal of a frame was divided into the data that are used for each subframe, and according to the signal from display controller 2307 inputs be written into the frame memory A 2303 or frame memory B 2304 in.Note, in accompanying drawing 23, SF1, SF2 and SF3 illustrate as the subframe in each of frame memory A 2303 and frame memory B 2304, but the quantity of subframe is not limited to this.
According to the signal from display controller 2307, memory read is selected circuit 2306 to read a frame of digital vision signal that is written to frame memory A 2303 or frame memory B 2304 and this vision signal is input in the line storage 2309.
The signal that which pixel column that is used for display frame storer A 2303 or frame memory B 2304 and the data of which subframe are imported into line storage 2309 is imported into from display controller 2307 confirms circuit 2305.According to this signal, the data of the pixel in the same lines of the pixel data of single row and subframe are formerly compared.Then, be used for showing that the write control signal whether data of the vision signal of the pixel that is imported into single row mate is imported into line storage 2309 and display controller 2307.
The data of vision signal that are imported into the pixel of single row are imported into the display controller 2307 from line storage 2309.At this; Through confirming that circuit 2305 is imported under the situation of line storage 2309, line storage 2309 is not input to the vision signal of the pixel of single row in the display controller 2307 at the data that are used to show the pixel column that is imported into line storage 2309 and the signal that is written to the Data Matching of the pixel column of subframe formerly.
In addition; Display controller 2307 is with initial pulse signal (G_SP; S_SP), clock signal (G_CLK, S_CLK), the output control signal (G_ENABLE, S_ENABLE), driving voltage, vision signal (Digital Video Data) etc. are input in the display 2308.
In other words; Be used in during the data that are used for single pixel column and will during a certain subframe of an image duration, write the vision signal of pixel wherein and the last subframe under the identical situation of the data of vision signal of this pixel column; Prevent the initial pulse signal (S_SP) of display controller 2307 outputs, so that prevent to export the sampling pulse that the vision signal of this pixel column is converted into parallel data from serial data corresponding to this pixel column.In addition, display controller 2307 will be used to control that (G_ENABLE S_ENABLE) is input in the display 2308 from the sweep signal of scan line driver circuit and the output control signal of whether being exported from the vision signal of signal line drive circuit.Be used for the data of vision signal of single row in during the data of vision signal and the last subframe when identical, the data of this vision signal are not imported in the display 2308.
Note, show that the calcspar of the primary structure of display device of the present invention is not limited to the structure shown in accompanying drawing 2 and 23.Any structure that when the signal that will be input to pixel is identical with the signal that is input to this pixel, stops this signal is input to this pixel can be used.Therefore, the signal that is input to this pixel is not limited to vision signal at this, and it can be to make pixel be in the not signal of luminance (erase signal).
(embodiment mode 7)
In the present embodiment pattern, explain circuit structure applicable to definite circuit 2305 of definite circuit 205 of the accompanying drawing of describing in the embodiment pattern 62 and accompanying drawing 23.
The instance of confirming circuit is shown in Figure 38.All be connected in series with the switch 4006 of pixel column equal number.L level current potential (is GND at this) is set to an end of the switch 4006 that is connected in series, and the other end is connected to lead-out terminal 4009.In addition, the distribution 4008 that is set to H level current potential (at this for power supply potential Vdd) is connected through pull-up resistor 4007 between the other end and lead-out terminal 4009 of the switch 4006 that is connected in series.Therefore, when all switches that are connected in series 4006 were all connected, the output control signal of exporting from lead-out terminal 4009 (ENABLE) was the L level signal.On the other hand, when any switch that is connected in series 4006 cut off, the output control signal of exporting from lead-out terminal 4009 (ENABLE) was the H level signal.
Formerly and after subframe in be used for same pixel row and same pixel row video signal data all be imported into each NOR door 4003.In addition, formerly and after subframe in be used for the vision signal of same pixel row and same pixel row data all also be imported into each AND door 4004.Then, each output of NOR door 4003 and AND door 4004 all is imported into OR door 4005.According to the output of OR door 4005, control said switch 4006 for switching on or off.
In other words, whether be switched on or cut off the comparative result of the j row pixel data among the i of pixel data 4001 and the SFx of the i that confirms SFx-1 in the capable pixel data 4002 in capable through switch 4006 corresponding to pixel in the j row.In other words, when the switch 4006 corresponding to the pixel in the j row is switched on, the j row pixel data coupling among the pixel data 4002 during pixel data 4001 during the i of SFx-1 is capable and the i of SFx are capable.Then, under unmatched situation, be cut off corresponding to the switch 4006 of the pixel in the j row.In other words; Only export control signal (ENABLE) under the situation of the Data Matching of all pixel columns in the pixel data 4002 of the i of pixel data in the i of SFx-1 is capable 4001 and SFx in capable and be in the L level, be in the H level and under the unmatched situation of the data of any pixel column, export control signal (ENABLE).
Explain the operation of confirming circuit in more detail.At first, make an explanation under the situation that the pixel data 4002 of the i of pixel data in the i of SFx-1 is capable 4001 and SFx in capable all matees in all row.In accompanying drawing 39, suppose that the i of the i of SFx-1 pixel data 4001 and the SFx in the capable pixel data 4002 in capable is in H level and H level respectively in first row; In secondary series, be in L level and L level; In the 3rd row, be in H level and H level; ...; In (n-1) row, be in H level and H level; With in n row, be in L level and L level.In other words, the pixel data 4002 of the i of pixel data 4001 and the SFx of the i of SFx-1 in capable in capable equal coupling in all row.
Pixel data all is in the H level in first row; Therefore, the H level is imported in two input terminals of NOR door 4003 and AND door 4004.Then, the output of NOR door 4003 is in the L level, and the output of AND door 4004 is in the H level.Therefore, the signal of the signal of H level and L level is imported in the input terminal of OR door 4005, so the output of OR door 4005 is in the H level.Then, the switch 4006 in first row passes through from the signal connection of the H level of OR door output.In addition, pixel data all is in the L level in secondary series; Therefore, the L level is imported into two input terminals of NOR door 4003 and AND door 4004.Then, the output of NOR door 4003 is in the H level, and the output of AND door 4004 is in the L level.Therefore, the signal of the signal of H level and L level is imported in the input terminal of OR door 4005, so the output of OR door is in the H level.Then, the switch in the secondary series 4006 passes through from the signal connection of the H level of OR door output.Similarly, the switch 4006 in all row all is switched on, and the output control signal (ENABLE) of lead-out terminal 4009 all is in the L level.
Subsequently, the pixel data 4002 unmatched situation in arbitrary row during pixel data 4001 during the i that explains at SFx-1 is capable and the i of SFx are capable.In accompanying drawing 40, suppose that the i of the i of SFx-1 pixel data 4001 and the SFx in the capable pixel data 4002 in capable is in H level and H level respectively in first row; In secondary series, be in L level and H level; In the 3rd row, be in H level and L level; ...; In (n-1) row, be in L level and L level; With in n row, be in L level and L level.In other words, the pixel data 4002 of the i of pixel data 4001 and the SFx of the i of SFx-1 in capable in capable at least the pixel data in secondary series and the 3rd row do not match.
Pixel data all is in the H level in first row; Therefore, the H level is imported in two input terminals of NOR door 4003 and AND door 4004.Then, the output of NOR door 4003 is in the L level, and the output of AND door 4004 is in the H level.Therefore, the signal of the signal of H level and L level is imported in the input terminal of OR door 4005, so the output of OR door is in the H level.Then, the switch in first row 4006 passes through from the signal connection of the H level of OR door 4005 outputs.On the other hand, the pixel data in secondary series in the i of SFx-1 is capable is in the L level, and the pixel data in the i of SFx is capable is in the H level; Therefore, L level and H level are imported into the input terminal of NOR door 4003 and AND door 4004.Then, the output of NOR door 4003 is in the L level, and the output of AND door 4004 is in the L level.Therefore, the signal of L level is imported in two input terminals of OR door 4005, so the output of OR door 4005 is in the L level.Then, the switch in the secondary series 4006 is cut off through the signal from the L level of OR door output.Also be that the pixel data in the i of SFx-1 is capable is in the H level in the 3rd row, and the pixel data in the i of SFx is capable is in the L level, so the L level of OR door 4005 outputs.Therefore the switch 4006 in the 3rd row is by the signal cut of the L level of exporting from OR door 4005.Therefore the switch 4006 in secondary series and the 3rd row is cut off at least, and the output control signal (ENABLE) of lead-out terminal 4009 is in the H level.
Notice that the structure of accompanying drawing 38 only is an example, confirms that the structure of circuit is not limited thereto.
Therefore, confirm that circuit can have the structure shown in accompanying drawing 73.
The data that are used for the vision signal that same pixel row and same pixel be listed as formerly with in the back in the subframe all are imported into two input terminals with the OR door 7303 of pixel column equal number.Then, the output of OR door 7303 each all be imported in the input terminal with the AND door 7304 of OR door equal number.According to the output of AND door, control said switch 7305 for switching on or off.
In other words, the comparative result of the pixel data of the j row among the pixel data 7302 of the i through confirming i at SFx-1 pixel data 7301 and the SFx in capable corresponding to the output of the OR door 7303 of pixel in the j row in capable.In other words, when the output corresponding to the OR door 7303 of the pixel in the i row is in the H level, the i row pixel data coupling among the pixel data 7302 during pixel data 7301 in the i of SFx-1 is capable and the i of SFx are capable.Then, under unmatched situation, be in the L level corresponding to the output of the OR door 7303 of pixel in the j row.Then, only when the output that is listed as the OR door 7303 of all pixels was in the H level corresponding to each, the output of AND door 7304 was in the H level, and switch 7305 is switched on.In other words; Only export control signal (ENABLE) under the situation of the Data Matching of all pixel columns among the pixel data 7302 of the i of pixel data in the i of SFx-1 is capable 7301 and SFx in capable and be in the L level, be in the H level and under the unmatched situation of the data of any pixel column, export control signal (ENABLE).
Notice that definite circuit of in the present embodiment pattern, describing only is an example, the invention is not restricted to this.
(embodiment pattern 8)
In the present embodiment pattern, explain the structure of the display board that is used for display device with reference to accompanying drawing 36A and 36B.
In the present embodiment pattern, explain display board applicable to display device with reference to accompanying drawing 36A and 36B.Notice that accompanying drawing 36A is the top view of explanation display board, accompanying drawing 36B is the cross sectional view along the accompanying drawing 36A of A-A ' intercepting.This display board comprises signal line drive circuit 3601, pixel portion 3602, second scan line driver circuit 3603 and first scan line driver circuit 3606 with the dotted line indication.It also comprises seal substrate 3604 and sealant 3605, and the part of surrounding through sealant 3605 is interval 3607.
Notice that distribution 3608 is to be used for sending the signal that will be input to second scan line driver circuit 3603, first scan line driver circuit 3606 and signal line drive circuit 3601 and through the distribution as FPC (flexible print circuit) 3609 receiving video signals of external input terminals, clock signal, enabling signal etc.IC chip (semi-conductor chip with memory circuitry, buffer circuit etc.) 3619 is installed in the junction of FPC3609 and display board through COG (glass top chip) etc.Note, only show FPC, but printed wiring board (PWB) also can be attached to FPC.Display device in this manual not only comprises display board itself, and comprises and be attached with FPC or PWB is attached to display board wherein.In addition, it is also included within the display board that IC chip etc. has been installed on it.
Then, explain cross-sectional structure with reference to accompanying drawing 36B.Pixel portion 3602 and its peripheral driver circuit (second scan line driver circuit 3603, first scan line driver circuit 3606 and signal line drive circuit 3601) all are formed on the substrate 3610; At this, show signal line drive circuit 3601 and pixel portion 3602.
Note,, use n channel transistor 3620 and p channel transistor 3621 to form cmos circuit as signal line drive circuit 3601.In the present embodiment pattern, describe and wherein the peripheral driver circuit is integrated in the display board on the substrate; Yet the present invention is not limited to this.The peripheral driver circuit of all or part can be formed on that IC chip etc. is gone up and through installations such as COG.
Pixel portion 3602 comprises a plurality of circuit, and each circuit all forms a pixel that comprises switching TFT 3611 and drive TFT 3612.Notice that the source electrode of drive TFT 3612 is connected to first electrode 3613.Insulator 3614 forms the end sections that covers first electrode 3613.At this, use the positive type light sensitive acrylic resin film.
Insulator 3614 is formed in curved surface that its upper end part or bottom part have band curvature so that make its covering favourable.For example, using under the situation of positive type light sensitive acrylic acid (resin) as the material of insulator 3614, insulator 3614 only preferably is formed the curved surface that in upper end part has radius-of-curvature (0.2 micron to 3 microns).Through in etchant, become insoluble minus and all can be used as insulator 3614 of rayed through the rayed soluble eurymeric that in etchant, becomes.
Layer 3616 and second electrode 3617 that includes organic compounds is formed on first electrode 3613.At this, the material with high work function preferably is used as the material as first electrode 3613 of anode.For example, first electrode 3613 can use following material to form: monofilm is such as tin indium oxide (ITO) film, indium zinc oxide (IZO) film, titanium nitride film, chromium film, tungsten film, Zn film or Pt film; Titanium nitride film with comprise the stack membrane of aluminium as the film of principal ingredient; By titanium nitride film, comprise the three-decker that aluminium is formed as the film and the titanium nitride film of principal ingredient; Deng.When first electrode 3613 has rhythmo structure, can equally with distribution have low resistance, and form favourable Ohmic contact.In addition, first electrode can be used as anode.
In addition, include evaporation method or the ink-jet method formation of layer 3616 through using evaporation mask of organic compounds.The metal complex that belongs to the 4th group of periodic table can be used as the part of the layer 3616 that includes organic compounds, and in addition, the material of use capable of being combined can be the material of low-molecular-weight material or HMW.In addition, as the material that is used to include organic compounds, general usually individual layer or the lamination that uses organic compound.In addition, present embodiment also comprises the structure of the part of the film that mineral compound wherein is used to be formed by organic compound.In addition, known triplet material also can use.
As being used to form, have material (Al, Ag, Li, Ca or its alloy ratio such as MgAg, MgIn, AlLi, the CaF of low work function at the material that includes second electrode (negative electrode) 3617 on the layer 3616 of organic compounds 2Or Ca 3N 2) can use.Pass through under the situation of second electrode, 3617 transmissions, at the said light that produces in the layer 3616 of organic compounds that includes by metallic film and nesa coating (indium zinc oxide (ITO), the alloy (In of indium oxide and tin oxide of thinner thickness 2O 3-ZnO), and tin oxide (ZnO) etc.) lamination formed is preferably used as second electrode (negative electrode) 3617.
Through sealant 3605 seal substrate 3604 is connected on the substrate 3610, has obtained such structure, wherein display element 3618 is provided in the space 3607 that is surrounded by substrate 3610, seal substrate 3604 and sealant 3605.Note, also have such situation: wherein fill with sealant 3605 and inert gas (such as nitrogen or argon gas) in space 3607.
Notice that epoxy preferably is used as sealant 3605.This material preferably allows the least possible moisture and oxygen to permeate.Except glass substrate and quartz substrate, can also use the plastic that forms by FRP (glass fiber reinforced plastics), PVF (PVF), Myler, polyester, acrylic fibre etc. as seal substrate 3604.
This display board obtains as indicated abovely.
Through integrated signal line drive circuit 3601, pixel portion 3602, second scan line driver circuit 3603 and first scan line driver circuit 3606 shown in accompanying drawing 36A and 36B, can reduce the cost of display device.
Note; The structure of display board is not limited to the structure that signal line drive circuit 3601, pixel portion 3602, second scan line driver circuit 3603 and first scan line driver circuit 3606 shown in accompanying drawing 36A integrate, and also can utilize such structure: wherein be formed on the IC chip and through COG etc. corresponding to the signal line drive circuit 4201 shown in accompanying drawing 42A of signal line drive circuit 3601 and be installed on the display board.Notice that the substrate 4200 of accompanying drawing 42A, pixel portion 4202, second scan line driver circuit 4203, first scan line driver circuit 4204, FPC 4205, IC chip 4206, IC chip 4207, seal substrate 4208 and sealant 4209 are corresponding to the substrate 3610 of accompanying drawing 36A, pixel portion 3602, second scan line driver circuit 3603, first scan line driver circuit 3606, FPC3609, IC chip 3619, IC chip 3619, seal substrate 3604 and sealant 3605.
In other words, only be that the signal line drive circuit of requirement high speed operation uses CMOS etc. to be formed on the IC chip to reduce power consumption.In addition, the semi-conductor chip through using silicon wafer etc. can be realized more at a high speed operation and lower power consumption as the IC chip.
In addition, through being integrated with pixel portion 4202, first scan line driver circuit 4203 and second scan line driver circuit 4204 can realize that cost reduces.
Therefore, can reduce the cost of High Resolution Display spare.In addition, be installed on the coupling part of FPC 3609 and substrate 3610 through the IC chip that will have functional circuit (memory circuitry or buffer circuit) and can effectively utilize Substrate Area.
In addition, can utilize following structure: wherein be formed on the IC chip and and be installed in display board through COG etc. corresponding to the signal line drive circuit among the accompanying drawing 42B of the signal line drive circuit among the accompanying drawing 36A 3601, second scan line driver circuit 3603 and first scan line driver circuit 3,606 4211, second scan line driver circuit 4214 and first scan line driver circuit 4213.In this case, can further reduce the power consumption of High Resolution Display spare.Therefore, the preferred polysilicon transistorized semiconductor layer that is applied in pixel portion, use is to provide consumption more lower powered display device.Notice that the substrate 4210 of accompanying drawing 42B, pixel portion 4212, FPC 4215, IC chip 4216, IC chip 4217, seal substrate 4218 and sealant 4219 correspond respectively to substrate 3610, pixel portion 3602, FPC 3609, IC chip 3619, IC chip 3619, seal substrate 3604 and the sealant 3605 of accompanying drawing 36A.
In addition, through the transistorized semiconductor layer that uses amorphous silicon to be used for pixel portion 4212 cost is reduced.In addition, can make large-sized display board.
The structure of above-described display board is shown in the synoptic diagram of accompanying drawing 41A.This display board comprises that wherein a plurality of line of pixels are listed in the pixel portion 4102 on the substrate 4101, also comprises second scan line driver circuit 4103, first scan line driver circuit 4104 and the signal line drive circuit 4105 that are positioned near the pixel portion 4102.
The signal that is input to second scan line driver circuit 4103, first scan line driver circuit 4104 and signal line drive circuit 4105 is carried from the outside through flexible print circuit (FPC) 4106.
Though do not illustrate, the IC chip can be installed on the FPC 4106 through COG (glass top chip), TAB (carrier band weldering automatically) etc.The part of the memory circuitry of second scan line driver circuit 4103, first scan line driver circuit 4104 and the signal line drive circuit 4105 that in other words, is difficult to integrate with pixel portion 4102, buffer circuit etc. can be formed on the IC chip and be installed on the display device.
At this, in display device of the present invention, second scan line driver circuit 4103 and first scan line driver circuit 4104 may be provided on the side of pixel portion 4102, shown in accompanying drawing 41B.Note display device shown in the accompanying drawing 41B and the setting that only is second scan line driver circuit 4103 in the display device difference shown in the accompanying drawing 41A; Therefore can use identical Reference numeral.In addition, second scan line driver circuit 4103 and first scan line driver circuit 4104 can be carried out and a similar function of drive circuit, perhaps can use among these two scan line driver circuit any.In other words, can suitably change this structure according to dot structure or driving method.
In addition, first scan line driver circuit and second scan line driver circuit and signal line drive circuit needn't be provided at respectively on the line direction and column direction of pixel.For example, be formed on the function that peripheral driver circuit 4301 on the IC chip shown in accompanying drawing 43A can have second scan line driver circuit 4214, first scan line driver circuit 4213 and signal line drive circuit 4211 shown in accompanying drawing 42B.Notice that the substrate 4300 of accompanying drawing 43A, pixel portion 4302, FPC 4304, IC chip 4305, IC chip 4306, seal substrate 4307 and sealant 4308 correspond respectively to substrate 3610, pixel portion 3602, FPC 3609, IC chip 3619, IC chip 3619, seal substrate 3604 and the sealant 3605 of accompanying drawing 36A.
Notice that the synoptic diagram of the connection of the signal wire of the display device of figures 43A is shown in the accompanying drawing 43B.This display device comprises substrate 4310, peripheral driver circuit 4311, pixel portion 4312, FPC 4313 and FPC 4314.Signal and power supply potential from the outside are input to peripheral driver circuit 4311 through FPC 4313.Then, the output of peripheral driver circuit 4311 be imported into link to each other with pixel portion 4312 included pixels in the sweep trace of line direction and the signal wire on column direction.
In addition, applicable to the instance of the display element of display element 3618 shown in accompanying drawing 44A and the 44B.In other words, can explain the structure of the display element of the pixel that is applicable to embodiment pattern 1 with reference to accompanying drawing 44A and 44B.
The display element of accompanying drawing 44A has such component structure: wherein anode 4402, the hole injection layer 4403 that is formed by hole-injecting material, the hole transmission layer 4404 that is formed by hole mobile material, luminescent layer 4405, the electron transfer layer 4406 that is formed by electron transport material, electron injecting layer 4407 and the negative electrode 4408 that is formed by the electronics injecting material all are stacked on the substrate 4401.At this, luminescent layer 4405 can only be formed by a kind of luminescent material; Yet it can be formed by two kinds or more kinds of material.In addition, component structure of the present invention is not limited to this structure.
Except the rhythmo structure of each functional layer shown in Figure 44 A; Aspect component structure, also have the change of wide scope, such as the element that uses high-molecular weight compounds or wherein luminescent layer be to use the efficient element that the triplet luminescent material of emission light constitutes under triple excited states.In addition, component structure of the present invention also be applicable to through with hole blocking layer control charge carrier recombination region so that light-emitting zone is divided into white light display element that two zones obtain etc.
In the manufacturing approach of the element of the present invention shown in Figure 44 A, on substrate 4401, evaporate hole-injecting material, hole mobile material and luminescent material according to following order with anode 4402 (ITO).Afterwards, evaporation electron transport material and electronics injecting material form negative electrode 4408 through evaporation at last.
To list the material that is suitable for hole-injecting material, hole mobile material, electron transport material, electronics injecting material and luminescent material below.
As hole-injecting material, in organic compound, porphyrin compound, phthalocyanine (are referred to as " H hereinafter 2Pc "), copper phthalocyanine (being referred to as " CuPc " hereinafter) etc. is effective.In addition, have than the littler ionic potential value of employed hole mobile material and have the hole transport materials with function and also can be used as hole-injecting material.Also exist the chemical doping conducting polymer to quantize compound, gather (ethylene dioxythiophene) (being referred to as " PEDOT " hereinafter) comprising what be doped with polystyrolsulfon acid (being referred to as " PSS " hereinafter), polyaniline etc.In addition, the insulation high-molecular weight compounds also is being effectively aspect the complanation of anode, and uses polyimide (being referred to as " PI " hereinafter) usually.In addition, also use mineral compound, said mineral compound comprises the ultrathin membrane of aluminium oxide (being referred to as " aluminium oxide " hereinafter) and such as the film of metals such as gold or platinum.
The material that is widely used as most hole mobile material is aromatic amine based compound (in other words being the compound with key of phenyl ring-nitrogen).Widely used material comprises 4, and 4-bis (diphenylamine)-biphenyl (being referred to as " TAD " hereinafter), its derivant be such as 4,4-bis [N-(3-aminomethyl phenyl)-N-phenyl-amino] biphenyl (being referred to as " TPD " hereinafter) or 4; 4-bis [N-(1-naphthyl)-N-phenyl-amino] biphenyl (being referred to as " α-NPD " hereinafter) in addition, also comprises the star burst aromatic amines compound; Such as 4; 4 ', 4 " (N, N-diphenylamine)-triphenylamine (being referred to as " TDATA " hereinafter) or 4-three; 4 ', 4 "-three [N-(3-aminomethyl phenyl)-N-aniline]-triphenylamines (being referred to as " MTDATA " hereinafter).
As electron transport material; Usually use metal complex; Comprising metal complex, such as Alq, Balq, three (4-methyl-8-quinoline) aluminium (being referred to as " Almq " hereinafter) or two (10-hydroxy benzo [H]-quinoline root) berylliums (being referred to as " BeBq " hereinafter), in addition with quinoline backbone or benzoquinoline backbone; Also comprise metal complex, (be referred to as " Zn (BOX) hereinafter such as two [2-(2-hydroxyphenyl) benzoxazole] zinc with azoles base or thiazolyl ligand 2") or two [2-(2-hydroxyphenyl) benzothiazole] zinc (be referred to as " Zn (BTZ) hereinafter 2").In addition; Except that metal complex; Such as 2-(4-biphenyl)-5-(4-spy-n-butylphenyl)-1; 3; 4-oxadiazole (being referred to as " PBD " hereinafter) or OXD-7 De oxadiazole (oxadiazole) derivant, such as TAZ or 3-(4-spy-n-butylphenyl)-4-(4-ethyl group phenyl)-5-(4-biphenyl)-1,2, the triazole derivative of 4-triazole (being referred to as " p-EtTAZ " hereinafter) and also have electron transport property such as the phenanthroline derivant of bathophenanthroline (bathophenanthroline) (being referred to as " BPhen " hereinafter) or BCP.
Can use above-mentioned electron transport material as the electronics injecting material.In addition, use the ultrathin membrane of insulator usually, such as the metal halide that comprises calcium fluoride, lithium fluoride, cesium fluoride etc. or comprise the alkali metal oxide of Lithia.In addition, also be effective such as diacetone lithium (being referred to as " Li (acac) " hereinafter) or 8-quinoline-lithium alkali metal complexs such as (being referred to as " Liq " hereinafter).
As luminescent material, remove such as Alq, Almq, BeBq, BAlq, Zn (BOX) 2Or Zn (BTZ) 2Beyond above-mentioned metal complex, various fluorescent pigments also are effective.Said fluorescent pigment comprises: 4 of blueness, 4-dicyano ethylene-2-methyl-6-(p-dimethylamino-styrene)-4H-pyrans of 4-bis (2,2-biphenyl-vinyl) biphenyl, reddish orange etc.In addition, the triplet luminescent material also is feasible, and said triplet luminescent material mainly is to be the complex compound of central metal with platinum or iridium.As the triplet luminescent material, three (2-phenylpyridine) iridium, two (2-(4 '-tryl) the pyridine root closes-N C 2') diacetone iridium (being referred to as " acacIr (tpy) 2 " hereinafter), 2,3,7,8,12,13,17,18-octaethyl-21H, 23H-porphyrin-platinum etc. is known.
Through the above-mentioned material that combination has each function, can produce the display element of high reliability.
In addition; Through change have the polarity of the driver transistor of dot structure described in the embodiment pattern 1 in case become the n channel transistor and make display element opposite electrode current potential amplitude be set to the current potential anti-phase of power lead, also can use have by with Figure 44 A in the display element of each layer of opposite sequence stack.In other words; In component structure, negative electrode 4408, the electron injecting layer 4407 that is formed by the electronics injecting material, the electron transfer layer 4406 that is formed by electron transport material, luminescent layer 4405, the hole transmission layer 4404 that is formed by hole mobile material, hole injection layer 4403 and the anode 4402 that is formed by hole-injecting material sequentially are stacked on the substrate 4401.
In addition, in order to extract the light emission of display element, at least one in anode and the negative electrode can be transparent.Afterwards, TFT and display element are formed on the substrate.Exist have a kind of through with the substrate opposite surfaces extract the top emission structure of light emission display element, have a kind of display element of the bottom emission structure through the surface extraction light emission on substrate one side and have a kind of through with substrate opposite surfaces and substrate one side on the surface extract the display element of two emitting structurals of light emission.Pixel arrangement of the present invention can be applied to have the display element of any emitting structural.
To the display element with top emission structure be described with reference to Figure 45 A below.
On substrate 4500, be formed with drive TFT 4501, between them, insert basement membrane 4505, and form first electrode 4502 its source electrode with drive TFT 4501 is contacted.Form layer 4503 and second electrode 4504 that includes organic compounds above that.
Notice that first electrode 4502 is anodes of display element, and second electrode 4504 is negative electrodes of display element.In other words, in the zone that the layer 4503 that includes organic compounds is sandwiched between first electrode 4502 and second electrode 4504, form display element.
At this, preferably use material to form first electrode 4502 as anode with high work function.For example, can use monofilm such as titanium nitride film, chromium film, tungsten film, Zn film or Pt film; By titanium nitride film with comprise aluminium and be the film formed lamination of its principal ingredient; Or by titanium nitride film, comprise aluminium and be the film of its principal ingredient and the film formed trilamellar membrane structure of titanium nitride etc.Note when first electrode 4502 has rhythmo structure, can equally with distribution having low resistance, form good Ohmic contact, also be used as anode.Use the light reflecting metallic film through making, can form lighttight anode.
Second electrode 4504 as negative electrode preferably uses following structure to form: (Al, Ag, Li, Ca or its alloy are such as MgAg, MgIn, AlLi, CaF by the material with low work function 2Or Ca 3N 2) metallic film that forms and the lamination of nesa coating (tin indium oxide (ITO), indium zinc oxide (IZO), zinc paste (ZnO) etc.).Through using above-mentioned thin metal film and nesa coating, can form the negative electrode of ability printing opacity.
Therefore, indicated like the arrow among Figure 45 A, can extract the light of display element from top surface.In other words, display element is being applied in the situation of the display board shown in Figure 36 A and the 35B, light sends towards substrate 3,610 one sides.Therefore, when the display element with top emission structure was used for display device, the substrate of printing opacity was as seal substrate 3604.
In addition, in the situation of blooming was provided, said blooming can be located on the seal substrate 3604.
Note, can use the metal film of processing by the material with low work function (such as MgAg, MgIn or AlLi) to form first electrode 4502 so that it is as negative electrode.In this case, can use nesa coating (such as tin indium oxide (ITO) film or indium zinc oxide (IZO) film) to form second electrode 4504.Therefore, through this structure, can improve the transmittance of top-emission.
To the display element with bottom emission structure be described with reference to Figure 45 B below.Because it is all identical with Figure 45 A to remove its structure emitting structural, so identical Reference numeral is described among use and Figure 45 A.
Preferably use material to form first electrode 4502 as anode with high work function.For example, can use nesa coating (such as tin indium oxide (ITO) film or indium zinc oxide (IZO) film).Through using nesa coating, can form the anode of ability printing opacity.
Can use that (Al, Ag, Li, Ca or its alloy are such as MgAg, MgIn, AlLi, CaF by the material with low work function 2Or Ca 3N 2) metal film processed forms second electrode 4504 as negative electrode.Through using above-mentioned light reflecting metallic film, can form lighttight negative electrode.
Therefore, indicated like the arrow among Figure 45 B, can extract the light of display element from basal surface.In other words, display element is being applied in the situation of the display board shown in Figure 36 A and the 36B, light sends towards substrate 3,610 one sides.Therefore, when the display element with bottom emission structure was used for display device, the substrate that uses printing opacity was as substrate 3610.
In addition, in the situation of blooming was provided, said blooming can be located on the substrate 3610.
To the display element with two emitting structurals be described with reference to Figure 45 C below.Because it is all identical with Figure 45 A to remove its structure emitting structural, so identical Reference numeral is described among use and Figure 45 A.
Preferably use material to form first electrode 4502 as anode with high work function.For example, can use nesa coating (such as tin indium oxide (ITO) film or indium zinc oxide (IZO) film).Through using nesa coating, can form the anode of printing opacity.
Use preferably that (Al, Ag, Li, Ca or its alloy are such as MgAg, MgIn, AlLi, CaF by the material with low work function 2Or Ca 3N 2) metal film and the formed lamination of nesa coating (alloy (In2O3-ZnO) of tin indium oxide (ITO), indium oxide and zinc paste, zinc paste (ZnO) etc.) processed form second electrode 4504 as negative electrode.Through using above-mentioned thin metal film and nesa coating, can form the negative electrode of light-permeable.
Therefore, indicated like the arrow among Figure 45 C, can be from the light of two surface extraction display elements.In other words, display element is being applied in the situation of the display board shown in Figure 36 A and the 36B, light sends towards substrate 3,610 one sides and seal substrate 3,604 one sides.Therefore, when the display element with two emitting structurals is used for display device, the substrate that uses printing opacity as substrate 3610 and seal substrate 3604 both.
In addition, in the situation of blooming was provided, said blooming can be located at substrate 3610 and seal substrate 3604 on both.
In addition, the present invention can be applicable to through using white light emitting elements and color filter to realize the display device of panchromatic demonstration.
As shown in Figure 46, on substrate 4600, be formed with basement membrane 4602, drive TFT 4601 forms above that, and forms first electrode 4603 its source electrode with drive TFT 4601 is contacted.Form layer 4604 and second electrode 4605 that includes organic compounds above that.
Notice that first electrode 4603 is anodes of display element, and second electrode 4605 is negative electrodes of display element.In other words, in the zone that the layer 4604 that includes organic compounds is sandwiched between first electrode 4603 and second electrode 4605, form display element.Structure through shown in Figure 46 is sent white light.Respectively red filter 4606R, green filter 4606G and blue filter 4606B are located at the display element top to realize panchromatic demonstration.In addition, the black matrix" (also being referred to as " BM ") 4607 that is used to separate these chromatic filters is provided.
The said structure of use display element capable of being combined, and can suitably be applied to display device of the present invention.In addition, the structure of above-described display board and display element only are instances, and other structure can be applied to display device of the present invention naturally.
(embodiment pattern 9)
The present invention can be applicable to various electronic equipments.Particularly, it can be applied to the display part of electronic equipment.The instance of this electronic equipment is following: such as camera, goggle-type display (head-wearing display), navigational system, audio reproducing system (for example automobile audio or sound part etc.), computing machine, game machine, the portable data assistance (for example mobile computer, mobile phone, portable game machine or e-book) of video camera or digital camera, have picture reproducer (a kind of equipment that is used to reproduce the storage medium of digital universal disc (DVD) for example and comprises the luminescent device that can show its image particularly) of storage medium reading section etc.
Figure 26 A has shown luminescent device, comprises base 26001, support 26002, display part 26003, speaker portion 26004, video inputs 26005 etc.Display device of the present invention can be used in display part 26003.Notice that this luminescent device comprises the luminescent device of the display message that is useful on its classification, for example be used for personal computer, be used for the luminescent device that television broadcasting received or be used for display ads.Use the present invention can reduce power consumption as the luminescent device of display part 26003.
Figure 26 B is a camera, comprises main body 26101, display part 26102, image receiving unit 26103, operating key 26104, external connection port 26105, shutter 26106 etc.
Use the present invention can reduce power consumption as the camera of display part 26102.
Figure 26 C has shown computing machine, comprises main body 26201, base 26202, display part 26203, keyboard 26204, external connection port 26205, trackpoint 26206 etc.Use the present invention can reduce power consumption as the computing machine of display part 26203.
Figure 26 D has shown mobile computer, comprises main body 26301, display part 26302, switch 26303, operating key 26304, infrared port 26305 etc.Use the present invention can reduce power consumption as the mobile computer of display part 26302.
Figure 26 E shown have the storage medium reading section portable image reproduction device (particularly; DVD reproducer for example), it comprises main body 26401, base 26402, display part A 26403, display part B 26404, storage medium (DVD etc.) reading section 26405, operating key 26406, speaker portion 26407 etc.Display part A 26403 main displays image information, display part B 26404 main character display information.Use the present invention can reduce power consumption as the picture reproducer of display part A 26403 and display part B 26404.
Figure 26 F has shown the goggle-type display, and it comprises main body 26501, display part 26502 and arm portion 26503 etc.Use the present invention can reduce power consumption as the goggle-type display of display part 26502.
Figure 26 G has shown video camera, and it comprises main body 26601, display part 26602, base 26603, external connection port 26604, remote control receiving unit 26605, image receiving unit 26606, battery 26607, audio frequency importation 26608, operating key 26609 etc.Use the present invention can reduce power consumption as the video camera of display part 26602.
Figure 26 H has shown mobile phone, comprises that main body 26701, base 26702, display part 26703, audio frequency importation 26704, audio output part divide 26705, operating key 26706, external connection port 26707, antenna 26708 etc.
In recent years, mobile phone has game function, camera-enabled, electronic money function etc., and the demand of the mobile phone that is used for high added value is increased.Though mobile phone becomes multi-functional and frequency of utilization increases, still require charging once to use the long time.Use the present invention can reduce power consumption as the mobile phone of display part 26703.Therefore, use becomes possibility for a long time.
As indicated above, the present invention can be applicable to all electronic equipments.
(embodiment pattern 10)
In the present embodiment pattern, explain wherein pixel portion to be divided into a plurality of zones and to carry out the display device that the signal to pixel writes in each zone respectively.In other words, can from the driver each zone, carry out signal writes.
Accompanying drawing 24 has shown wherein pixel portion is divided into two zones and carries out the instance of the display device that signal writes through different drive circuits.
Display device shown in the accompanying drawing 24 comprises first pixel region 2405, second pixel region 2406, selects the scan line driver circuit 2403 of the pixel column of first pixel region 2405, with vision signal be input to first pixel region 2405 signal line drive circuit 2401, select second pixel region 2406 pixel column scan line driver circuit 2404 and vision signal is input to the signal line drive circuit 2402 of second pixel region 2406.
In first pixel region 2405, pixel 2407 is arranged with respect to sweep trace G1 to Gm and signal wire S1 to Sn with matrix-style.In second pixel region 2406, pixel 2407 is arranged with respect to sweep trace G ' 1 to G ' m and signal wire S ' 1 to S ' n with matrix-style.
Clock signal (G1_CLK), inversion clock signal (G1_CLKB), initial pulse signal (G1_SP), output control signal (G1_ENABLE) etc. are input in the scan line driver circuit 2403 to select to be written into the pixel column of signal.Then, clock signal (S1_CLK), inversion clock signal (S1_CLKB), initial pulse signal (S1_SP), output control signal (S1_ENABLE), vision signal (Digital Video Data 1) etc. are input in the signal line drive circuit 2401 vision signal is input in the pixel column of being selected by scan line driver circuit 2403.Note, through sweep signal being input to the selection of carrying out pixel column among the sweep trace G1 to Gm, through vision signal being input to the vision signal input of carrying out in each among the signal wire S1 to Sn pixel column.
Note, the vision signal of in the pixel of single row, in the address period during the subframe formerly, importing with will be during subframe subsequently under the identical situation of the vision signal imported, this signal is written in the said single row of pixels in preventing during subframe subsequently.Therefore; The vision signal that the pixel that is used for being presented at single row is imported in the address period during the subframe formerly whether with during subframe subsequently in the identical output control signal (G1_ENABLE of vision signal of input; S1_ENABLE), be imported into respectively in scan line driver circuit 2403 and the signal line drive circuit 2401.
Clock signal (G2_CLK), inversion clock signal (G2_CLKB), initial pulse signal (G2_SP), output control signal (G2_ENABLE) etc. are input in the scan line driver circuit 2404 to select to be written into the pixel column of signal.In addition, clock signal (S2_CLK), inversion clock signal (S2_CLKB), initial pulse signal (S2_SP), output control signal (S2_ENABLE), vision signal (Digital Video Data 1) etc. are input in the signal line drive circuit 2402 vision signal is input in the pixel column of being selected by scan line driver circuit 2404.Note, through sweep signal being input to the selection of carrying out pixel column among sweep trace G ' 1 to the G ' m, carry out vision signal input pixel column through vision signal being input in each of signal wire S ' 1 to S ' n.
Note, the vision signal of in the pixel of single row, in the address period during the subframe formerly, importing with will be during subframe subsequently under the identical situation of the vision signal imported, this signal is written in the pixel of single row in preventing during subframe subsequently.Therefore; Be presented in the pixel of single row the vision signal in the address period during the subframe formerly, imported whether with during subframe subsequently in the identical output control signal of the vision signal of input (G2_ENABLE S2_ENABLE) is imported into respectively in scan line driver circuit 2404 and the signal line drive circuit 2402.
Though vision signal is written to respectively in first pixel region 2405 and second pixel region 2406, first pixel region 2405 and second pixel region 2406 both as a display part display image.In other words, be divided into vision signal (Digital Video Data 1) and vision signal (Digital Video Data 2) as the data of the image of a display part, they are imported in the corresponding signal lines drive circuit.
Owing to during structure is cut apart pixel portion and shortened signal and write as this, therefore can provide a kind of and bring up to high definition and carry out the display device that senior gray scale shows.
Note, relevant with the raising of sharpness and display gray scale grade, the increase power consumption increase of the number of times that writes along with the enforcement signal.Yet; The vision signal of in the pixel of single row, in the address period during the subframe formerly, importing with will the situation that the vision signal of input is identical in during the subframe of back under, display device of the present invention prevents in during the subframe of back to write to the signal of the pixel of single row.Therefore, display device of the present invention can reduce power consumption.
In addition, the structure optimization of present embodiment pattern is applied to the display device of the high capacity of display (display device with a large amount of display pixels), writes because in each pixel region, can carry out signal to pixel respectively.In other words, along with the increase of the capacity of display, the pixel of all row is write required time (increase).Yet, if, in each pixel region, carry out signal respectively and write, along with the increase of the quantity in the zone of cutting apart can be shortened all pixels are write required time as the structure of present embodiment pattern.
(embodiment 1)
In the present embodiment; The display device of in embodiment pattern 1, describing with reference to accompanying drawing 12A and 12B illustrated in detail; In this display device, be used for single pixel column and will be written to during a certain subframe of an image duration that vision signal is not imported in the pixel under the data of the vision signal of the pixel wherein situation identical with the data that are written to this pixel column.Accompanying drawing 12A shown the usage level direction as time shaft and vertical direction as signal writing operation and the signal erase operation of pixel column axle in a certain image duration.
Hereinafter makes an explanation to the capable pixel column of i.In the capable pixel column of i; Time for writing signal in during first subframe is expressed as SF1a (i), second, third, the time for writing signal in during the 4th, the 5th and the 6th subframe is expressed as SF2a (i), SF3a (i), SF4a (i), SF5a (i) and SF6a (i) respectively.In addition, explain between light emission period and not between light emission period to the pixel of i in capable with reference to accompanying drawing 12B.When focal attention i is capable, much shorter during the time for writing signal of pixel kept than data; Therefore in accompanying drawing 12B, save time for writing signal.In SF1a (i) during write signal, SF1s (i) during the data during operation proceeds to during first subframe keep.Then, the time for writing signal SF2a (i) in during second subframe begins SF1s (i) end during data keep.When giving the pixel write signal according to time for writing signal SF2a (i), SF2s (i) beginning during the data in during second subframe keep, SF2s (i) finished through the signal erase operation during data kept.This section time durations of time for writing signal SF3a (i) beginning during the signal of the pixel in i is capable is wiped free of afterwards during the 3rd subframe through erase operation is not between light emission period.In a similar fashion, SF3s (i) was the time durations of the time for writing signal SF4a (i) from be written to after the pixel signal during the 4th subframe according to the time for writing signal SF3a (i) during the 3rd subframe during data in during the 3rd subframe kept.SF4s (i) was the time durations of the time for writing signal SF5a (i) from be written to after the pixel signal during the 5th subframe according to the time for writing signal SF4a (i) during the 4th subframe during data in during the 4th subframe kept.SF5s (i) was from according to the time for writing signal SF5a (i) during the 5th subframe signal being written to after the pixel up to the time durations of wiping the signal of the pixel in i is capable through the signal erase operation during data in during the 5th subframe kept.SF6s (i) was the time durations of the time for writing signal SF1a (i) during first subframe from be written to after the pixel signal during next frame according to the time for writing signal SF6a (i) during the 6th subframe during data in during the 6th subframe kept.
At this, if it is identical with the data of the vision signal of all pixels that are used for single row at SF2a (i) in SF1a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF2a (i), stops to i the pixel in capable writes.In addition, be that this pixel is placed the not data of luminance if in SF3a (i), be used for the data of vision signal of all pixels of single row, the signal that then in SF3a (i), stops to i the pixel in capable writes.Similarly, if it is identical with the data of the vision signal of all pixels that are used for single row at SF3a (i) in SF4a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF4a (i), stops to i the pixel in capable writes.If it is identical with the data of the vision signal of all pixels that are used for single row at SF4a (i) in SF5a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF5a (i), stops to i the pixel in capable writes.If in SF6a (i), being used for the data of vision signal of all pixels of single row is that this pixel is placed the not data of luminance, the signal that then in SF6a (i), stops to i the pixel in capable writes.
As indicated above, under the situation of Data Matching of the signal of in the end importing in the subframe (vision signal and erase signal) and the vision signal of the pixel that is used for single row, the signal of pixel column is write in stopping at during this subframe.For example, prevent to be used to select the signal output of the scan line driver circuit of this pixel column.In other words, will be used for not selecting the L signal of this pixel column to be input to the sweep trace of this pixel column, perhaps the sweep trace with this pixel column places quick condition.In addition, also prevent signal line drive circuit outputting video signal.The output of this signal line drive circuit can be that pixel is placed the signal of luminance or pixel is placed the not signal of luminance.Can import this running out maybe low power signal.Replacedly, can signal wire be placed quick condition.
This makes and can reduce the number of times of implementing charging and discharge and reduce power consumption.
(embodiment 2)
In the present embodiment; The display device of in embodiment pattern 1, describing with reference to accompanying drawing 12A and 12B illustrated in detail; In this display device; The data of during being used for a certain subframe an image duration, pixel being carried out the vision signal of the single pixel column that signal wipes are when this pixel is placed the data of luminance not, do not wipe the signal of this pixel column.Accompanying drawing 12A shown the usage level direction as time shaft and vertical direction as signal writing operation and the signal erase operation of pixel column axle in a certain image duration.
Hereinafter is concentrated the capable pixel column of i is made an explanation.In the capable pixel column of i; Time for writing signal in during first subframe is expressed as SF1a (i), second, third, the time for writing signal in during the 4th, the 5th and the 6th subframe is expressed as SF2a (i), SF3a (i), SF4a (i), SF5a (i) and SF6a (i) respectively.In addition, the signal erasing time in during second subframe is expressed as SF2e (i), and the signal erasing time in during the 5th subframe is expressed as SF5e (i).In addition, explain between light emission period and not between light emission period to the pixel of i in capable with reference to accompanying drawing 12B.When focal attention i is capable, much shorter during the time for writing signal of pixel kept than data; Therefore in accompanying drawing 12B, save time for writing signal.In SF1a (i) during write signal, SF1s (i) during the data during operation proceeds to during first subframe keep.Then, the time for writing signal SF2a (i) in during second subframe begins SF1s (i) end during data keep.When giving the pixel write signal according to time for writing signal SF2a (i), SF2s (i) beginning during the data in during second subframe keep, SF2s (i) finished through the signal erase operation during data kept.This section time durations of time for writing signal SF3a (i) beginning during the signal of the pixel in i is capable is wiped free of afterwards during the 3rd subframe through erase operation is not between light emission period.In a similar fashion, SF3s (i) was the time durations of the time for writing signal SF4a (i) from be written to after the pixel signal during the 4th subframe according to the time for writing signal SF3a (i) during the 3rd subframe during data in during the 3rd subframe kept.SF4s (i) was the time durations of the time for writing signal SF5a (i) from be written to after the pixel signal during the 5th subframe according to the time for writing signal SF4a (i) during the 4th subframe during data in during the 4th subframe kept.SF5s (i) was from according to the time for writing signal SF5a (i) during the 5th subframe signal being written to after the pixel up to the time durations of wiping the signal of the pixel in i is capable through the signal erase operation during data in during the 5th subframe kept.SF6s (i) was the time durations of the time for writing signal SF1a (i) during first subframe from be written to after the pixel signal during next frame according to the time for writing signal SF6a (i) during the 6th subframe during data in during the 6th subframe kept.
At this, be that this pixel is placed the not data of luminance if in SF2a (i), be used for the data of vision signal of all pixels of single row, the signal that then in SF2e (i), stops to i the pixel in capable is wiped.If in SF5a (i), being used for the data of vision signal of all pixels of single row is that this pixel is placed the not data of luminance, the signal that then in SF5e (i), stops to i the pixel in capable is wiped.
Under the situation of erase signal mentioned above, before just be input to the vision signal in the pixel of single row data be that the signal that stops this pixel column was wiped when this pixel was placed the data of luminance not.For example, prevent to export the signal of the scan line driver circuit that is used to select this pixel column.In other words, will be used for not selecting the L signal of this pixel column to be input to the sweep trace of this pixel column, perhaps the sweep trace with this pixel column places quick condition.From the signal line drive circuit, can keep vision signal continuation input or this vision signal of this pixel column can be erase signal.Can import the signal of this power that maybe be little that runs out.Replacedly, can signal wire be placed quick condition.
This makes and can reduce the number of times of implementing charging and discharge and reduce power consumption.
(embodiment 3)
In the present embodiment; The display device of in embodiment pattern 1, describing with reference to accompanying drawing 12A and 12B illustrated in detail; In this display device; Be used for single pixel column and will under the video signal data that is written to pixel wherein during a certain subframe of the image duration situation identical, vision signal be imported into this pixel with the data of the pixel column that is written to this pixel; In addition, be this pixel to be placed the signal of not carrying out this pixel column under the data conditions of luminance not wipe in the data of the vision signal of the single pixel column that the signal that will be performed pixel is wiped.
Hereinafter is concentrated the capable pixel column of i is made an explanation.In the capable pixel column of i; Time for writing signal in during first subframe is with SF1a (i) expression, second, third, the time for writing signal in during the 4th, the 5th and the 6th subframe is expressed as SF2a (i), SF3a (i), SF4a (i), SF5a (i) and SF6a (i) respectively.In addition, the signal erasing time in during second subframe is expressed as SF2e (i), and the signal erasing time in during the 5th subframe is expressed as SF5e (i).In addition, i is capable for focal attention, explains between light emission period and not between light emission period to the pixel of i in capable with reference to accompanying drawing 12B.When focal attention i is capable, much shorter during the time for writing signal of pixel kept than data; Therefore in accompanying drawing 12B, save time for writing signal.In SF1a (i) during write signal, SF1s (i) during the data during operation proceeds to during first subframe keep.Then, the time for writing signal SF2a (i) in during second subframe begins SF1s (i) end during data keep.When giving the pixel write signal according to time for writing signal SF2a (i), SF2s (i) beginning during the data in during second subframe keep, SF2s (i) finished through the signal erase operation during data kept.This section time durations of time for writing signal SF3a (i) beginning during the signal of the pixel in i is capable is wiped free of afterwards during the 3rd subframe through erase operation is not between light emission period.In a similar fashion, SF3s (i) was the time durations of the time for writing signal SF4a (i) from be written to after the pixel signal during the 4th subframe according to the time for writing signal SF3a (i) during the 3rd subframe during data in during the 3rd subframe kept.SF4s (i) was the time durations of the time for writing signal SF5a (i) from be written to after the pixel signal during the 5th subframe according to the time for writing signal SF4a (i) during the 4th subframe during data in during the 4th subframe kept.SF5s (i) was from according to the time for writing signal SF5a (i) during the 5th subframe signal being written to after the pixel up to the time durations of wiping the signal of the pixel in i is capable through the signal erase operation during data in during the 5th subframe kept.SF6s (i) was the time durations of the time for writing signal SF1a (i) during first subframe from be written to after the pixel signal during next frame according to the time for writing signal SF6a (i) during the 6th subframe during data in during the 6th subframe kept.
At this, if it is identical with the data of the vision signal of all pixels that are used for single row at SF2a (i) in SF1a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF2a (i), stops to i the pixel in capable writes.In addition, be that this pixel is placed the not data of luminance if in SF3a (i), be used for the data of vision signal of all pixels of single row, the signal that then in SF3a (i), stops to i the pixel in capable writes.Similarly, if it is identical with the data of the vision signal of all pixels that are used for single row at SF3a (i) in SF4a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF4a (i), stops to i the pixel in capable writes.If it is identical with the data of the vision signal of all pixels that are used for single row at SF4a (i) in SF5a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF5a (i), stops to i the pixel in capable writes.If in SF6a (i), being used for the data of vision signal of all pixels of single row is that pixel is placed the not data of luminance, the signal that then in SF6a (i), stops to i the pixel in capable writes.
At this, be that this pixel is placed the not data of luminance if in SF2a (i), be used for the data of vision signal of all pixels of single row, the signal that then in SF2e (i), stops to i the pixel in capable is wiped.If in SF5a (i), being used for the data of vision signal of all pixels of single row is that this pixel is placed the not data of luminance, the signal that then in SF5e (i), stops to i the pixel in capable is wiped.
As indicated above, under the situation of Data Matching of the signal of in the end importing in the subframe (vision signal and erase signal) and the vision signal of the pixel that is used for single row, the signal of pixel column is write in stopping at during this subframe.For example, prevent to be used to select the signal of the scan line driver circuit of this pixel column to be exported.In other words, will be used for not selecting the L signal of this pixel column to be input to the sweep trace of this pixel column, perhaps the sweep trace with this pixel column places quick condition.In addition, also prevent signal line drive circuit outputting video signal.The output of this signal line drive circuit can be that pixel is placed the signal of luminance or pixel is placed the not signal of luminance.Can import the signal of this power that maybe be little that runs out.Replacedly, can signal wire be placed quick condition.In addition, under the situation of erase signal, before just be input to the vision signal in the pixel of single row data be that the signal that stops this pixel column was wiped when this pixel was placed the data of luminance not.For example, prevent to be used to select the signal of the scan line driver circuit of this pixel column to be exported.In other words, will be used for not selecting the L signal of this pixel column to be input to the sweep trace of this pixel column, perhaps the sweep trace with this pixel column places quick condition.From the signal line drive circuit, can keep vision signal continuation input or this vision signal of this pixel column can be erase signal.Can import the signal of this power that maybe be little that runs out.Replacedly, can signal wire be placed quick condition.
This makes and can reduce the number of times of implementing charging and discharge and reduce power consumption.
Note, under the situation that luminance does not continue, in case signal is input to pixel then no longer this signal is input to this pixel.Therefore, in this case,, the signal leakage that is input to pixel exports signal regularly before showing to make the mistake.Note, it is desirable to keep signal that to signal wire input is used for pixel is placed luminance not so that reduce signal leakage.Under the situation of luminous continuation, when the input erase signal, rewrite the signal of pixel; Therefore do not have problems.
(embodiment 4)
In the present embodiment, explain the driving method that is more suitable for of the display device of describing in the embodiment pattern 1.
Display device of the present invention is suitable for the driving method of such service time of gray level method: through be divided into an image duration during a plurality of subframes and during each subframe each pixel of control luminous and not luminous, the difference of the T.T. of the fluorescent lifetime through each pixel is expressed gray scale; Particularly be adapted to pass through and implement the driving method that number of light emission times is expressed gray scale in sequentially being increased in during each subframe.In other words, the luminous number of sub frames of increase execution along with gray level also increases.Therefore, carry out in the luminous subframe, in high grade grey level, also carry out luminous in low gray level.This gray level method is called as " gray level method overlapping time ".
Explain situation with reference to accompanying drawing 22A and 22B with gray level method expression overlapping time 3-position gray scale.Accompanying drawing 22A shown the usage level direction as time shaft and vertical direction as the signal writing operation of pixel column axle in a certain image duration.In order to express 3-position gray scale, with being divided into seven sub-frame an image duration.
Notice that hereinafter makes an explanation to the capable pixel column of i.In the capable pixel column of i; Time for writing signal in during first subframe is expressed as SF1a (i), second, third, the time for writing signal in during the 4th, the 5th, the 6th and the 7th subframe is expressed as SF2a (i), SF3a (i), SF4a (i), SF5a (i), SF6a (i) and SF7a (i) respectively.
In addition, explain between light emission period to the pixel of i in capable with reference to accompanying drawing 22B.When focal attention i is capable, much shorter during the time for writing signal of pixel kept than data; Therefore in accompanying drawing 22B, save time for writing signal.In SF1a (i) during write signal, SF1s (i) during the data during operation proceeds to during first subframe keep.Then, the time for writing signal SF2a (i) in during second subframe begins SF1s (i) end during data keep.Similarly, during each subframe, carry out signal write fashionable, beginning during data keep, and these data write through the signal in next subframe during keeping and finish.Set second, third like this, respectively, the data in during the 4th, the 5th, the 6th and the 7th subframe keep during SF2s (i), SF3s (i), SF4s (i), SF5s (i), SF6s (i) and SF7s (i).During data as indicated above keep SF1s (i), SF2s (i), SF3s (i), SF4s (i), SF5s (i), SF6s (i) and SF7s (i) each all have equal time span.
At this, if it is identical with the data of the vision signal of all pixels that are used for single row at SF2a (i) in SF1a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF2a (i), stops to i the pixel in capable writes.In addition, be identical if in SF3a (i), be used for the data of vision signal of all pixels of single row with the data of the vision signal of all pixels that are used for single row at SF2a (i), the signal that then in SF3a (i), stops to i the pixel in capable writes.If it is identical with the data of the vision signal of all pixels that are used for single row at SF3a (i) in SF4a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF4a (i), stops to i the pixel in capable writes.If it is identical with the data of the vision signal of all pixels that are used for single row at SF4a (i) in SF5a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF5a (i), stops to i the pixel in capable writes.If it is identical with the data of the vision signal of all pixels that are used for single row at SF5a (i) in SF6a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF6a (i), stops to i the pixel in capable writes.If it is identical with the data of the vision signal of all pixels that are used for single row at SF6a (i) in SF7a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF7a (i), stops to the mat woven of fine bamboo strips i pixel in capable writes.
As indicated above, under the situation of Data Matching of the signal of in the end importing in the subframe (vision signal) and the vision signal of the pixel that is used for single row, the signal of pixel column is write in stopping at during this subframe.For example, prevent to export the signal of the scan line driver circuit that is used to select this pixel column.In other words, will be used for not selecting the L signal of this pixel column to be input to the sweep trace of this pixel column, perhaps the sweep trace with this pixel column places quick condition.In addition, also prevent signal line drive circuit outputting video signal.The output of this signal line drive circuit can be that pixel is placed the signal of luminance or pixel is placed the not signal of luminance.Can import the signal of this power that maybe be little that runs out.Replacedly, can signal wire be placed quick condition.
This makes and can reduce the number of times of implementing charging and discharge and reduce power consumption.
This be because, particularly using overlapping time during gray level method, carry out continuously in any gray level luminous or not luminous, formerly and the possibility of Data Matching of vision signal that in the subframe of back, is used for the pixel of single row sharply increase.
At this, accompanying drawing 27 has shown the luminous and non-luminous accompanying drawing in explaining in each gray level during each subframe.There is the subframe of circles mark (zero) to represent luminance, has the subframe of X-mark (*) to represent not luminance.Then, express gray scale through being increased in the luminous subframe of each gray level execution.In gray level 0, in SF1 to SF7, carry out not luminous.In gray level 1, only in SF1, carry out luminous and in SF2 to SF7, carry out not luminous.In gray level 2, in SF1 and SF2, carry out luminous and in SF3 to SF7, carry out not luminous.In gray level 3, luminous and not luminous in SF4 to SF7 in SF1 to SF3.In gray level 4, luminous and not luminous in SF5 to SF7 in SF1 to SF4.In gray level 5, luminous and not luminous in SF6 to SF7 in SF1 to SF5.In gray level 6, luminous and not luminous in SF7 in SF1 to SF6.In gray level 7, in all SF1 to SF7, carry out luminous.
Therefore find: in high grade grey level, repeat in during each subframe luminously, in low gray level, repeat in during each subframe not luminous.Therefore; When entire display screen is equally bright shown in accompanying drawing 31A; When entire display screen is equally dark shown in accompanying drawing 31B, and comprise shown in accompanying drawing 31C that incandescent shows and the utmost point shows slinkingly when showing at display screen, display device of the present invention can greatly reduce power consumption.
For example, all be in gray level at 5 to 7 o'clock in all pixels in a certain pixel column under the situation of display screen whole light yellow shown in accompanying drawing 31A, all pixels in SF1 to SF5 in this pixel column all are in luminance.Therefore, in SF1, be written to signal in the pixel column after, be in SF6, once more this signal to be written in the pixel column.In other words, can save four signals to this pixel column writes.
For example, whole shown in accompanying drawing 31B at display screen is that all pixels in a certain pixel column all were in gray level at 0 to 2 o'clock under the dark situation, and all pixels in SF3 to SF7 in this pixel column all are in not luminance.Therefore, do not need once more this signal to be written in the pixel column after in SF3, being written to signal in the pixel column.In other words, can save four signals to this pixel column writes.
For example; Comprise shown in accompanying drawing 31C that incandescent shows and the utmost point shows slinkingly that all pixels in a certain pixel column all are in gray level 0 when showing at display screen; In the time of in 1,6 and 7, all pixels in SF2 to SF6 in pixel column all are in luminance or non-luminance.Therefore, in SF2, be written to signal in the pixel column after, be in SF7, once more this signal to be written in the pixel column.In other words, can save four signals to this pixel column writes.
Notice that accompanying drawing 31A has shown the situation that on the display screen of personal computer, is presented at sky on fine daytime, but this only is an instance.Therefore, the present invention is not limited to this.
In addition, accompanying drawing 31B has shown the situation that on the display screen of personal computer, shows night sky, but this only is an instance.Therefore, the present invention is not limited to this.
In addition, accompanying drawing 31C has shown the situation of character display on the display screen of personal computer, but this only is an instance.Therefore, the present invention is not limited to this.
Note, using overlapping time shown in accompanying drawing 27 during gray level method, only luminous the and not luminous switching of antithetical phrase in image duration be once in an image duration; Therefore, in addition intermediate grey scales be in formerly and during the subframe of back in the possibility of coupling of data in the pixel of single pixel column higher.Therefore, the number of times of implementing charging and discharge can be reduced, therefore power consumption can be reduced.
In addition, through using this driving method also can reduce false contouring.This be because, in the gray level higher than a certain gray level, a certain gray level with more hang down the gray scale place make each luminous subframe of pixel during in this pixel all luminous.Therefore, even when the optical axis moves, still can prevent eyes coarse brightness of perception on the transition point between the gray level.
In addition, can luminous weighting center be arranged on the center through the selecting sequence that changes the subframe of selecting with respect to gray level.The example is shown in Figure 32.In gray level 0, in SF1 to SF7, carry out not luminous.In gray level 1, only in SF4, carry out luminous and in SF1 to SF3 and SF5 to SF7 execution not luminous.In gray level 2, in SF3 and SF4, carry out luminous and, carry out not luminous among the SF2, SF5 to SF7 at SF1; In gray level 3, in SF3 to SF5, carry out luminous and at SF1, SF2, execution is not luminous among SF6 and the SF7; In gray level 4, in SF2 to SF5, carry out luminous and at SF1, execution is not luminous among SF6 and the SF7; In gray level 5, in SF2 to SF6, carry out luminous and in SF1 and SF7 execution not luminous; In gray level 6, in SF1 to SF6, carry out luminous and in SF7, carry out not luminous; In gray level 7, in SF1 to SF7, all carry out luminous.In other words,, low gray level,, select the subframe near this centre subframe to be used for wherein carrying out during the luminous subframe during carrying out luminous subframe along with gray level increases since dynatron image duration.Through selecting above-mentioned subframe, luminous weighting center can be positioned at this center and can carry out clearly and show.
If the fluorescent lifetime in being weighted in during all subframes equably, then number of sub frames need increase to carry out senior gray scale and shows.Therefore, do not increase number of sub frames in order to carry out senior gray scale to show, everybody is divided into each zone such as high-order position, middle component level and low-order bit, fluorescent lifetime is weighting equably in each zone.For example, be that 2 positions, middle component level are that 2 positions and low-order bit are under the situation of 1 position in high-order position, make an explanation with reference to accompanying drawing 28.
The fluorescent lifetime of high-order position, middle component level and low-order bit is weighted into 8: 2: 1.In addition, 2 number of sub frames of high-order is three (SF1 to SF3), and it can realize 2 expression, i.e. four gray levels.2 number of sub frames of scala media is three (SF4 to SF6), and it can realize 2 expression, i.e. four gray levels.In addition, 1 number of sub frames of low order is one (SF7), and it can realize 1 expression, i.e. two gray levels.Therefore, can express 5 through 7 sub-frame (three sub-frame of three sub-frame of high-order position, middle component level and a sub-frame of low-order bit) altogether, i.e. 32 gray levels.
Still as accompanying drawing 28 shown that the signal of in the end importing in the subframe (vision signal) and being used under the situation of Data Matching of vision signal of pixel of single row writes the signal of this pixel column in stopping at during the subframe.In this case; For example; All pixels all are under the situation of gray level 0 to 7, gray level 24 to 31 or gray level 0 to 7 and 24 to 31 in a certain pixel column; All pixels still remain on luminance or luminance not in this pixel column, and constant in SF1 to SF3.Therefore, can save that the signal to pixel column writes in SF2 and SF3.Therefore, the number of times of implementing charging and discharge can be reduced, power consumption can be reduced.In addition, all pixels all be in gray level 0 or 1, gray level 30 or 31 or the situation of gray level 0 or 1 and 30 or 31 under, all pixels still remain on luminance or luminance not in this pixel column, and constant in SF1 to SF6.Therefore, can save that the signal to pixel column writes in SF2 and SF6.Therefore, the number of times of implementing charging and discharge can be greatly reduced, power consumption can be reduced.In other words,, whole screen gray level can greatly reduce power consumption when being partial to high grade grey level, low gray level or high grade grey level and low gray level basically.
At this, the gray level that accompanying drawing 30A is presented at a certain pixel column is in the luminous and not luminous of each subframe under 28 to 31 the situation.Suppose a certain pixel column comprise 10 row prerequisite under make an explanation.In SF1 to SF7, the subframe that is marked with circles mark (zero) is wherein to carry out luminous subframe.Notice that pixel column 1 is in gray level 28; Pixel column 2 is in gray level 31; Pixel column 3 is in gray level 29; Pixel column 4 is in gray level 28; Pixel column 5 is in gray level 30; Pixel column 6 is in gray level 31; Pixel column 7 is in gray level 29; Pixel column 8 is in gray level 30; Pixel column 9 is in gray level 28; Pixel column 10 is in gray level 30.Then, shown in accompanying drawing 30A, in SF1 to SF5, in all pixel columns, carry out luminous; The signal that therefore, in SF2 to SF5, can save pixel column writes.Can reduce power consumption like this.
In addition, need not increase number of sub frames to express a plurality of gray levels; Therefore can prevent to show that with more senior gray scale related power consumption increases.
Notice that overlapping time, gray level method can be used for high-order position, and digit time, gray level method can be used for low-order bit.Make an explanation with reference to accompanying drawing 29.In other words, be weighted at 4: 2: 1 o'clock 3 of low order, 2 fluorescent lifetime of high-order is weighted into 8.2 number of sub frames of high-order is three (SF1 to SF3).This makes can express 2, i.e. 4 gray levels.3 number of sub frames of low order is three (SF4 to SF6), and this makes can express 3 gray scale.Therefore, can express 5 through six sub-frame (three sub-frame of high-order position and three sub-frame of low-order bit), i.e. 32 gray levels.
Therefore, also be in accompanying drawing 29, under the situation of Data Matching of the signal of in the end importing in the subframe (vision signal) and the vision signal of the pixel that is used for single row, the signal of this pixel column is write in stopping at during the subframe.In this case; All pixels all are under the situation of gray level 0 to 7, gray level 24 to 31 or gray level 0 to 7 and 24 to 31 in a certain pixel column; All pixels still remain on luminance or luminance not in this pixel column, and constant in SF1 to SF3.Therefore, can save that the signal to pixel column writes in SF2 and SF3.
At this, the gray level that accompanying drawing 30B is presented at a certain pixel column is in the luminous and not luminous of each subframe under 0 to 3 and 28 to 31 the situation.Suppose a certain pixel column comprise 10 row prerequisite under make an explanation.In SF1 to SF6, the subframe that is marked with circles mark (zero) is wherein to carry out luminous subframe.Notice that pixel column 1 is in gray level 28; Pixel column 2 is in gray level 31; Pixel column 3 is in gray level 29; Pixel column 4 is in gray level 28; Pixel column 5 is in gray level 3; Pixel column 6 is in gray level 1; Pixel column 7 is in gray level 0; Pixel column 8 is in gray level 2; Pixel column 9 is in gray level 28; Pixel column 10 is in gray level 30.Then, shown in accompanying drawing 30B, in SF1 to SF4, in all pixel columns, keep luminous or not luminous; The signal that therefore, in SF2 to SF4, can save pixel column writes.Can reduce power consumption like this.
Therefore, can reduce the number of times of implementing charging and discharge, and reduce power consumption.Note, provide combination shown in accompanying drawing 29 overlapping time gray level method and digit time gray level method can reduce number of sub frames.
(embodiment 5)
In the present embodiment, such structure of utilization; Wherein, The data of the vision signal that will be written to pixel column all with just in time before when being written into the Data Matching of vision signal of pixel column of signal, the data of vision signal that then will be written into the pixel column of signal are not written in the signal line drive circuit.In other words; Line by line signal is being written in the capable sequential display spare of pixel; Be not imported into the signal line drive circuit with the data vision signal that be complementary, pixel column that just in time is written to before the vision signal of pixel column, the data of the vision signal of the pixel column before the use just in time are written to this pixel column with signal.Replacedly, with just in time before the signal of pixel write side by side to carry out write.Driving method combination through with this method and the display device of in embodiment pattern 1, describing can further reduce power consumption.
The display device of present embodiment makes an explanation with reference to accompanying drawing 25.Select circuit 2501 from frame memory, to read through memory read the data of the vision signal that is written to pixel.For the every capable pixel of subframe reads the data of vision signal and selects circuit 2502 to be entered in first shift register 2503 or second shift register 2505 through input register.In other words, replacedly, the data of the vision signal of the pixel of single row are imported in first shift register 2503 and second shift register 2505.
In addition, confirm that circuit 2504 relatively is input to the data of the vision signal of the pixel that is used for single row in first shift register 2503 and second shift register 2505.Then, show that the output control signal (SR_ENABLE) whether the data of the vision signal be imported into the pixel that is used for single row in first shift register 2503 and second shift register 2505 mate is imported into output register selection circuit 2506.
In addition, output register select circuit 2506 to read before to be written in first shift register 2503 or second shift register 2505 pixel that is used for single row in any vision signal data and these data are input to display 2507.Note; During among the data of the vision signal of the pixel of single row are imported into first shift register 2503 and second shift register 2505 one under the situation of these data and the Data Matching of the vision signal that is imported into the pixel that is used for single row in another, the output control signal (SR_ENABLE) that shows this result is imported into output register and selects in the circuit 2506; Therefore do not select circuit 2506 to be input to display 2507 from output register the data of pixel in this row.
Notice that the structure that shows in the accompanying drawing 38 can be used for confirming in the circuit 2504.
Note, this structure in the present embodiment can with the textural association in the accompanying drawing 2.Memory read in the accompanying drawing 25 selects circuit 2501 to select circuit 206 corresponding to reading in the accompanying drawing 2.In addition, display 2507 is corresponding to the display in the accompanying drawing 2 208.
According to the structure of present embodiment, require first shift register 2503 and second shift register 2505 to be used for display controller 207.Yet if these are formed on the identical IC chip, load capacitance, wiring resistance, contact resistance etc. are all far below the load capacitance of the signal line drive circuit of arranging on the substrate with pixel portion, wiring resistance, contact resistance etc.Therefore, the data of comparing vision signal are input to the situation in the signal line drive circuit in display, and present embodiment can reduce power consumption considerably.
(embodiment 6)
In the present embodiment, explain the new driving method of the display device of the pixel comprise the display element that is formed with the current drives that its brightness changes according to electric current.
Explain the basic structure of the driving method of present embodiment with reference to accompanying drawing 65A.Accompanying drawing 65A shown the usage level direction write as the signal of pixel column axle in a certain image duration as time shaft and vertical direction during (address period) and data keep during (during keeping).Notice that according to this driving method, be divided into during a plurality of subframes an image duration, during each subframe in vision signal be written in the pixel, the control pixel is luminous and not luminous with the expression gray scale during each subframe.
During the capable completion of the m signal writing operation from first row to the last row of conduct in during each subframe is address period.Then, from address period be accomplished to next son image duration during be keep during.
The radiative brightness that obtains from display element in during this driving method change each during each subframe kept is shown in accompanying drawing 65B.At this, represent with SF1s during the keeping of SF1 during the subframe; Represent with SF2s during the keeping of SF2 during the subframe; Represent with SF3s during the keeping of SF3 during the subframe; Represent with SF4s during the keeping of SF4 during the subframe; Represent with SF5s during the keeping of SF5 during the subframe.Notice that the length during each is kept about equally.At this, at SF1s, SF2s, SF3s, the light intensity that sends from pixel among SF4s and the SF5s each with SF1d, SF2d, SF3d, SF4d and SF5d represent.Then, if satisfy SF1d: SF2d: SF3d: SF4d: SF5d=1: 2: 4: 8: 16, then pixel is luminous or not luminous can express 32 gray levels through during each subframe, selecting.
Therefore, according to this structure, even expressing under the situation of senior gray scale, still can be so that corresponding to longer during the keeping in during the subframe of LSB, because the length of each in during each subframe during keeping is about equally.
Equally in this structure; Be used for single pixel column and will during the video signal data that is written to pixel wherein during a certain subframe of an image duration and last subframe, be used for stopping the signal of pixel column is write under the identical situation of the data of vision signal of this pixel column.
At this, the pixel column capable to i makes an explanation.In the capable pixel column of i, the time for writing signal in during first subframe is expressed as SF1a (i), second, third, the time for writing signal in during the 4th and the 5th subframe is expressed as SF2a (i), SF3a (i), SF4a (i) and SF5a (i) respectively.
At this, if it is identical with the data of the vision signal of all pixels that are used for single row at SF2a (i) in SF1a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF2a (i), stops to i the pixel in capable writes.In addition, be that this pixel is placed the not data of luminance if in SF3a (i), be used for the data of vision signal of all pixels of single row, the signal that then in SF3a (i), stops to i the pixel in capable writes.Similarly, if it is identical with the data of the vision signal of all pixels that are used for single row at SF3a (i) in SF4a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF4a (i), stops to i the pixel in capable writes.If it is identical with the data of the vision signal of all pixels that are used for single row at SF4a (i) in SF5a (i), to be used for the data of vision signal of all pixels of single row, the signal that then in SF5a (i), stops to i the pixel in capable writes.
Therefore, the signal of pixel is being write the fashionable number of times that can reduce enforcement charging and discharge, and can reduced power consumption.
In addition, through senior gray scale demonstration is carried out in the driving method and gray level method combination digit time of present embodiment easily.66A makes an explanation with reference to accompanying drawing.
Accompanying drawing 66A shown the usage level direction as time shaft and vertical direction as signal writing operation and the signal erase operation of pixel column axle in a certain image duration.
Hereinafter makes an explanation to the capable pixel column of i.In the capable pixel column of i; Time for writing signal in during first subframe is expressed as SF1a (i), second, third, the time for writing signal in during the 4th, the 5th and the 6th subframe is expressed as SF2a (i), SF3a (i), SF4a (i), SF5a (i) and SF6a (i) respectively.In addition, explain the light intensity of in an image duration, launching with reference to accompanying drawing 66B from pixel.In SF1a (i) during write signal, SF1s (i) during the data during operation proceeds to during first subframe keep.Then, the time for writing signal SF2a (i) in during second subframe begins SF1s (i) end during data keep.When giving the pixel write signal according to time for writing signal SF2a (i), SF2s (i) beginning during the data in during second subframe keep.Then, the time for writing signal SF3a (i) in during the 3rd subframe begins SF2s (i) end during data keep.When giving the pixel write signal according to time for writing signal SF3a (i), SF3s (i) beginning during the data in during the 3rd subframe keep, SF3s (i) finished through the signal erase operation during data kept.This section time durations of time for writing signal SF4a (i) after the signal of the pixel since i is capable is wiped free of through erase operation in during the 4th subframe is not between light emission period.Subsequently in SF4a (i) during write signal, SF4s (i) during the data during operation proceeds to during the 4th subframe keep.Then, the time for writing signal SF5a (i) in during the 5th subframe begins SF4s (i) end during data keep.When giving the pixel write signal according to time for writing signal SF5a (i), SF5s (i) beginning during the data in during the 5th subframe keep.Then, the time for writing signal SF6a (i) in during the 6th subframe begins SF6s (i) end during data keep.When giving the pixel write signal according to time for writing signal SF6a (i), SF6s (i) beginning during the data in during the 6th subframe keep, SF6s (i) finished through the signal erase operation during data kept.This section time durations of time for writing signal SF1a (i) during first subframe after the signal of the pixel since i is capable is wiped free of through erase operation in image duration subsequently is not between light emission period.
At this, in accompanying drawing 66A and 66B, the length of subframe is set to and satisfies SF1s (i): SF2s (i): SF3s (i): SF4s (i): SF5s (i): SF6s (i)=4: 2: 1: 4: 2: 1.In addition, be set to 8 times of luminous intensity of pixel in SF4s (i), SF5s (i) and SF6s (i) in the luminous intensity of pixel during SF1s (i), SF2s (i) and the SF3s (i).Then, when the brightness in during the 6th subframe was 1, the brightness in the luminance in during each subframe of an image duration was 2,4,8,16 and 32 in during the 5th, the 4th, the 3rd, second and first subframe.Therefore, can show 64 gray levels.Notice that the length during the at this moment the longest subframe approximately is four times of length during the shortest subframe.Therefore, can make during the shortest subframe than longer during subframe the shortest under the situation through common 64 gray levels of gray level method expression digit time.Therefore, can carry out senior gray scale demonstration and not wipe the signal of pixel.
In addition, the structure example of the display device of the luminous intensity of change pixel during accompanying drawing 64 has shown during each subframe.
Comprise signal line drive circuit 6401, scan line driver circuit 6402 and pixel portion 6403 at the display device shown in the accompanying drawing 64.In addition, in pixel portion 6403, a plurality of pixels 6404 are with respect to the signal wire S that extends from signal line drive circuit 6401 along column direction and follow the sweep trace G that direction extends from scan line driver circuit 6402 and arrange with matrix-style.Notice that the pixel of accompanying drawing 10 is used for pixel 6404 as an example.The power lead 1007 of the pixel of accompanying drawing 10 is corresponding to the power lead V of the display device that shows in the accompanying drawing 64.
In addition, this display device comprises monitor element 6405, current source 6406 and buffering amplifier 6407.Carry electric current arbitrarily from current source 6406 for monitor element 6405.Then, between two electrodes of monitor element 6405, produce voltage.In other words, if between two electrodes of monitor element 6405, apply voltage, the electric current of then carrying from current source 6406 flows to monitor element 6405.Therefore; Through carry desirable electric current to impose on the display element into this pixel to present to the display element of pixel and with the voltage that produces in the monitor element 6405 for monitor element 6405, the display element of this light emitting pixel can have desirable luminous intensity.
Therefore, can be to the opposite electrode of the opposite electrode of monitor element 6405 and display element with identical potential setting.The current potential of the pixel electrode of monitor element 6405 is imported on the input terminal of buffer amplifier 6407.Then, about equally current potential from the buffering amplifier 6407 lead-out terminal export.This current potential is set to power lead V.When connecting driver transistor, be applied to the display element of this pixel as the voltage of the potential difference (PD) between current potential that is set to power lead V and opposite electrode.Therefore, can set luminous intensity arbitrarily.In other words, under the situation of the driving method that display device is applied to present embodiment, set the current value that flows to current source 6406 and in during each subframe, obtain desirable luminous intensity.
(embodiment 7)
In the present embodiment, explain a kind of use pixel intensity with the dot structure under the situation of the display element that applies change in voltage with comprise the display device of this dot structure and suitable driving method thereof.The display element that liquid crystal cell is particularly suitable for describing in the present embodiment.
At first, the basic structure of accompanying drawing 54 display pixels.This pixel comprises aanalogvoltage holding circuit 5401, digital signal memory circuit 5402, display element 5403, signal wire 5404, first switch 5405 and second switch 5406.
Under the situation of this structure, in the process of selecting pixel, connect first switch 5405.
Showing under the situation that moves image, selecting aanalogvoltage holding circuit 5401 through second switch 5406.Then, the aanalogvoltage corresponding to vision signal is imported into the aanalogvoltage holding circuit 5401 from signal wire 5404.
Aanalogvoltage holding circuit 5401 keeps this aanalogvoltage and this voltage is imposed on display element 5403.Express the gray scale of this pixel by this way according to aanalogvoltage.Then, aanalogvoltage is transfused to aanalogvoltage holding circuit 5401 from signal wire 5404 in each image duration.
Under the situation that shows still image, select digital signal memory circuit 5402 through second switch 5406.To be input to digital signal memory circuit 5402 corresponding to the digital signal of vision signal from signal wire 5404 then.
Digital signal memory circuit 5402 is stored these digital signals and is set the current potential of the pixel electrode of display element 5403.Like this, control the luminous and not luminous of display element 5403 according to the potential difference (PD) between the opposite electrode 5407 of current potential of importing from digital signal memory circuit 5402 and display element 5403.
Note, under the situation that shows still image, can the usable floor area gray level method etc. express gray scale.
Explain the situation of usable floor area gray level method with reference to accompanying drawing 55 and 56.
Display device in the accompanying drawing 55 comprises the first signal line drive circuit 5501, secondary signal line driver circuit 5502, pixel portion 5503 and scan line driver circuit 5504; In pixel portion 5503, pixel 5505 is arranged with matrix-style with respect to sweep trace and signal wire.
Each pixel 5505 comprises sub-pixel 5506a, sub-pixel 5506b and sub-pixel 5506c.Weighting is carried out in luminous zone to sub-pixel.For example, the luminous zone is sized to and satisfies 2 2: 2 1: 2 0This makes can carry out the demonstration of 3-position, promptly has the demonstration of 8 gray levels.
Notice that first switch 5507 of sub-pixel 5506a is connected to signal wire Da, first switch 5507 of sub-pixel 5506b is connected to signal wire Db, and first switch 5507 of sub-pixel 5506c is connected to signal wire Dc.Through be input to the signal of sweep trace S from scan line driver circuit 5504, first switch 5507 of control sub-pixel 5506a, sub-pixel 5506b and sub-pixel 5506c switches on or off.In other words, first switch 5507 is in on-state in the pixel of a selection.Then, from each signal wire aanalogvoltage or digital signal are written to aanalogvoltage holding circuit 5509 or digital signal memory circuit 5510.
In other words, under the situation that moves the image demonstration, signal is input to sweep trace S to connect first switch 5507, selects aanalogvoltage holding circuits 5509 through second switch 5508.Aanalogvoltage corresponding to vision signal is input to signal wire Da, signal wire Db and signal wire Dc from the first signal line drive circuit 5501.Then, aanalogvoltage is remained in the aanalogvoltage holding circuit 5509 of each sub-pixel.Notice that the aanalogvoltage that at this moment is input to signal wire Da, signal wire Db and signal wire Dc each other about equally.Therefore, can express gray scale according to the size of aanalogvoltage.
On the other hand, under the situation that still image shows, signal is imported into sweep trace S connecting first switch 5507, and selects digital signal memory circuits 5510 through second switch 5508.Digital signal corresponding to vision signal is input to signal wire Db, signal wire Db and signal wire Dc from secondary signal line driver circuit 5502.Then, digital signal is stored in the digital signal memory circuit 5510 of each sub-pixel.Note, be input to signal wire Da, signal wire Db and the signal wire Dc digital signal in each with big or small corresponding every the signal conduct at this moment of the luminous zone of each sub-pixel and be transfused to.Therefore, select through digital signal that each sub-pixel is luminous and not luminous can express gray scale.
Then, the structure of figures 56.Display device in the accompanying drawing 56 comprises the first signal line drive circuit 5601, secondary signal line driver circuit 5602, pixel portion 5603 and scan line driver circuit 5604; In pixel portion 5603, pixel 5605 is arranged with matrix-style with respect to sweep trace and signal wire.
Each pixel 5605 comprises sub-pixel 5606a, sub-pixel 5606b and sub-pixel 5606c.Weighting is carried out in luminous zone to sub-pixel.For example, the luminous zone is sized to and satisfies 2 2: 2 1: 2 0This makes can carry out the demonstration of 3-position, promptly has the demonstration of 8 gray levels.
Notice that first switch 5607 of sub-pixel 5606a, sub-pixel 5606b and sub-pixel 5606c all is connected to signal wire D.Through be input to the signal of sweep trace Sa from scan line driver circuit 5604, first switch 5607 of control sub-pixel 5606a switches on or off; Through being input to the signal of sweep trace Sb from scan line driver circuit 5604, the break-make of first switch 5607 of control sub-pixel 5606b; Through being input to the signal of sweep trace Sc from scan line driver circuit 5604, the break-make of first switch 5607 of control sub-pixel 5606c.In other words, first switch 5607 is in on-state in the pixel of a selection.Then, from signal lines aanalogvoltage or digital signal are written to aanalogvoltage holding circuit 5609 or digital signal memory circuit 5610.
In other words, moving under the situation that image shows, signal sequence ground is input to sweep trace Sa, sweep trace Sb and sweep trace Sc to connect first switch 5607 of each sub-pixel, through second switch 5608 selection aanalogvoltage holding circuits 5609.Aanalogvoltage corresponding to vision signal is input to signal wire D from the first signal line drive circuit 5601.Then, aanalogvoltage is sequentially remained in the aanalogvoltage holding circuit 5609 of each sub-pixel.Notice that the aanalogvoltage that when selecting each sub-pixel, is input to signal wire D each other about equally.Therefore, can express gray scale according to the size of aanalogvoltage.
On the other hand, under the situation that still image shows, signal is input to sweep trace Sa, sweep trace Sb and sweep trace Sc connecting first switch 5607 of each sub-pixel by order, and selects digital signal memory circuits 5610 through second switch 5608.Digital signal corresponding to vision signal is input to signal wire D from secondary signal line driver circuit 5602.Then, digital signal sequentially is stored in the digital signal memory circuit 5610 of each sub-pixel.Note big or small corresponding every the digital signal of the luminous zone of input and each sub-pixel when selecting each sub-pixel.Therefore, select the luminous or not luminous of each sub-pixel can express gray scale through digital signal.
When under the situation that still image shows, rewriteeing image a part of, display device of the present invention stops signal that wherein not carry out the pixel column of rewriting is write.
In other words, former frame in be used under the situation of data and the Data Matching that wherein will carry out the pixel column that writes of vision signal of pixel column, scan line driver circuit comprises and prevents the selecteed output-controlling device of this pixel column.
In addition, accompanying drawing 57 has shown the structure example of the pixel that comprises aanalogvoltage holding circuit and digital signal memory circuit.This pixel comprises pixel selection switch 5701, first switch 5702, second switch 5703, the 3rd switch 5704, first transducer (phase inverter) 5705, second transducer (phase inverter) 5706, display element 5708, signal wire 5709 and capacitor element 5710.
In the process that signal is written to pixel, connect pixel selection switch 5701.
At this, showing under the situation that moves image that first switch 5702 is cut off with second switch 5703.Notice that the 3rd switch 5704 is in the state of switching on or off.Then, import from signal wire 5709 corresponding to the aanalogvoltage of vision signal, the electric charge of aanalogvoltage is accumulated in the capacitor element 5710.Through cutting off pixel selection switch 5701, aanalogvoltage is remained in the capacitor element 5710.
Like this, express gray scale according to aanalogvoltage.
On the other hand, under the situation that shows still image, first switch 5702 is at first connected, and then, cuts off second switch 5703.The 3rd switch 5704 becomes connection from dissengaged positions.Digital signal quilt corresponding to vision signal is imported in second transducer 5706 from the output that signal wire 5709 is input to first transducer, 5705, the first transducers 5705.Then, the output of second transducer 5706 is imported into capacitor element 5710 and display element 5708.Even pixel selection switch 5701 is cut off, the output of second transducer 5706 is still continued to be input in the pixel electrode of display element 5708.Note, have in digital signal under the situation of high driving capacity, can connect first switch 5702 and the 3rd switch 5704 simultaneously.
When digital signal is written to pixel, this digital signal of storage shown in accompanying drawing 58A and 58B.In other words, the input of second transducer 5706 is set in the output of first transducer 5705, and shown in arrow, the input of first transducer 5705 is set in the output of second transducer 5706.Therefore, the digital signal that is written to this pixel can continue to be stored.
Liquid crystal cell is being applied under the situation of display element 5708, when applying long time of dc voltage to liquid crystal cell, in liquid crystal cell, is causing aging etc.Therefore, it is reverse to impose on the voltage preference rule ground of liquid crystal cell.Therefore, first switch 5702 is alternately connected and is cut off shown in accompanying drawing 58A and 58B with second switch 5703, and pixel selection switch 5701 cuts off and 5704 connections of the 3rd switch simultaneously.In addition, the current potential that is set to opposite electrode 5711 also changes according to connection/cut-outs timing of the rule of first switch 5702 and second switch 5703.In white display pixel, AC voltage is imposed on display element 5708.On the other hand, in the black display pixel, the voltage that applies for display element 5708 is set to the threshold voltage that is equal to or less than liquid crystal cell.
For example; Situation about being explained as follows with reference to accompanying drawing 59: when the digital signal (Digital Video Data) from signal wire 5709 inputs is high level (being also referred to as the H level), this pixel is placed luminance (white shows), and when digital signal (Digital Video Data) is low level (being also referred to as the L level), this pixel is placed not luminance (black display).At this moment, the current potential that is set to opposite electrode 5711 in during the signal to this pixel writes is set at the L level.During writing, (in being meant during the signal of pixel writes signal being written to the time of selected pixel); The 3rd switch 5704 is switched on from dissengaged positions, and pixel selection switch 5701 is switched on simultaneously, first switch 5702 is switched on and second switch 5703 is cut off.Then, during still image shows in, pixel selection switch 5701 is cut off, the 3rd switch is switched on.
Shown in accompanying drawing 59; There is high vision signal (Digital VideoData) to be input to the pixel wherein in during writing, (in being meant during the signal of pixel writes signal being written to the time of selected pixel) from signal wire 5709; First switch 5702 is connected in during still image shows, and second switch 5703 cuts off.When the output of the H level of second transducer 5706 was imported into the pixel electrode of display element 5708, the current potential that is in the L level was set to the opposite electrode 5711 of display element 5708.In addition, cut off at first switch 5702, second switch 5703 is connected and the output of the L level of first transducer 5705 when being imported into the pixel electrode of display element 5708, is set to the opposite electrode 5711 of display element 5708 at the current potential of H level.Therefore, keep AC voltage to continue to impose on display element 5708.
On the other hand; There is low vision signal (Digital Video Data) to be input to the pixel wherein in during writing, (in being meant during the signal to pixel writes signal being written to the time of selected pixel) from signal wire 5709; First switch 5702 is connected in during still image shows, and second switch 5703 cuts off.When the output of the L level of second transducer 5706 was imported into the pixel electrode of display element 5708, the current potential that is in the L level was set to the opposite electrode 5711 of display element 5708.In addition, cut off at first switch 5702, second switch 5703 is connected and the output of the H level of first transducer 5705 when being imported into the pixel electrode of display element 5708, is set to the opposite electrode 5711 of display element 5708 at the current potential of H level.Therefore, the voltage that imposes on display element 5708 can be set equal to or be lower than the threshold voltage of liquid crystal cell.
Showing under the situation of still image, can the usable floor area gray level method etc. expressing gray scale.
Situation with reference to the long-pending gray level method of accompanying drawing 60 brief explanation application surfaces.Pixel comprises sub-pixel 6000a, sub-pixel 6000b and sub-pixel 6000c.Weighting is carried out in luminous zone to sub-pixel.For example, the luminous zone is sized to and satisfies 2 0: 2 1: 2 2This makes can carry out the demonstration of 3-position, promptly has the demonstration of 8 gray levels.
Notice that pixel selection switch in the accompanying drawing 60 6001, first switch 6002, second switch 6003, the 3rd switch 6004, first transducer 6005, second transducer 6006, display element 6008 and capacitor element 6010 correspond respectively to pixel selection switch 5701 in the accompanying drawing 57, first switch 5702, second switch 5703, the 3rd switch 5704, first transducer 5705, second transducer 5706, display element 5708 and capacitor element 5710.In accompanying drawing 60, signal wire is provided for each sub-pixel, as the signal wire shown in the accompanying drawing 57 5709.In other words, the pixel selection switch 6001 of sub-pixel 6000a is connected to signal wire Da; The pixel selection switch 6001 of sub-pixel 6000b is connected to signal wire Db; The pixel selection switch 6001 of sub-pixel 6000c is connected to signal wire Dc.Then, from the digital signal of corresponding every of the size of the input of each signal wire and the luminous zone of each sub-pixel.Therefore, select the luminous or not luminous of each sub-pixel can express gray scale through digital signal.
Subsequently, accompanying drawing 61 shows another structure example of the pixel that comprises aanalogvoltage holding circuit and digital signal memory circuit.This pixel comprises the first pixel selection switch 6101, the second pixel selection switch 6104, first capacitor element 6102, second capacitor element 6105, display element 6103, transistor 6106, first switch 6107, second switch 6108, signal wire 6109, first power lead 6110 and second source line 6111.Vrefh and Vrefl alternately are set to first power lead 6110, and Vcom is set to second source line 6111.At this, Vrefh satisfy (Vrefh＞Vcom) with (Vrefh-Vcom)＞V LCD, Vrefl satisfy (Vrefh＜Vcom) with (Vcom-Vrefl)＞V LCDWhen electrode and the Vcom that is set to display element 6103 at Vrefh or Vrefl is set to another electrode, be equal to or higher than threshold voltage V LCDVoltage be applied in to display element 6103.In addition, the current potential that is substantially equal to the current potential of second source line 6111 is set to the opposite electrode 6112 of display element 6103.In other words, when Vcom was set to the pixel electrode of display element 6103, the potential difference (PD) between the current potential of the current potential of pixel electrode and opposite electrode was set to the threshold voltage V that is equal to or less than display element 6103 LCD
Explain the operation of pixel now.Moving under the situation that image shows, the first pixel selection switch 6101 is switched on, and the second pixel selection switch 6104, first switch 6107 and second switch 6108 are cut off, shown in accompanying drawing 62.Then, the simulation current potential that depends on the gray level of this pixel is imported into signal wire 6109.This simulation current potential is corresponding to vision signal.Notice that the pixel in accompanying drawing 62 has identical structure with pixel in accompanying drawing 61, so Reference numeral can be with reference to accompanying drawing 61.
Subsequently, explain the situation that still image shows.Under the situation that still image shows, the second pixel selection switch 6104 at first is switched on, and the first pixel selection switch 6101, first switch 6107 and second switch 6108 are cut off then.Then, digital signal is input to signal wire 6109.This digital signal is corresponding to vision signal.Then, signal is written to second capacitor element 6105, shown in accompanying drawing 63A.
Then, the second pixel selection switch 6104 is cut off, and first switch 6107 is switched on, and the first pixel selection switch 6101 is cut off with second switch 6108 simultaneously.Then, the current potential Vrefh of first power lead 6110 is set to an electrode of first capacitor element 6102, shown in accompanying drawing 63B.In addition, the current potential Vcom of second source line 6111 is set to another electrode of first capacitor element 6102; Therefore, the electric charge that is used for potential difference (PD) (Vrefh-Vcom) is accumulated in capacitor element 6102.Notice that at this moment power supply potential Vrefh is set on the pixel electrode of display element 6103.
Subsequently, first switch 6107 is cut off, and second switch 6108 is switched on, and the first pixel selection switch 6101 and the second pixel selection switch 6104 all are cut off simultaneously.Then, come oxide-semiconductor control transistors 6106 to switch on or off according to the digital signal that is written to second capacitor element 6105.
In other words,, the digital signal that is written to second capacitor element 6105 connects transistor 6106 when being the H level.Therefore, the current potential Vcom of second source line 6111 is set to two electrodes of first capacitor element 6102, shown in accompanying drawing 63C.Then, the current potential of Vcom is set to the pixel electrode of display element 6103.Notice that at this moment voltage imposes on display element 6103 hardly, the current potential that therefore is substantially equal to Vcom is set to the opposite electrode 6112 of display element 6103.Therefore, this pixel is placed in not luminance.On the other hand,, the digital signal that is written to second capacitor element 6105 cuts off transistor 6106 when being in the L level.Therefore, first capacitor element 6102 keeps this voltage, shown in accompanying drawing 63D.Correspondingly, remain on Vrefh owing to be set to the current potential of the pixel electrode of display element 6103, so this pixel is placed in luminance.
Subsequently, the current potential of the Vrefl through being set to first power lead 6110 is carried out similar operation in during next frame.Then, the reverse bias voltage of the voltage that imposes on display element 6103 in image duration is in the end imposed on the display element 6103 of light emitting pixel.Therefore, imposing on the current potential that the bias voltage direction of display element 6103 can be in each image duration be set to first power lead 6110 through change changes.Therefore, can prevent the aging of display element 6103.
Noting, as long as the digital signal that keeps in second capacitor element 6105 can oxide-semiconductor control transistors 6106 switch on or off, then all is acceptable.Therefore, even the slight discharge of charges accumulated still can be carried out normal operation in second capacitor element 6105.Therefore, every several image duration or more than ten image duration can carry out periodicity rewriting to the digital signal of this pixel.Can reduce power consumption like this.
Note, under the situation that still image shows, when changing a part of image, rewrite with the signal of the periodicity emphasis write operation of this pixel combine digital signal being carried out dividually to this pixel.In this case, display device of the present invention is only carried out the signal rewriting to this pixel with the periodicity emphasis write operation dividually in comprising the pixel column that changes within the pixel luminous or not luminance.In other words, when the data of the data of the vision signal of the pixel that will be written to certain pixel column and the digital signal that is written to this pixel were identical, scan line driver circuit was not selected pixel column.
Therefore, can further reduce power consumption.
Note, applicable to the dot structure of display device of the present invention be not limited to above-described these.In addition, for the digital signal memory circuit, can use the static RAM (SRAM) shown in accompanying drawing 57 or can use the dynamic RAM (DRAM) shown in accompanying drawing 61.Replacedly, can use their combination.
(embodiment 8)
In the present embodiment, explain the structure example of the mobile phone that in the display part, comprises display device of the present invention with reference to accompanying drawing 50.
Display board 5010 is incorporated in the housing 5000 so that separable.The shape and size of housing 5000 can suitably change according to the size of display board 5010.The housing 5000 that is fixed with display board 5010 is assemblied in the printed circuit board (PCB) 5001 and assembles and becomes module.
Display board 5010 is connected to printed circuit board (PCB) 5001 through FPC 5011.Printed circuit board (PCB) 5001 has loudspeaker 5002, microphone 5003, transmission and receiving circuit 5004 and comprises the signal processing circuit 5005 of CPU, controller etc.This module, input media 5006 and battery 5007 use base 5009 combinations and deposit.The window that the pixel portion of display board 5010 is configured to from be formed on base 5012 is visible.
In display board 5010; Can on substrate, form a part (the lower drive circuit of frequency of operation in a plurality of drive circuits) and the pixel portion of peripheral driver circuit through using TFT, and can on the IC chip, form another part (the higher drive circuit of frequency of operation in a plurality of drive circuits) of peripheral driver circuit with integrated mode.Can the IC chip be installed on the display board 5010 through COG (glass top chip).Perhaps can the IC chip be connected on the glass substrate through using TAB (carrier band weldering automatically) or printed circuit board (PCB).Notice that accompanying drawing 42A has shown the instance of the structure of display board, wherein the part of peripheral driver circuit and pixel portion are integrated on the substrate, and the IC chip that has formed another part of peripheral driver circuit on it passes through installations such as COG.Through adopting above-mentioned structure, can reduce the power consumption of display device, and can prolong the once service time of charging back mobile phone.In addition, the cost that can realize mobile phone reduces.
Replacedly; In order further to reduce power consumption; Can use TFT on substrate, to form pixel portion, all peripheral driver circuit can be formed on the IC chip, shown in accompanying drawing 42B, can the IC chip be installed on the display board through COG (glass top chip) etc. then.
The structure of describing in the present embodiment is the instance of mobile phone, and display device of the present invention not only can be applied in the mobile phone with said structure, but also can be applied in the mobile phone of various types of structures.
(embodiment 9)
Accompanying drawing 48 has shown the EL module that has wherein made up display board 4801 and circuit board 4802.Display board 4801 comprises pixel portion 4803, scan line driver circuit 4804 and signal line drive circuit 4805.For example, control circuit 4806, signal segmentation circuit 4807 etc. are formed on the circuit board 4802.Display board 4801 interconnects through being connected distribution 4808 with circuit board 4802.FPC etc. can be with connecting distribution.
In display board 4801; Can be formed on the substrate with the part (the lower drive circuit of frequency of operation in a plurality of drive circuits) of integrated mode through using TFT, and can on the IC chip, form another part (the higher drive circuit of frequency of operation in a plurality of drive circuits) of peripheral driver circuit pixel portion and peripheral driver circuit.Can the IC chip be installed on the display board 4801 through COG (glass top chip) etc.Replacedly, can the IC chip be installed on the display board 4801 through using TAB (carrier band weldering automatically) or printed circuit board (PCB).Notice that accompanying drawing 42 has shown the instance of the structure of display board, wherein the part of peripheral driver circuit and pixel portion are integrated on the substrate, and the IC chip that has formed another part of peripheral driver circuit on it passes through installations such as COG.
In addition, in order further to reduce power consumption, can use TFT on glass substrate, to form pixel portion, all drive circuits can be formed on the IC chip, and can the IC chip be installed on the display board through COG (glass top chip) etc.Notice that accompanying drawing 42B has shown structure example, wherein pixel portion is formed on the substrate, and the IC chip with peripheral driver circuit is installed on the substrate through COG etc.
Can accomplish the EL television receiver with this EL module.Accompanying drawing 49 is the calcspars that show the primary structure of EL television receiver.Tuner 4901 receiving video signals and sound signal.Handle vision signal through video amplifier circuit 4902, video processing circuit 4903 and control circuit 4906; Wherein video processing circuit 4903 is used for the conversion of signals of video amplifier circuit 4902 outputs is become the colour signal corresponding to every kind of color of red, green, blue, and control circuit 4806 is used for vision signal is converted to the input standard of drive circuit.Control circuit 4806 outputs to scan line side and signal line side with corresponding signal.Under situation about driving, can be employed in signal line side and signal segmentation circuit 4807 is provided so that the structure of the digital signal that is divided into the m sheet is provided with digital form.
Sound signal in the signal that receives through tuner 4901 is sent to audio signal amplifier circuit 4904, and its output is transferred to loudspeaker 4906 through audio signal processing circuit 4905.Control circuit 4907 receives from the volume of importation 4908 or the control information of receiving station (receive frequency), and sends signal to tuner 4901 and audio signal processing circuit 4905.
Certainly, the present invention is not limited to the TV receiver, and can be applicable to various uses as the large scale show media, the message panel of locating such as station, airport etc., or the monitor of advertising display panel on the street and PC.
Naturally; The present invention not only can be used for television receiver, also can be used as large-sized display media and is applied in the various uses, for example at the train station, the message panel located such as airport; The display of the perhaps advertising display panel on the street, and personal computer.
The application is the basis with the Japanese patent application sequence number No.2005-148801 that on May 20th, 2005 submitted in Jap.P. office, and the full content of said application is incorporated this paper into way of reference.

Claims (22)

1. Actire matrix display device comprises:
The pixel portion that comprises a plurality of pixels, a plurality of signal wire and a plurality of sweep traces;
Be connected to the signal line drive circuit of said signal wire;
Be connected to the scan line driver circuit of said sweep trace; And
Confirm circuit, be configured to relatively to be input in the pixel of single row corresponding to have be used for to pixel write vision signal formerly and the data of the vision signal during a plurality of subframes regularly of back,
Wherein said scan line driver circuit comprises multistage trigger circuit and output control circuit;
Wherein when the signal that will be written to pixel column is identical with signal in being stored in this pixel column; This scan line driver circuit will not be used to select the strobe pulse of this pixel column to export to and the corresponding sweep trace of this pixel column through using said output control circuit; And when the signal that will be written to this pixel column was identical with signal in being stored in this pixel column, this signal line drive circuit placed quick condition with this signal wire; And
One of them by during gray level method is divided into a plurality of subframes according to overlapping time image duration.
2. Actire matrix display device according to claim 1, wherein said scan line driver circuit comprise that whether control export strobe pulse to the said output control circuit of sweep trace.
3. Actire matrix display device according to claim 1, wherein said signal line drive circuit comprise that whether control place signal wire the output control circuit of quick condition.
4. Actire matrix display device according to claim 1 wherein when the signal that will be written to pixel column is identical with signal in being stored in this pixel column, stops to import the vision signal that is transfused to the signal line drive circuit.
5. Actire matrix display device according to claim 1 wherein when the signal that will be written to pixel column is identical with signal in being stored in this pixel column, stops to import the clock signal and the inversion clock signal that are transfused to the signal line drive circuit.
6. electronic equipment that in the display part, comprises Actire matrix display device according to claim 1.
7. Actire matrix display device comprises:
The pixel portion that comprises a plurality of pixels, a plurality of signal wire and a plurality of sweep traces;
Be connected to the signal line drive circuit of said signal wire;
Be connected to the scan line driver circuit of said sweep trace; And
Confirm circuit, be configured to relatively to be input in the pixel of single row corresponding to have be used for to pixel write vision signal formerly and the data of the vision signal during a plurality of subframes regularly of back,
Wherein said scan line driver circuit comprises multistage trigger circuit and output control circuit;
Wherein when the signal that will be written to pixel column is identical with signal in being stored in this pixel column; This scan line driver circuit will not be used to select the strobe pulse of this pixel column to export to and the corresponding sweep trace of this pixel column through using said output control circuit; And when the signal that will be written to this pixel column was identical with signal in being stored in this pixel column, this signal line drive circuit did not change the state of original state to said signal wire output signal; And
One of them by during gray level method is divided into a plurality of subframes according to overlapping time image duration.
8. Actire matrix display device according to claim 7, wherein said scan line driver circuit comprise that whether control export strobe pulse to the said output control circuit of sweep trace.
9. Actire matrix display device according to claim 7 wherein when the signal that will be written to pixel column is identical with signal in being stored in this pixel column, stops to import the vision signal that is transfused to the signal line drive circuit.
10. Actire matrix display device according to claim 7 wherein when the signal that will be written to pixel column is identical with signal in being stored in this pixel column, stops to import the clock signal and the inversion clock signal that are transfused to the signal line drive circuit.
11. electronic equipment that in the display part, comprises Actire matrix display device according to claim 7.
12. a method that is used to drive Actire matrix display device, this display device comprises:
The pixel portion that comprises a plurality of pixels, a plurality of signal wire and a plurality of sweep traces;
Be connected to the signal line drive circuit of said signal wire;
Be connected to the scan line driver circuit of said sweep trace; And
Confirm circuit, be configured to relatively to be input in the pixel of single row corresponding to have be used for to pixel write vision signal formerly and the data of the vision signal during a plurality of subframes regularly of back,
Wherein said scan line driver circuit comprises multistage trigger circuit and output control circuit;
Said method comprises following step:
Relatively will be written to the signal of pixel column and be stored in the signal in this pixel column; With
When the signal that will be written to this pixel column is identical with signal in being stored in this pixel column, stop to select this pixel column, simultaneously signal wire is placed quick condition,
One of them by during gray level method is divided into a plurality of subframes according to overlapping time image duration.
13. the method that is used to drive Actire matrix display device according to claim 12, wherein said scan line driver circuit comprise that whether control export strobe pulse to the said output control circuit of sweep trace.
14. the method that is used to drive Actire matrix display device according to claim 12, wherein said signal line drive circuit comprise that whether control place signal wire the output control circuit of quick condition.
15. the method that is used to drive Actire matrix display device according to claim 12 wherein when the signal that will be written to pixel column is identical with signal in being stored in this pixel column, stops to import the vision signal that is transfused to the signal line drive circuit.
16. the method that is used to drive Actire matrix display device according to claim 12; Wherein when the signal that will be written to pixel column is identical with signal in being stored in this pixel column, stop to import the clock signal and the inversion clock signal that are transfused to the signal line drive circuit.
17. electronic equipment that in the display part, comprises use according to the Actire matrix display device of the driving method of claim 12.
18. a method that is used to drive Actire matrix display device, this display device comprises:
The pixel portion that comprises a plurality of pixels, a plurality of signal wire and a plurality of sweep traces;
Be connected to the signal line drive circuit of said signal wire;
Be connected to the scan line driver circuit of said sweep trace; And
Confirm circuit, be configured to relatively to be input in the pixel of single row corresponding to have be used for to pixel write vision signal formerly and the data of the vision signal during a plurality of subframes regularly of back,
Wherein said scan line driver circuit comprises multistage trigger circuit and output control circuit;
Said method comprises following step:
Relatively will be written to the signal of pixel column and be stored in the signal in this pixel column; With
When the signal that will be written to this pixel column is identical with signal in being stored in this pixel column, stop to select this pixel column, export signal to said signal wire simultaneously and do not change the state of original state,
One of them by during gray level method is divided into a plurality of subframes according to overlapping time image duration.
19. the method that is used to drive Actire matrix display device according to claim 18, wherein said scan line driver circuit comprise that whether control export strobe pulse to the said output control circuit of sweep trace.
20. the method that is used to drive Actire matrix display device according to claim 18 wherein when the signal that will be written to pixel column is identical with signal in being stored in this pixel column, stops to import the vision signal that is transfused to the signal line drive circuit.
21. the method that is used to drive Actire matrix display device according to claim 18; Wherein when the signal that will be written to pixel column is identical with signal in being stored in this pixel column, stop to import the clock signal and the inversion clock signal that are transfused to the signal line drive circuit.
22. electronic equipment that in the display part, comprises use according to the Actire matrix display device of the driving method of claim 18.
CN2006100824416A 2005-05-20 2006-05-19 Active matrix display device, method for driving the same, and electronic device Expired - Fee Related CN1866340B (en)

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