CN1849606A - 用于测试电路的方法 - Google Patents
用于测试电路的方法 Download PDFInfo
- Publication number
- CN1849606A CN1849606A CNA2004800260164A CN200480026016A CN1849606A CN 1849606 A CN1849606 A CN 1849606A CN A2004800260164 A CNA2004800260164 A CN A2004800260164A CN 200480026016 A CN200480026016 A CN 200480026016A CN 1849606 A CN1849606 A CN 1849606A
- Authority
- CN
- China
- Prior art keywords
- circuit
- predetermined
- network
- network node
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 40
- 230000005611 electricity Effects 0.000 claims description 19
- 238000012545 processing Methods 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000004088 simulation Methods 0.000 abstract description 6
- 230000005669 field effect Effects 0.000 description 6
- 230000002349 favourable effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000005284 excitation Effects 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 238000010998 test method Methods 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
ercDefines( defPins( pin "VSS"="P2" pin "VDD"="P1" ) shortDevices( short "MOS" excludingPinTypes "VSS" "VDD" ) )
/* 分配引脚类型和电压 */ ercDefines( defPins( pin"VSS" voltage 0 ="P5" "P3" pin"VINT"voltage 2.0="P2" "P4" pin"VPP" voltage 3.0="P1" ) /* 定义用于传递电压的器件和停止网络 */ shortDevices( short "MOS" BIG short "MOS" SMALL short "RES" value=<500 excludingPinTypes "VPP" "VINT" "VSS" )
/* 测试规则 */ reportDevice( "MOS" models SMALL condition nodeVoltage(voltage "GATE" - voltage "SDRAIN" >"VINT") || nodeVoltage(voltage "SDRAIN" - voltage "GATE" > "VINT") title "SMALL MOS,voltage difference Gate- Source/Drain/Substrate> VINT" )
reportDevice( "MOS" models P_SMALL condition length<280 && nodeVoltage(voltage "SDRAIN" > "vint") && nodeVoltage(voltage "SOURCE" - voltage "DRAIN" > "vint") title "Small PMOS,length<280,voltage SOURCE-DRAIN> vint" )
Claims (13)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10343346A DE10343346B4 (de) | 2003-09-12 | 2003-09-12 | Verfahren zum Prüfen einer elektrischen Schaltung und Einrichtung zur Durchführung des Verfahrens |
DE10343346.5 | 2003-09-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1849606A true CN1849606A (zh) | 2006-10-18 |
CN100429663C CN100429663C (zh) | 2008-10-29 |
Family
ID=34305904
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004800260164A Expired - Fee Related CN100429663C (zh) | 2003-09-12 | 2004-09-07 | 用于测试电路的方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7313498B2 (zh) |
EP (1) | EP1665105A2 (zh) |
JP (1) | JP2007505296A (zh) |
CN (1) | CN100429663C (zh) |
DE (1) | DE10343346B4 (zh) |
WO (1) | WO2005026995A2 (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10343344B4 (de) * | 2003-09-12 | 2006-04-20 | Infineon Technologies Ag | Verfahren zum Prüfen einer elektrischen Schaltung |
CN100452062C (zh) * | 2006-01-13 | 2009-01-14 | 大同股份有限公司 | 测试硬件描述语言所撰写的硬件电路方块的方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3851161A (en) * | 1973-05-07 | 1974-11-26 | Burroughs Corp | Continuity network testing and fault isolating |
US4590472A (en) * | 1982-12-01 | 1986-05-20 | General Electric Company | Analog signal conditioner for thermal coupled signals |
US4837502A (en) * | 1983-11-04 | 1989-06-06 | Grumman Aerospace Corporation | Computer-aided, logic pulsing probe for locating faulty circuits on a printed circuit card |
JPH04335443A (ja) * | 1990-12-28 | 1992-11-24 | General Electric Co <Ge> | システム内の不良部品を隔離する方法と装置 |
US5568142A (en) * | 1994-10-20 | 1996-10-22 | Massachusetts Institute Of Technology | Hybrid filter bank analog/digital converter |
US5488323A (en) * | 1994-12-14 | 1996-01-30 | United Technologies Corporation | True hysteresis window comparator for use in monitoring changes in switch resistance |
US5588142A (en) * | 1995-05-12 | 1996-12-24 | Hewlett-Packard Company | Method for simulating a circuit |
US5627478A (en) * | 1995-07-06 | 1997-05-06 | Micron Technology, Inc. | Apparatus for disabling and re-enabling access to IC test functions |
US5831437A (en) * | 1996-01-05 | 1998-11-03 | Rutgers University | Test generation using signal flow graphs |
US6117179A (en) * | 1998-02-23 | 2000-09-12 | Advanced Micro Devices, Inc. | High voltage electrical rule check program |
US6055366A (en) * | 1998-02-23 | 2000-04-25 | Advanced Micro Devices, Inc. | Methods and apparatus to perform high voltage electrical rule check of MOS circuit design |
US6499129B1 (en) * | 1998-07-22 | 2002-12-24 | Circuit Semantics, Inc. | Method of estimating performance of integrated circuit designs |
WO2000057317A1 (en) * | 1999-03-19 | 2000-09-28 | Moscape, Inc. | System and method for performing assertion-based analysis of circuit designs |
US6389578B1 (en) * | 1999-05-26 | 2002-05-14 | Hewlett-Packard Company | Method and apparatus for determining the strengths and weaknesses of paths in an integrated circuit |
US20030093504A1 (en) * | 2001-10-31 | 2003-05-15 | Tilmann Neunhoeffer | Method for processing data containing information about an electronic circuit having a plurality of hierarchically organized networks, computer readable storage medium and data processing system containing computer-executable instructions for performing the method |
US6898546B2 (en) * | 2001-10-31 | 2005-05-24 | Infineon Technologies Ag | Method for processing data representing parameters relating to a plurality of components of an electrical circuit, computer readable storage medium and data processing system containing computer-executable instructions for performing the method |
US7240316B2 (en) * | 2002-04-16 | 2007-07-03 | Micron Technology, Inc. | Apparatus and method to facilitate hierarchical netlist checking |
US7073111B2 (en) * | 2002-06-10 | 2006-07-04 | Texas Instruments Incorporated | High speed interconnect circuit test method and apparatus |
-
2003
- 2003-09-12 DE DE10343346A patent/DE10343346B4/de not_active Expired - Fee Related
-
2004
- 2004-09-07 CN CNB2004800260164A patent/CN100429663C/zh not_active Expired - Fee Related
- 2004-09-07 EP EP04786733A patent/EP1665105A2/de not_active Withdrawn
- 2004-09-07 JP JP2006525619A patent/JP2007505296A/ja active Pending
- 2004-09-07 WO PCT/DE2004/002011 patent/WO2005026995A2/de active Search and Examination
-
2006
- 2006-03-09 US US11/372,470 patent/US7313498B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
WO2005026995A3 (de) | 2005-09-01 |
EP1665105A2 (de) | 2006-06-07 |
JP2007505296A (ja) | 2007-03-08 |
WO2005026995A2 (de) | 2005-03-24 |
US7313498B2 (en) | 2007-12-25 |
US20060212236A1 (en) | 2006-09-21 |
DE10343346B4 (de) | 2011-01-27 |
CN100429663C (zh) | 2008-10-29 |
DE10343346A1 (de) | 2005-04-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
C56 | Change in the name or address of the patentee | ||
CP01 | Change in the name or title of a patent holder |
Address after: Munich, Germany Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: Infineon Technologies AG |
|
TR01 | Transfer of patent right |
Effective date of registration: 20120920 Address after: Munich, Germany Patentee after: QIMONDA AG Address before: Munich, Germany Patentee before: Infineon Technologies AG |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20151229 Address after: German Berg, Laura Ibiza Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: QIMONDA AG |
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CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081029 Termination date: 20170907 |
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CF01 | Termination of patent right due to non-payment of annual fee |