CN1794408A - Panel display having adulterated polycrystal silicon field emission cathode array structure and its manufacturing technology - Google Patents
Panel display having adulterated polycrystal silicon field emission cathode array structure and its manufacturing technology Download PDFInfo
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Abstract
This invention relates to a panel display with doped-polysilicon field emission cathode array structure and its process technology, in which, the display includes a sealed vacuum cavity composed of a cathode panel, an anode panel and surrounding glasses, anode conduction strips etched on the anode panel and fluorescence powder layer on the conduction strips, a supporting wall and getter attached elements, in which, a doped polysilicon field emission cathode array structure is prepared on the cathode panel to reduce the distance between the cathode and the grating, control the working voltage of the grating and reduce the current of the control grating.
Description
Technical field
The invention belongs to the mutual crossing domain in Display Technique field, plane, microelectronics science and technology field, vacuum science and technical field and nanoscale science and technology field, relate to the element manufacturing of panel field emission display, be specifically related to the content of element manufacturing aspect of the panel field emission display of carbon nanotube cathod, specially refer to and have a kind of manufacture craft that has field emission flat panel display device adulterated polycrystal silicon field emission cathode array structure, carbon nanotube cathod.
Background technology
Carbon nano-tube has little tip curvature radius, high aspect rate, and good field emission characteristics and good physical and chemical stability are a kind of quite outstanding cold cathode emissive materials, have caused showing great attention to of numerous researchers.Carbon nano-tube itself is exactly a kind of coaxial tubulose material, can launch a large amount of electronics under the alive outside situation.Utilizing carbon nano-tube is a kind of emerging field emission types of display part as the flat-panel monitor of cathode material, has advantages such as high brightness, complanation and high definition, and it is used more and more widely, has sizable development space future.In order to effectively reduce the total device cost, reduce the operating voltage of device, so that can combine with the integrated drive electronics of routine, the field emission display device of making three-stage structure has become a kind of inevitable choice.
The distance of control grid and carbon nanotube cathod is a key factor that influences the device operating voltage.Distance between control grid and the carbon nanotube cathod is more little, the voltage that is applied to the control grid forms powerful electric field strength with regard to easy more on the carbon nano-tube top, force carbon nanotube cathod to launch a large amount of electronics, meanwhile, the voltage that is applied on the grid is also just very low, and this is favourable one side; But, because very big of the electric field strength on carbon nano-tube top, so just the insulating barrier between control grid and the carbon nano-tube is had higher requirement, promptly must have the good insulation performance performance, guarantee the class of insulation between the two, the electrical break down phenomenon can not take place, thickness is also as much as possible little simultaneously, avoid between the two distance excessive, promote the control operating voltage of grid.So just insulating barrier is had higher requirement, can sharply increase the overall cost of element manufacturing at aspects such as technology and materials.So, how on earth handle the distance between control grid and the carbon nanotube cathod well, also will reduce the cost of manufacture of device in the operating voltage that should reduce device, this is the realistic problem that the researcher need contemplate.
In addition,, also need to reduce as much as possible the total device cost, carry out reliable and stable, with low cost, function admirable, high quality devices is made guaranteeing that grid structure has carbon nanotube cathod under the prerequisite of good control action.
Summary of the invention
The objective of the invention is to overcome the shortcoming that exists in the above-mentioned flat-panel display device and provide a kind of with low cost, manufacturing process is reliable and stable, be made into the power height, flat-panel display device that has adulterated polycrystal silicon field emission cathode array structure and manufacture craft thereof simple in structure.
The object of the present invention is achieved like this:
A kind of flat-panel monitor that has doped polycrystalline silicon field-emission cathode array structure comprise by negative electrode panel, anode plate and all around glass enclose the sealed vacuum chamber that frame constitutes; The anode conducting bar that on anode plate, makes by lithography and be produced on phosphor powder layer above the anode conducting bar; Knee wall and getter subsidiary component are manufactured with doped polycrystalline silicon field-emission cathode array structure on the negative electrode panel.
Described doped polycrystalline silicon field-emission cathode array structure comprises the negative electrode panel, the intermediate metal that carves at negative electrode panel glazing, the doped polysilicon layer that on intermediate metal, is manufactured with, evaporation has catalyst metal layer on doped polysilicon layer, in the preparation of the outside of catalyst metal layer silicon dioxide insulating layer is arranged, on silicon dioxide insulating layer, be manufactured with gate metal layer, on gate metal layer, prepare the silicon dioxide cover layer, to the silicon dioxide cover layer, gate metal layer, silicon dioxide insulating layer, the catalyst metal layer etching forms pattern, doped polysilicon layer after the etching is that high two ends, a centre are low, and having the vertebra shape structure of vertebra point, catalyst metal layer is present near the tip of taper doped polycrystalline silicon.
The fixed position of described doped polycrystalline silicon field-emission cathode array structure is for being fixed on the negative electrode panel, the negative electrode panel of doped polycrystalline silicon field-emission cathode array structure is a glass substrate material, and the layer of metal transition zone that exists on the negative electrode panel is one of gold, silver, aluminium, nickel, molybdenum, tin.
Having doped polysilicon layer above the intermediate metal of described doped polycrystalline silicon field-emission cathode array structure is p type or for the n type.
Have a catalyst metal layer above the doped polysilicon layer of described doped polycrystalline silicon field-emission cathode array structure, this catalyst metal layer is one of metallic iron, cobalt, nickel, chromium; Gate metal layer of the top existence of silicon dioxide insulating layer, gate metal layer is one of metal gold, silver, aluminium, tin, indium, niobium; Silicon dioxide cover layer of the top existence of gate metal layer will cover whole gate metal layer.
A kind of manufacture craft that has the carbon nanotube field emission flat-panel monitor of doped polycrystalline silicon field-emission cathode array structure, manufacture craft is as follows:
The growth of A, carbon nanotube cathod: the catalyst that utilizes catalyst metal layer to use as carbon nano-tube, in conjunction with cryochemistry vapor deposition direct growth method, near the doped polysilicon layer tip of cone structure, prepare carbon nanotube cathod;
The making of B, anode plate:
1), cleaning plate glass, remove surface impurity, form anode plate;
2), evaporation one deck tin indium oxide film on anode plate;
3), tin indium oxide film is carried out photoetching, formation anode conducting bar;
4), in conjunction with silk-screen printing technique, non-display area printing insulation paste layer at the anode conducting bar, after toasting 5～15 minutes under 150 ℃ ± 10 ℃ temperature conditions, be placed on the high temperature sintering that carries out 580 ℃ ± 10 ℃ in the sintering furnace, the retention time is 5～15 minutes;
5). in conjunction with silk-screen printing technique, the viewing area printing phosphor powder layer on the anode conducting bar is placed in the baking oven, and baking is 5～15 minutes under 120 ℃ ± 10 ℃ temperature conditions;
C, device assembling: with backing material glass, anode plate, doped polycrystalline silicon field-emission cathode array structure and glass encloses frame, supporting wall structure is assembled together, and getter put in the middle of the cavity, fix with glass powder with low melting point, around face glass, smeared glass powder with low melting point, fixed with clip;
D, finished product are made: the device that has assembled is carried out following packaging technology:
1), in the middle of being put into baking oven, toasts by the sample device;
2), carry out high temperature sintering in the middle of putting into sintering furnace;
3), on exhaust station, carry out device exhaust, sealed-off, on the roasting machine that disappears, the getter of device inside baked and disappears, install pin at last additional and form needed flat-panel monitor.
Doped polycrystalline silicon field-emission cathode array structure comprises backing material glass, intermediate metal, doped polysilicon layer, catalyst metal layer, silicon dioxide insulating layer, gate metal layer and silicon dioxide cover layer part, and adopts following technology to make:
1), the making of backing material glass: whole glass is carried out scribing, form backing material glass; This backing material glass is the negative electrode panel just;
2), the making of intermediate metal: at backing material evaporation last layer on glass metal, in conjunction with conventional photoetching process, metal level is carried out etching then, form intermediate metal;
3), the making of doped polysilicon layer: making doped polysilicon layer on intermediate metal, in conjunction with conventional photoetching process, doped polysilicon layer is carried out etching, and the doped polysilicon layer after the etching is that high two ends, a centre are low, and has the vertebra shape structure of vertebra point;
4), the making of catalyst metal layer: catalyst metal layer of evaporation on doped polysilicon layer;
5), the making of silicon dioxide insulating layer: on catalyst metal layer, prepare silicon dioxide insulating layer,
6), the making of gate metal layer: metal level of evaporation on silicon dioxide insulating layer forms gate metal layer;
7), the tectal making of silicon dioxide: on gate metal layer, prepare the silicon dioxide cover layer, cover whole gate metal layer;
8), the tectal etching of silicon dioxide: in conjunction with conventional photoetching process, the silicon dioxide cover layer is carried out etching, form pattern;
9), the etching of gate metal layer: in conjunction with conventional photoetching process, gate metal layer is carried out etching, form pattern;
10), the etching of silicon dioxide insulating layer: in conjunction with conventional photoetching process, silicon dioxide insulating layer is carried out etching, form pattern;
11), the etching of catalyst metal layer: in conjunction with conventional photoetching process, catalyst metal layer is carried out etching, form pattern; Catalyst metal layer exists only near the tip of taper doped polycrystalline silicon;
12), cleaning surfaces is handled: clean is carried out on the surface to whole doped polycrystalline silicon field-emission cathode array structure, removes dust and impurity.
The present invention has following good effect:
Main characteristics among the present invention are to have made doped polycrystalline silicon field-emission cathode array structure, and have made and have doped polycrystalline silicon field-emission cathode array field emission flat light-emitting display device structure, carbon nanotube cathod.
At first, utilize the sharp vertebra shape doped polycrystalline silicon of etching to make carbon nanotube cathod, help reducing working voltage of device effectively in the distance that shortens under the prerequisite that does not increase the integral device cost between carbon nanotube cathod and the grid as base material.Utilize doped polysilicon layer to be easy to produce shape, and the characteristic that can conduct electricity, as the base material of carbon nanotube cathod; High two ends were low and have a sharp vertebra shape structure of vertebra point in the middle of doped polycrystalline silicon was etched into, then near the vertebra point evaporation catalyst metal layer, the catalyst metal layer at all the other positions is all etched away, like this, utilize this metal level as catalyst, just can carry out the direct growth method and prepare carbon nanotube cathod.Prepared carbon nanotube cathod all concentrates near the vertebra point of doped polycrystalline silicon, also helps increasing the electric field strength on carbon nano-tube top; By the thickness of control preparation silicon dioxide insulating layer, and the etching speed and the etch period of control gate metal layer, the distance between grid and the carbon nanotube cathod just can be controlled effectively.Certainly, also can effectively control distance between the two by the height of adjusting doped polycrystalline silicon.On the one hand, height by further lifting doped polysilicon layer, perhaps reduce the thickness of silicon dioxide layer, just can effectively shorten the distance between gate metal layer and the carbon nanotube cathod layer, reduce the operating voltage of device, on the other hand, in manufacturing process, do not adopt special manufacture craft, do not adopt special manufacturing materials yet, can not increase the cost of manufacture of device like this.
Secondly, owing near the tip of the doped polycrystalline silicon of sharp vertebra shape, made catalyst metal layer, and can carry out the growth of carbon nanotube cathod, like this, when making full use of the good field emission characteristics of carbon nanotubes grown, also that the making of the making of carbon nanotube cathod and grid is highly together integrated, help further promoting the integrated level of integral device, simplify the manufacture craft and the manufacturing process of device.
The 3rd, on the negative electrode panel, made intermediate metal, this intermediate metal serves as the lead-in wire of carbon nanotube cathod on the one hand, make it possible to successfully applied voltage is applied on the carbon nanotube cathod, also doped polysilicon layer and substrate glass are kept apart mutually simultaneously, play a cushioning effect, prevent from the manufacturing process of device, to burst, improved the power that is made into of device.
In addition, in the doped polycrystalline silicon field-emission cathode array structure in the present invention, do not adopt special structure fabrication material, do not adopt special device making technics yet, this has just further reduced the cost of manufacture of whole flat-panel display device to a great extent, simplify the manufacturing process of device, can carry out large-area element manufacturing, helped carrying out business-like large-scale production.
Description of drawings
Fig. 1 has provided the vertical structure schematic diagram of doped polycrystalline silicon field-emission cathode array structure;
Fig. 2 has provided the transversary schematic diagram of doped polycrystalline silicon field-emission cathode array structure;
Fig. 3 has provided and has had structural representation doped polycrystalline silicon field-emission cathode array structure, the carbon nanotube field emission flat-panel screens.
Embodiment
Below in conjunction with drawings and Examples the present invention is further specified, but the present invention is not limited to these embodiment.
As shown in Figure 3, the present invention includes by negative electrode panel 1 (being backing material glass 1), anode plate 9 and all around glass enclose the sealed vacuum chamber that frame 15 is constituted; The anode conducting bar 10 that on anode plate 9, makes by lithography and be produced on phosphor powder layer 11 above the anode conducting bar 10; Insulation paste layer 12 in the printing of the non-display area of anode conducting bar 10; Be arranged on knee wall 13 and getter subsidiary component 14 between negative electrode panel 1 and the anode plate 9, on negative electrode panel 1, be manufactured with doped polycrystalline silicon field-emission cathode array structure.On the negative electrode panel, be manufactured with adulterated polycrystal silicon field emission cathode array structure and carbon nanotube cathod; The control grid that is used for the emission of controlling carbon nanotube cathode electronics; Doped polycrystalline silicon field-emission cathode array structure, can reduce the distance between carbon nanotube cathod and the grid effectively, reduce the control operating voltage of grid, reduce to control the electric current of grid, help further improving the display resolution of flat-panel display device, simplify the manufacture craft of device, reduce the cost of manufacture of device.
As Fig. 1, shown in 2, described doped polycrystalline silicon field-emission cathode array structure comprises negative electrode panel 1, the intermediate metal 2 that on negative electrode panel 1, makes by lithography, the doped polysilicon layer 3 that on intermediate metal 2, is manufactured with, evaporation has catalyst metal layer 4 on doped polysilicon layer 3, in the preparation of the outside of catalyst metal layer 4 silicon dioxide insulating layer 5 is arranged, on silicon dioxide insulating layer 5, be manufactured with gate metal layer 6, on gate metal layer 6, prepare silicon dioxide cover layer 7, to silicon dioxide cover layer 7, gate metal layer 6, silicon dioxide insulating layer 5, catalyst metal layer 4 etchings form pattern, doped polysilicon layer 3 after the etching is that high two ends, a centre are low, and having the vertebra shape structure of vertebra point, catalyst metal layer 4 is present near the tip of taper doped polycrystalline silicon.
The fixed position of described doped polycrystalline silicon field-emission cathode array structure is for being fixed on the negative electrode panel, the negative electrode panel 1 of doped polycrystalline silicon field-emission cathode array structure is a glass substrate material, and the layer of metal transition zone that exists on the negative electrode panel is one of gold, silver, aluminium, nickel, molybdenum, tin.
Having doped polysilicon layer above the intermediate metal of described doped polycrystalline silicon field-emission cathode array structure is p type or for the n type.
Have a catalyst metal layer above the doped polysilicon layer of described doped polycrystalline silicon field-emission cathode array structure, this catalyst metal layer is one of metallic iron, cobalt, nickel, chromium; Gate metal layer of the top existence of silicon dioxide insulating layer, gate metal layer is one of metal gold, silver, aluminium, tin, indium, niobium; Silicon dioxide cover layer of the top existence of gate metal layer will cover whole gate metal layer.
The fixed position of the doped polycrystalline silicon field-emission cathode array structure among the present invention is for being fixed on the negative electrode panel; The backing material of the doped polycrystalline silicon field-emission cathode array structure among the present invention be large-scale, have quite good thermal endurance and operability, a High Performance Insulation material with low cost; The backing material of the doped polycrystalline silicon field-emission cathode array structure among the present invention is a glass, and negative electrode panel just is as soda-lime glass, Pyrex; Have the layer of metal transition zone on the negative electrode panel of the doped polycrystalline silicon field-emission cathode array structure among the present invention, this intermediate metal can be gold, silver, aluminium, nickel, molybdenum, tin; Intermediate metal among the present invention can form pattern in conjunction with the photoetching process of routine; There is doped polysilicon layer above the intermediate metal of the doped polycrystalline silicon field-emission cathode array structure among the present invention; Doped polysilicon layer in the doped polycrystalline silicon field-emission cathode array structure among the present invention can be one deck, also can be multilayer; Doped polycrystalline silicon in the doped polycrystalline silicon field-emission cathode array structure among the present invention can be the p type, also can be the n type; Doped polysilicon layer in the doped polycrystalline silicon field-emission cathode array structure among the present invention can form pattern in conjunction with the photoetching process etching of routine; Doped polysilicon layer in the doped polycrystalline silicon field-emission cathode array structure among the present invention after the etching is that high two ends, a centre are low, and has the vertebra shape structure of vertebra point; Have a catalyst metal layer above the doped polysilicon layer in the doped polycrystalline silicon field-emission cathode array structure among the present invention, this catalyst metal layer can be metallic iron, cobalt, nickel, chromium; Catalyst metal layer in the doped polycrystalline silicon field-emission cathode array structure among the present invention can form pattern in conjunction with the photoetching process of routine; Catalyst metal layer after the etching in the doped polycrystalline silicon field-emission cathode array structure among the present invention only exists only near the tip of taper doped polycrystalline silicon; Silicon dioxide insulating layer of top existence of doped polysilicon layer in the doped polycrystalline silicon field-emission cathode array structure among the present invention; Silicon dioxide insulating layer in the doped polycrystalline silicon field-emission cathode array structure among the present invention can form pattern in conjunction with the photoetching process of routine; Gate metal layer of top existence of silicon dioxide insulating layer in the doped polycrystalline silicon field-emission cathode array structure among the present invention; Gate metal layer in the doped polycrystalline silicon field-emission cathode array structure among the present invention can form pattern in conjunction with the photoetching process of routine; Gate metal layer in the doped polycrystalline silicon field-emission cathode array structure among the present invention can be metallic gold, silver, aluminium, tin, indium, niobium; Silicon dioxide cover layer of top existence of gate metal layer in the doped polycrystalline silicon field-emission cathode array structure among the present invention will cover whole gate metal layer.
The manufacture craft of carbon nanotube field emission flat-panel monitor that has doped polycrystalline silicon field-emission cathode array structure among the present invention is as follows:
The growth of A, carbon nanotube cathod 8: the catalyst that utilizes catalyst metal layer to use as carbon nano-tube, in conjunction with cryochemistry vapor deposition direct growth method, near the doped polysilicon layer tip of cone structure, prepare carbon nano-tube [8] negative electrode;
The reprocessing of B, carbon nanotube cathod 8: conventional treatment process (as pickling) commonly used carries out reprocessing to carbon nanotube cathod, with the further field emission characteristics that improves carbon nanotube cathod.
The making of C, anode plate:
1), cleaning plate glass, remove surface impurity, form anode plate 9;
2), evaporation one deck tin indium oxide film on anode plate 9;
3), tin indium oxide film is carried out photoetching, formation anode conducting bar 10;
4), in conjunction with silk-screen printing technique, non-display area printing insulation paste layer 12 at anode conducting bar 10, be used to prevent the parasitic electrons emission, after under 150 ℃ ± 10 ℃ temperature conditions, toasting 5～15 minutes, be placed on the high temperature sintering that carries out 580 ℃ ± 10 ℃ in the sintering furnace, the retention time is 5～15 minutes;
5). in conjunction with silk-screen printing technique, the viewing area printing phosphor powder layer 11 on anode conducting bar 10 is placed in the baking oven, and baking is 5～15 minutes under 120 ℃ ± 10 ℃ temperature conditions;
The assembling of D, device: with backing material glass 1, anode plate 9, doped polycrystalline silicon field-emission cathode array structure and glass enclose frame 15, knee wall 13 structures are assembled together, and getter 14 put in the middle of the cavity, fix with glass powder with low melting point, around face glass, smeared glass powder with low melting point, fixed with clip;
E, finished product are made: the device that has assembled is carried out following packaging technology:
1), in the middle of being put into baking oven, toasts by the sample device;
2), carry out high temperature sintering in the middle of putting into sintering furnace;
3), on exhaust station, carry out device exhaust, sealed-off, on the roasting machine that disappears, the getter of device inside baked and disappears, install pin at last additional and form needed flat-panel monitor.
Doped polycrystalline silicon field-emission cathode array structure among the present invention comprises backing material glass 1, intermediate metal 2, doped polysilicon layer 3, catalyst metal layer 4, silicon dioxide insulating layer 5, gate metal layer 6 and silicon dioxide cover layer 7 parts, and adopts following technology to make:
1, the making of backing material glass 1: whole glass is carried out scribing, form backing material glass 1; This backing material glass 1 is the negative electrode panel just;
2, the making of intermediate metal 2: evaporation last layer crome metal on backing material glass 1, in conjunction with conventional photoetching process, metallic chromium layer is carried out etching then, form intermediate metal 2;
3, the making of doped polysilicon layer 3: on intermediate metal 2, make n type doped polysilicon layer 3.In conjunction with conventional photoetching process, doped polysilicon layer 3 is carried out etching, the doped polysilicon layer after the etching is that high two ends, a centre are low, and has the vertebra shape structure of vertebra point;
4, the making of catalyst metal layer 4: metal nickel dam of evaporation on 3 layers of doped polycrystalline silicon, promptly catalyst metal layer 4;
5, the making of silicon dioxide insulating layer 5: on catalyst metal layer 4, prepare silicon dioxide insulating layer 5.This silicon dioxide insulating layer both can be one deck, also can be multilayer;
6, the making of gate metal layer 6: metallic silver layer of evaporation on silicon dioxide insulating layer 5 forms gate metal layer 6;
7, the making of silicon dioxide cover layer 7: on gate metal layer 6, prepare silicon dioxide cover layer 7; Cover whole gate metal layer;
8, the etching of silicon dioxide cover layer 7: in conjunction with conventional photoetching process, silicon dioxide cover layer 7 is carried out etching, form pattern;
9, the etching of gate metal layer 6: in conjunction with conventional photoetching process, gate metal layer 6 is carried out etching, form pattern;
10, the etching of silicon dioxide insulating layer 5: in conjunction with conventional photoetching process, silicon dioxide insulating layer 5 is carried out etching, form pattern;
11, the etching of catalyst metal layer 4: in conjunction with conventional photoetching process, catalyst metal layer 4 is carried out etching, form pattern; Catalyst metal layer only exists only near the tip of taper doped polycrystalline silicon;
12, cleaning surfaces is handled: clean is carried out on the surface to whole doped polycrystalline silicon field-emission cathode array structure, removes dust and impurity.
Claims (7)
1, a kind of flat-panel monitor of doped polycrystalline silicon field-emission cathode array structure, comprise by negative electrode panel [1], anode plate [9] and all around glass enclose the sealed vacuum chamber that frame [15] is constituted; The anode conducting bar [10] that on anode plate [9], makes by lithography and be produced on phosphor powder layer [11] above the anode conducting bar [10]; Knee wall [13] and getter subsidiary component [14] is characterized in that: be manufactured with doped polycrystalline silicon field-emission cathode array structure on negative electrode panel [1].
2, a kind of flat-panel monitor that has doped polycrystalline silicon field-emission cathode array structure according to claim 1, it is characterized in that: described doped polycrystalline silicon field-emission cathode array structure comprises negative electrode panel [1], the intermediate metal [2] that on negative electrode panel [1], makes by lithography, the doped polysilicon layer [3] that on intermediate metal [2], is manufactured with, evaporation has catalyst metal layer [4] on doped polysilicon layer [3], in the preparation of the outside of catalyst metal layer [4] silicon dioxide insulating layer [5] is arranged, on silicon dioxide insulating layer [5], be manufactured with gate metal layer [6], on gate metal layer [6], prepare silicon dioxide cover layer [7], to silicon dioxide cover layer [7], gate metal layer [6], silicon dioxide insulating layer [5], catalyst metal layer [4] etching forms pattern, doped polysilicon layer after the etching [3] is that high two ends, a centre are low, and having the vertebra shape structure of vertebra point, catalyst metal layer [4] is present near the tip of taper doped polycrystalline silicon.
3, a kind of flat-panel monitor that has doped polycrystalline silicon field-emission cathode array structure according to claim 2, it is characterized in that: the fixed position of described doped polycrystalline silicon field-emission cathode array structure is for being fixed on the negative electrode panel, the negative electrode panel [1] of doped polycrystalline silicon field-emission cathode array structure is a glass substrate material, and the layer of metal transition zone that exists on the negative electrode panel is one of gold, silver, aluminium, nickel, molybdenum, tin.
4, a kind of flat-panel monitor that has doped polycrystalline silicon field-emission cathode array structure according to claim 2 is characterized in that: having doped polysilicon layer above the intermediate metal of described doped polycrystalline silicon field-emission cathode array structure is p type or for the n type.
5, a kind of flat-panel monitor that has doped polycrystalline silicon field-emission cathode array structure according to claim 2, it is characterized in that: have a catalyst metal layer above the doped polysilicon layer of described doped polycrystalline silicon field-emission cathode array structure, this catalyst metal layer is one of metallic iron, cobalt, nickel, chromium; Gate metal layer of the top existence of silicon dioxide insulating layer, gate metal layer is one of metal gold, silver, aluminium, tin, indium, niobium; Silicon dioxide cover layer of the top existence of gate metal layer will cover whole gate metal layer.
6, a kind of manufacture craft that has the carbon nanotube field emission flat-panel monitor of doped polycrystalline silicon field-emission cathode array structure, it is characterized in that: manufacture craft is as follows:
The growth of A, carbon nanotube cathod [8]: the catalyst that utilizes catalyst metal layer [4] to use as carbon nano-tube, in conjunction with cryochemistry vapor deposition direct growth method, near the doped polysilicon layer tip of cone structure, prepare carbon nanotube cathod [8];
The making of B, anode plate:
1), cleaning plate glass, remove surface impurity, form anode plate [9];
2), go up evaporation one deck tin indium oxide film at anode plate [9];
3), tin indium oxide film is carried out photoetching, formation anode conducting bar [10];
4), in conjunction with silk-screen printing technique, non-display area printing insulation paste layer [12] at anode conducting bar [10], after toasting 5～15 minutes under 150 ℃ ± 10 ℃ temperature conditions, be placed on the high temperature sintering that carries out 580 ℃ ± 10 ℃ in the sintering furnace, the retention time is 5～15 minutes;
5). in conjunction with silk-screen printing technique, the viewing area printing phosphor powder layer [11] on anode conducting bar [10] is placed in the baking oven, and baking is 5～15 minutes under 120 ℃ ± 10 ℃ temperature conditions;
The assembling of C, device: with backing material glass [1], anode plate [9], doped polycrystalline silicon field-emission cathode array structure and glass enclose frame [15], supporting wall structure [13] is assembled together, and getter [14] put in the middle of the cavity, fix with glass powder with low melting point, around face glass, smeared glass powder with low melting point, fixed with clip;
D, finished product are made: the device that has assembled is carried out following packaging technology:
1), in the middle of being put into baking oven, toasts by the sample device;
2), carry out high temperature sintering in the middle of putting into sintering furnace;
3), on exhaust station, carry out device exhaust, sealed-off, on the roasting machine that disappears, the getter of device inside baked and disappears, install pin at last additional and form needed flat-panel monitor.
7, a kind of manufacture craft that has the carbon nanotube field emission flat-panel monitor of doped polycrystalline silicon field-emission cathode array structure according to claim 6, it is characterized in that: doped polycrystalline silicon field-emission cathode array structure comprises backing material glass [1], intermediate metal [2], doped polysilicon layer [3], catalyst metal layer [4], silicon dioxide insulating layer [5], gate metal layer [6] and silicon dioxide cover layer [7] part, and adopts following technology to make:
1), the making of backing material glass [1]: whole glass is carried out scribing, form backing material glass [1];
2), the making of intermediate metal [2]: go up evaporation last layer metal at backing material glass [1], then
In conjunction with conventional photoetching process, metal level is carried out etching, form intermediate metal [2];
3), the making of doped polysilicon layer [3]: making doped polysilicon layer [3] on intermediate metal [2], in conjunction with conventional photoetching process, doped polysilicon layer [3] is carried out etching, and the doped polysilicon layer after the etching is that high two ends, a centre are low, and has the vertebra shape structure of vertebra point;
4), the making of catalyst metal layer [4] a: catalyst metal layer of evaporation [4] on doped polycrystalline silicon [3] layer;
5), the making of silicon dioxide insulating layer [5]: on catalyst metal layer [4], prepare silicon dioxide insulating layer [5],
6), the making of gate metal layer [6]: metal level of evaporation on silicon dioxide insulating layer [5] forms gate metal layer [6];
7), the making of silicon dioxide cover layer [7]: on gate metal layer [6], prepare silicon dioxide cover layer [7], cover whole gate metal layer;
8), the etching of silicon dioxide cover layer [7]: in conjunction with conventional photoetching process, silicon dioxide cover layer [7] is carried out etching, form pattern;
9), the etching of gate metal layer [6]: in conjunction with conventional photoetching process, gate metal layer [6] is carried out etching, form pattern;
10), the etching of silicon dioxide insulating layer [5]: in conjunction with conventional photoetching process, silicon dioxide insulating layer [5] is carried out etching, form pattern;
11), the etching of catalyst metal layer [4]: in conjunction with conventional photoetching process, catalyst metal layer [4] is carried out etching, form pattern; Catalyst metal layer exists only near the tip of taper doped polycrystalline silicon;
12), cleaning surfaces is handled: clean is carried out on the surface to whole doped polycrystalline silicon field-emission cathode array structure, removes dust and impurity.
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