CN1681097A - 半导体芯片安装体的制造方法和半导体芯片安装体 - Google Patents

半导体芯片安装体的制造方法和半导体芯片安装体 Download PDF

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Publication number
CN1681097A
CN1681097A CN 200410058664 CN200410058664A CN1681097A CN 1681097 A CN1681097 A CN 1681097A CN 200410058664 CN200410058664 CN 200410058664 CN 200410058664 A CN200410058664 A CN 200410058664A CN 1681097 A CN1681097 A CN 1681097A
Authority
CN
China
Prior art keywords
mentioned
semiconductor chip
resin sheet
thermosetting resin
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN 200410058664
Other languages
English (en)
Chinese (zh)
Inventor
青木慎
细田邦康
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN1681097A publication Critical patent/CN1681097A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
CN 200410058664 2004-04-09 2004-07-27 半导体芯片安装体的制造方法和半导体芯片安装体 Pending CN1681097A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004116271A JP2005302971A (ja) 2004-04-09 2004-04-09 半導体チップ実装体の製造方法、半導体チップ実装体
JP116271/2004 2004-04-09

Publications (1)

Publication Number Publication Date
CN1681097A true CN1681097A (zh) 2005-10-12

Family

ID=35067607

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200410058664 Pending CN1681097A (zh) 2004-04-09 2004-07-27 半导体芯片安装体的制造方法和半导体芯片安装体

Country Status (3)

Country Link
JP (1) JP2005302971A (ja)
CN (1) CN1681097A (ja)
TW (1) TWI248139B (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021880A (zh) * 2011-09-22 2013-04-03 株式会社东芝 半导体装置的制造方法
CN105555848A (zh) * 2013-09-24 2016-05-04 日东电工株式会社 半导体芯片密封用热固化性树脂片及半导体封装体的制造方法
CN105990304A (zh) * 2015-02-25 2016-10-05 扬智科技股份有限公司 芯片封装结构及其制造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5456440B2 (ja) 2009-01-30 2014-03-26 日東電工株式会社 ダイシングテープ一体型ウエハ裏面保護フィルム
JP5640050B2 (ja) * 2009-01-30 2014-12-10 日東電工株式会社 半導体装置の製造方法
JP5640051B2 (ja) * 2009-01-30 2014-12-10 日東電工株式会社 半導体装置の製造方法
US9196533B2 (en) 2010-04-20 2015-11-24 Nitto Denko Corporation Film for back surface of flip-chip semiconductor, dicing-tape-integrated film for back surface of semiconductor, process for producing semiconductor device, and flip-chip semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021880A (zh) * 2011-09-22 2013-04-03 株式会社东芝 半导体装置的制造方法
CN103021880B (zh) * 2011-09-22 2015-07-08 株式会社东芝 半导体装置的制造方法
CN105555848A (zh) * 2013-09-24 2016-05-04 日东电工株式会社 半导体芯片密封用热固化性树脂片及半导体封装体的制造方法
CN105555848B (zh) * 2013-09-24 2019-04-23 日东电工株式会社 半导体芯片密封用热固化性树脂片及半导体封装体的制造方法
CN105990304A (zh) * 2015-02-25 2016-10-05 扬智科技股份有限公司 芯片封装结构及其制造方法

Also Published As

Publication number Publication date
TW200534409A (en) 2005-10-16
TWI248139B (en) 2006-01-21
JP2005302971A (ja) 2005-10-27

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