CN1627512A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1627512A
CN1627512A CNA2004100973604A CN200410097360A CN1627512A CN 1627512 A CN1627512 A CN 1627512A CN A2004100973604 A CNA2004100973604 A CN A2004100973604A CN 200410097360 A CN200410097360 A CN 200410097360A CN 1627512 A CN1627512 A CN 1627512A
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barrier metal
metal substrate
electrode
semiconductor device
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石栗雅彦
松木浩久
依田博行
冈本九弘
生云雅光
千叶修一
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Fujitsu Ltd
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Abstract

一种半导体器件包括半导体衬底和以节距X1排列的凸电极阵列。每个凸电极具有高度X3，并且形成于直径为X2的阻挡金属基底上，该阻挡金属基底连接到该半导体衬底上所排列的电极，以满足关系(X1/2)≤X2≤(3×X1/4)和(X1/2)≤X3≤(3×X1/4)。

Description

半导体器件及其制造方法
技术领域
本发明一般地涉及一种半导体器件及其制造方法，特别地涉及一种具有窄节距(narrow-pitch)凸(protruding)电极的半导体器件。
背景技术
近年来，随着电子设备的微型化，电子设备中并入的半导体器件已经被制造得越来越小。半导体器件或半导体芯片在其器件表面上具有凸起(bump)(凸电极)，同时其上放置有半导体芯片的电路板被配备有与这些凸起相对应的电极。通过倒装芯片(flip-chip)工艺，将半导体芯片安装在电路板上，且这些凸起与电路板电极连接。为了使半导体芯片进一步微型化，凸电极的节距必须进一步变窄。
通常，由焊料(solder)制成的凸电极(此后称为“凸起”)通过焊膏印刷、焊球转移(ball transfer)、焊电镀或其他技术而形成于半导体芯片的器件表面上。凸起节距常为500μm，随着高密度工艺的进步，其已变窄为250μm，并且进而为200μm。预料在不久的将来需要小于50μm的格栅阵列凸起节距。利用这种窄节距，半导体芯片相对于电路板的微小位置偏移通常妨碍可靠的电连接。然而，通过利用在采用球形焊球(solder ball)凸起时产生的自对准现象，能够自动纠正位置偏移。为此，球形焊料凸起是受欢迎的。
另一方面，在窄节距倒装芯片的安装中出现结构问题。由于电路板和半导体芯片之间的热膨胀特性差异，大量应力(stress)作用于凸起。在较大应力作用于凸起时，半导体芯片和电路板之间的电连接可靠性被降低。为了减少应力，需要使得凸起的高度相对于凸起节距尽可能大，并且保持焊球的基金属和底层(underlying layer)之间的粘结或接触。
关于制造方面，浆料印刷(paste printing)不适于形成窄节距的焊料凸起，因为典型焊膏的颗粒大小近似于节距大小。焊球转移工艺也不适用，因为这样小的焊球不能被可靠地固定。因此选择电镀。
当通过电解电镀在半导体芯片上制造凸起电极时，形成了限定凸起阵列的抗蚀图，然后通过电解电镀在抗蚀图中生长(grow)金属。这种方法例如被公开于JP11-195665A(Kokai)的第7-8页和图2中。
然而，如果球栅格阵列的节距变窄，则抗蚀剂层的开口图案变得更精细，并且纵横比(开口的深度与内径之比)变大。这使得电解电镀液进入抗蚀图的开口之中变得困难，因为抗蚀材料通常具有疏水性，并且会使电镀液流出。
如果抗蚀图的开口不能被电镀电解液充分地填充，则生长电镀层的厚度会变化，并且不能制造均匀形状的凸起。这种不均匀的凸起极大地降低半导体芯片和电路板之间的电连接可靠性。
发明内容
构思本发明以克服上述问题，并且本发明的目的是提供一种半导体器件，其具有高纵横比的均匀窄节距的凸电极。
为实现上述目的，在本发明的方案中，提供一种半导体器件。该半导体器件包括：半导体衬底；以及以节距X1排列的凸电极阵列。每个凸电极具有高度X3，并且形成于直径为X2的阻挡金属基底上，该阻挡金属基底连接到该半导体衬底上所排列的电极，以满足关系(X1/2)≤X2≤(3×X1/4)和(X1/2)≤X3≤(3×X1/4)。
这种布置能够实现窄节距的凸电极阵列，同时保证凸电极的足够高度。因此，当在倒装芯片安装工艺中将半导体器件安装到电路板上时，改善了接合可靠性。
在优选实例中，该阻挡金属基底是以如下次序从顶部排列的Ni层、Cu层和Ti层的组合，并且该Ti层相对于该铜Cu层具有从100nm到200nm范围内的侧边蚀刻(side etch)。
在本发明的另一方案中，提供一种用于制造半导体器件的方法。该方法包括步骤：(a)在半导体衬底上形成种子层；(b)形成在与位于该半导体衬底上的电极相对应的位置处具有开口的抗蚀剂掩模，该种子层被暴露于该开口中；(c)形成阻挡金属基底，以包含被暴露于该开口中的该种子层；(d)通过电镀在该阻挡金属基底上形成凸电极；以及(f)在该抗蚀剂掩模形成步骤之后执行预处理工艺，在该预处理工艺中执行灰化(ashing)工艺、酸浸(acid immersion)工艺和水洗(water rinsing)工艺中的至少一项。
由于在电镀步骤之前，执行灰化处理、酸浸处理和水洗处理中的至少一项，改善了抗蚀剂掩模相对于电镀液的润湿特性或吸镀特性。因此，电镀液容易被引入到具有高纵横比的开口之中，并且能够制造出具有充分和均匀高度的凸电极。
该方法还包括步骤：在该凸电极被形成于该开口中后，去除该抗蚀剂掩模；以及通过湿蚀刻，使该阻挡金属基底成形。
优选地，形成该凸电极的步骤包括：利用羧酸(carboxylic acid)在凸电极上进行无焊剂(fluxless)回流，以使该凸电极成形。
与常规焊剂(flux)回流工艺相比，这种布置可容易地控制还原能力。由于焊料向周围的扩散被很好地控制，因此防止相邻凸电极之间出现短路。
由此实现具有窄节距凸电极的高可靠性半导体器件，同时防止在回流工艺期间相邻电极之间的短路。
附图说明
从参照附图来阅读的如下具体描述中，本发明的其他目的、特征和优点将变得更为明显，在附图中：
图1是表示按照本发明实施例的半导体器件上形成的阻挡金属基底上的焊料凸起的图；
图2表示在制造按照本发明实施例的半导体器件时制备具有金属电极的半导体衬底；
图3表示在按照本发明实施例的半导体器件的制造工艺中由排列于Ti层上的Cu层所制成的种子层(seed layer)；
图4表示在按照本发明实施例的半导体器件的制造工艺中在半导体衬底上形成抗蚀剂层；
图5表示在按照本发明实施例的半导体器件的制造工艺中在该抗蚀剂(resist)中形成开口；
图6表示在按照本发明实施例的半导体器件的制造工艺中在该开口中形成阻挡金属基底；
图7表示在按照本发明实施例的半导体器件的制造工艺中在该开口中生长焊料；
图8表示在按照本发明实施例的半导体器件的制造工艺中去除抗蚀剂；
图9表示在半导体器件的制造工艺中利用阻挡金属基底的Ni层作为掩模来蚀刻Cu种子层；
图10表示在半导体器件的制造工艺中利用Cu层作为掩模来蚀刻Ti层；
图11表示在按照本发明实施例的半导体器件的制造工艺中通过回流形成焊球；
图12是表示在按照本发明实施例的半导体器件的制造工艺中Ti层的侧边蚀刻的图；
图13是表示在电镀步骤之前作为预处理执行的灰化条件的实例表；
图14是表示在电镀步骤之前作为预处理执行的酸浸条件的实例表；
图15是表示在电镀步骤之前作为预处理执行的水洗条件的实例表；
图16是表示在电镀步骤之前作为预处理执行的第二次灰化条件的实例表；以及
图17是表示按照本发明实施例执行的预处理的效果表。
具体实施方式
现在参照附图，描述本发明的优选实施例。
图1是按照本发明实施例经由阻挡金属基底在半导体器件上形成的凸电极的横截面图。尽管下面利用图1所示半导体器件10实例来描述本发明的优选实施例，但本发明不限于该实例。
在图1中，阻挡金属基底12被***到焊球13和半导体衬底11上形成的铝电极15之间。半导体器件10通过倒装芯片工艺而被接合(bond)到安装板比如内插器(interposer)上。半导体器件10包括：半导体衬底11、铝电极15、覆盖一部分铝电极15的覆盖层16、铝电极15上形成的阻挡金属基底12和阻挡金属基底12上形成的凸电极13。
半导体衬底11例如是其上构造有指定电路的硅衬底。在半导体衬底11的器件形成面(其中形成有电路)上形成铝电极15和覆盖层16。铝电极15点连接到半导体衬底11的器件形成面上所形成的电路，并且用作输入/输出端子或电源端子。
铝电极15在50μm或更小窄节距(相邻铝电极之间)的区域阵列中排列，以实现高密度半导体器件。在优选实例中，铝电极15的节距被设定为35μm。
覆盖层16由介电材料比如二氧化硅(SiO2)制成，并且保护半导体器件10的器件形成面。在该实例中，覆盖层16覆盖铝电极15的***，以使允许电极15的中心部分露出，用于与阻挡金属基底12的物理接触。换句话说，覆盖层16在铝电极15上限定窗口17。
阻挡金属基底12被***到凸电极13和铝电极15之间，以防止在它们之间出现扩散或反应。在该优选实施例中阻挡金属基底12由多金属层构成。
更具体地，阻挡金属基底12包括Ti层20、Cu层21和Ni层22，它们以该次序从底部起排列。Ti层20与铝电极15相接触。Ti层20的厚度约为100nm，Cu层21的厚度约为250nm，Ni层22的厚度约为4.5μm。与凸电极13直接接触的Ni层22的顶表面可配备有含Ni的合金层。
凸电极13被成形为球形(因此，凸电极13被称为“焊球”)。例如，焊球13由Pb-Sn合金或Sn-Ag合金制成。可选地，可使用含铟的焊材。焊球13被接合到阻挡金属基底12上，由此经由阻挡金属基底12电连接到铝电极15。焊球13通过下面将描述的回流工艺来形成。
确定焊球13和阻挡金属基底12的尺寸，以满足指定条件。
假定焊球13的节距是X1，阻挡金属基底12的直径是X2，焊球13从半导体衬底11起的高度是X3，则满足关系：
(X1/2)≤X2≤(3×X1/4)  (1)以及
(X1/2)≤X3≤(3×X1/4)  (2)
由于焊球13形成于铝电极15之上，焊球13的节距X1等于铝电极15的节距。阻挡金属基底12的直径X2是阻挡金属基底12中所含三个金属层20、21和22中的最大直径。在该实例中，X2表示Ni层22的直径。焊球13的高度X3是从覆盖层16的顶面到焊球13顶部之间的距离。
在该实例中，焊球13的节距X1被设定为35μm，阻挡金属基底12的直径X2(与Ni层22的直径相对应)被设定为20μm，焊球13的高度X3被设定为20μm。X1的一半(X1/2)是17.5μm，X1的四分之三是26.25μm。阻挡金属基底12的直径X2和焊球13的高度X3分别满足关系式(1)和(2)(在该实例中，X2＝X3＝20mm)。通过形成阻挡金属基底12和焊球13以满足关系式(1)和(2)，可实现窄节距的焊球阵列，同时保持焊球13的高度足够高。用于接合半导体器件10的倒装芯片工艺的可靠性得以改善。
接下来，参照图2至图16，对用于制造具有上述结构的半导体器件10的工艺进行说明。该说明集中于阻挡金属基底12和焊球13的形成来进行，因为其他步骤可利用公知技术完成。
首先制备半导体衬底11，如图2所示。通过公知工艺制造半导体衬底11，并且在半导体衬底11上在指定位置形成铝电极15。铝电极15电连接到半导体衬底11上所形成的电路(未示出)。半导体衬底11的顶表面被覆盖层16覆盖，以在开口17露出铝电极15。覆盖层16例如由二氧化硅(SiO2)制成。
然后如图3所示，在半导体衬底11的整个表面上以列出的次序形成Ti层20和Cu层21。Ti层20和Cu层21限定种子层。Ti层20被喷溅形成至100nm的厚度。然后，Cu层21被喷溅形成至250nm的厚度。
优选地，Ti层20的厚度在50nm至100nm范围内。Cu层21可被替换为位于Ti层20上250nm厚的Ni层。在蚀刻和粘结于铝电极15之后，从尺寸控制的观点来看，直接形成于半导体衬底11上的第一金属种子层是钛(Ti)
然后如图4所示，通过利用抗蚀剂25，对覆盖有Ti层20和Cu层21的半导体衬底11的整个表面进行涂敷，形成正型光阻剂(此后简称为“抗蚀剂”)25，以具有均匀厚度。抗蚀剂25是电镀抗蚀剂，比如PMER-LA900(产品名，Tokyo Ohka Kogyo有限公司制造和销售)。
然后如图5所示，通过曝光和显影，在抗蚀剂25中形成开口图案26。开口图案26的直径被选择为满足关系式(1)。在该实例中，开口图案26的直径被设定为20μm，其与阻挡金属基底12的直径X2相等。利用焊料电镀抗蚀剂25，将开口26的直径X2设计为等于抗蚀剂25的厚度(20μm)，实质上是抗蚀图案化工艺的性能限制。
在开口图案26形成于抗蚀剂25中之后，如下所述，在用于形成Ni层22和焊料27的电解电镀之前，执行预处理工艺。在优选实施例中，在图13所限定的条件下执行第一次灰化工艺，然后在图14所限定的条件下执行酸浸工艺。然后，再次执行图13的灰化工艺，最后在图15所限定的条件下，执行水洗工艺，以冲洗抗蚀剂25的表面。
为了防止将要被电镀的抗蚀剂25的表面氧化，可弱化第二次灰化条件，如图16中所限定。
在预处理之后，通过电解电镀，在开口26中将Ni层22形成至4.5μm的厚度，且水洗后的抗蚀剂表面仍然湿润，以完成阻挡金属基底12，如图6所示。利用Ti层20和Cu层21作为种子层，在电解电镀工艺中生长Ni层22。尽管在图中未示出，Ni层22的顶表面可被含Ni的合金电镀层(比如Ni-Fe合金或Ni-Co合金)覆盖。这种布置改善了阻挡金属基底12相对于焊料27的润湿(wetting)特性。
然后如图7所示，通过电解电镀，以Sn-Ag焊料27填充开口26，且Ni层22和Cu/Ti种子层21/20介于焊料27和铝电极15之间。利用Cu层21和Ti层20作为种子层，还执行焊料27的电解电镀。焊料27的材料不限于Sn-Ag，也可使用Pb-Sn或铟焊料。
在电解电镀处理(如图6和图7所示)之前执行包括灰化、酸浸和水洗的预处理工艺，大大改善了抗蚀剂25的表面属性，增加了相对于电镀液的吸镀(plating-attract)特性。
因此，用于形成Ni层22和焊料27的电解电镀液易于进入具有高纵横比的开口26之中，并且以足够和均匀的高度实现高纵横比的精细图案化的焊料27。
尽管在上述实施例中，通过以列出的次序依次地执行第一次灰化、酸浸、第二次灰化和水洗来完成预处理，但是这些工艺的次序不限于该具体实例。图17示出了这些工艺和对应预处理结果的各种组合。从图17清楚地理解，与常规方法相比较，通过执行第一次灰化、酸浸、第二次灰化和水洗中的至少一项，可改善电镀性能。通过优化组合，可改善抗蚀剂25相对于电镀液的吸镀特性，并且用于形成Ni层22和焊料27的电解电镀液可被容易地引入到开口26之中。
在焊料27的电解电镀工艺之后，去除抗蚀剂25，并且蚀刻Ni层22，如图8所示。Ni层22的蚀刻是阻挡金属基底12的成形工艺的一部分。
然后如图9所示，利用Ni层22作为掩模，对Cu层21进行湿蚀刻。蚀刻剂例如是富氧水(oxygenated water)和乙酸的混合液。
然后如图10所示，利用Cu层21作为掩模，以氟化酸水溶液蚀刻Ti层20。当Ni层22、Cu层21和Ti层20被蚀刻时，阻挡金属基底12被成形。
通过上述蚀刻处理，蚀刻后的Ti层20的直径变为19.0μm，其与抗蚀剂开口图案26的20μm直径非常接近。因此，在Ti层20和底层铝电极1 5之间获得足够宽的接触面积，这能够防止铝电极15由于作用于焊球13的应力而脱落(come off)。
通过适当调整氟化酸在氟化酸水溶液中的密度，Ti层20相对于上方Cu层21的侧边蚀刻量可被设定得很小，在100nm到200nm范围内，如图12中的箭头A所示。该侧边蚀刻量小于常规的侧边蚀刻量(通常约1.5μm)，从而加宽Ti层20和铝电极15之间的接触面积，并且增大接合强度。Ti侧边蚀刻的减少量还防止出现迁移，即防止焊料27中所含锡(Sn)经过Ti层20扩散到铝电极15之中。
以这种方式，无需使用昂贵的干蚀刻装置，通过湿蚀刻便可成形阻挡金属基底12。由此降低制造成本。
在阻挡金属基底12被成形后，焊料27被成形，如图11所示。利用蚁酸(在该实例中是羟酸)作为还原剂(reducing agent)，通过无焊剂回流，使得焊料27熔化。在图11中，通过回流工艺形成焊球13。通过采用无焊剂回流，能够防止在焊料熔化过程中可能出现的短路。
由此，通过无焊剂回流防止了短路的出现，因为与常规焊剂回流相比，易于调节还原能力。熔融焊料被很好地控制，以免扩张到周围。
尽管在上述实例中使用羧酸(蚁酸)作为还原剂，但在无焊剂回流工艺中也可使用氢作为还原剂。可选地，利用含有合成树脂的某类焊剂，进行熔焊剂回流。在这种情况下，焊料27可被定性为球形，而不会导致短路。
在回流工艺之后，焊球13的高度变为20μm，其满足关系式(2)。焊球13的高度与节距之比是20/35，其约等于1.14/2。通过进行上述回流工艺以使焊球13成形，能够形成足够高的焊球13，同时保持窄节距，因此在用于将半导体器件10安装到电路板上的倒装芯片工艺中改善接合可靠性。
该专利申请基于和要求2003年12月10日提交的日本专利申请号2003-411592的在先申请日的权益，在此通过参考并入其全部内容。

Claims (5)

1.一种半导体器件，包括：
半导体衬底；以及
以节距X1排列的凸电极阵列，每个所述凸电极具有高度X3，并且形成于直径为X2的阻挡金属基底上，该阻挡金属基底连接到排列于该半导体衬底上的电极，以满足关系(X1/2)≤X2≤(3×X1/4)和(X1/2)≤X3≤(3×X1/4)。
2.如权利要求1所述的半导体器件，其中该阻挡金属基底包括以如下次序从顶部排列的镍(Ni)层、铜(Cu)层和钛(Ti)层，并且该钛(Ti)层相对于该铜(Cu)层具有从100nm到200nm范围内的侧边蚀刻。
3.一种用于制造半导体器件的方法，包括步骤：
在半导体衬底上形成种子层；
形成在与位于该半导体衬底上的电极相对应的位置处具有开口的抗蚀剂掩模，该种子层被暴露于该开口中；
形成阻挡金属基底，以包含被暴露于该开口中的该种子层；
通过电镀在该阻挡金属基底上形成凸电极；以及
在该抗蚀剂掩模形成步骤之后，进行预处理工艺，在该预处理工艺中执行灰化工艺、酸浸工艺和水洗工艺中的至少一项。
4.如权利要求3所述的方法，还包括步骤：
去除该抗蚀剂掩模；以及
蚀刻该阻挡金属基底的一部分，以使该阻挡金属基底成形。
5.如权利要求3所述的方法，还包括步骤：
通过利用羧酸的无焊剂回流使该凸电极成形。
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CN102190277A (zh) * 2010-03-15 2011-09-21 欧姆龙株式会社 电极结构及具有该电极结构的微型设备用封装
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