CN104821271A - 蚀刻底层凸块金属化层及产生的装置 - Google Patents

蚀刻底层凸块金属化层及产生的装置 Download PDF

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CN104821271A
CN104821271A CN201510055498.6A CN201510055498A CN104821271A CN 104821271 A CN104821271 A CN 104821271A CN 201510055498 A CN201510055498 A CN 201510055498A CN 104821271 A CN104821271 A CN 104821271A
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metal
layer
acid solution
wafer
copper
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CN104821271B (zh
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T·A·阿塔纳索夫
R·维勒克
A·N·董
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GlobalFoundries Inc
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GlobalFoundries Inc
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Abstract

本发明涉及蚀刻底层凸块金属化层及产生的装置，揭露用于湿蚀刻UBM层的方法及所导致的装置。实施例可包括：在具有至少两金属层的晶圆上图案成形金属凸块；曝露该晶圆至第一酸溶液，以移除由图案成形该金属凸块所曝露出的该两金属层中的一部分第一层；以及曝露该晶圆至第二酸溶液，以移除由图案成形该金属凸块与曝露该晶圆至该第一酸溶液所曝露出的该两金属层中的一部分第二层，其中，由移除该部分的该第一金属层及第二金属层所形成的在该金属凸块下面的底切是少于1.5微米。

Description

蚀刻底层凸块金属化层及产生的装置
技术领域
本案发明涉及金属凸块的制造，特别是相关于减少由蚀刻凸块下金属(UBM)层所导致的金属凸块的底切。本案发明尤其是可应用到20纳米(nm)技术节点以及以外。
背景技术
可用干或湿蚀刻凸块下金属层(UBM)层以防止短路。因为不需要额外清理蚀刻残余物，湿蚀刻可能优于干蚀刻。湿蚀刻的花费也少于干蚀刻。然而，蘑菇状电镀金属凸块下方的湿蚀刻将引起底切。
更特定而言，例如在焊锡膏制程的该金属层由光阻剂所遮罩，或例如在电镀焊锡制程的由金属凸块所遮罩的两个之一，UBM湿蚀刻移除曝露的金属层。有两个问题涉及成功的UBM蚀刻，为从曝露的部分完整移除金属层，及控制由从该金属凸块下方不期望地移除该UBM层所引起的底切。
现今所使用的湿蚀刻溶液包括硫酸(H2SO4)、过氧化氢(H2O2)及水，并接着稀释的氢氟酸(HF)，以上造成2.5至3微米的该金属凸块底切。像这样大数量的底切减低了该金属凸块的稳定性。更进一步而言，该现今的湿蚀刻溶液也攻击了该金属凸块层，像是镍或是铝层。
因此，存在一种对于湿蚀刻UBM层且产生较小金属凸块的底切的方法及所导致的装置的需要。
发明内容
本发明的一种方面(aspect)为湿蚀刻UBM层且产生小于1.5微米的金属凸块底切的方法。
本发明的另一种方面为具有小于1.5微米的金属凸块底切的装置。
本发明的额外方面及其他特征将在以下描述所揭示，以及于审阅下文后在某种程度上对于具有本领域技术的人士将是显而易见的，或可从本发明的实行学习。本发明的优点可在所附权利要求书中特别地指出后而了解及获得。
根据本发明，有些技术功效可在某种程度上达成，通过一种方法，包括：在具有至少两金属层的晶圆上图案成形金属凸块；曝露该晶圆至第一酸溶液，以移除由图案成形该金属凸块所曝露出的该两金属层中的一部分第一层；以及曝露该晶圆至第二酸溶液，以移除由图案成形该金属凸块与曝露该晶圆至该第一酸溶液所曝露出的该两金属层中的一部分第二层，其中，由移除该部分的该第一金属层及第二金属层所形成的在该金属凸块下面的底切是少于1.5微米。
本发明的一种方面包括该第一酸溶液包括磷酸(H3PO4)、过氧化氢(H2O2)及水。另一种方面包括该第一酸溶液包括体积百分比为0.07％至0.36％的H3PO4、体积百分比为0.1％至0.7％的H2O2及剩余体积的水。一种进一步的方面包括在30℃至40℃下曝露该晶圆至该第一酸溶液，并持续30至60秒。一种额外的方面包括该第二酸溶液包括稀释的氢氟酸(HF)，HF在有机溶液，或是氨、H2O2、氟及水的混合物(APFM)中。还有另一种方面包括该第二酸溶液包括体积百分比为0.1％至0.49％的HF及剩余体积的水。尚有另一种方面包括在20℃至25℃下曝露该晶圆至该第二酸溶液，并持续20至40秒。一种额外方面包括在曝露至该第二酸溶液之后，在20℃至25℃下以去离子水清洗该晶圆，并持续60至120秒。另一种方面包括由移除在该金属凸块下方的该部分的金属层所形成的底切为1微米。进一步的方面包括该第一金属层及第二金属层分别包括具有200至400纳米(nm)厚度的铜(Cu)层及具有100至200nm厚度的钛(Ti)层，且在曝露至该第一酸溶液及该第二酸溶液后，该部分的Cu层和Ti层被彻底地移除。尚有另一方面包括该金属凸块包括第一Cu层，且该金属层包括第二Cu层，并且该第一酸溶液对该第一铜层上方的该第二铜层为选择性。进一步的方面包括通过Cu的电化学沉积(ECD)形成该第一Cu层；以及通过铜的物理气相沉积(PVD)形成该第二铜层。
本案发明的另一方面为一种装置，包括：衬底；金属座体(seat)层，在该衬底上；以及金属凸块，在该金属座体层上，其中该金属座体层是由湿蚀刻UBM层所形成，且该金属凸块下方的该金属座体层的底切是小于1.5微米。
方面包括该金属座体层包括在Ti层上的Cu层。进一步的方面包括该Cu层具有200到400nm的厚度。另一种方面包括该Ti层具有100到200nm的厚度。进一步的方面包括该金属凸块下方的该金属座体层的底切为1微米。
本案发明的另一种方面包括一种方法，包括：在晶圆上的凸块下金属层上图案成形金属凸块；以一种包括体积百分比为0.07％至0.36％的磷酸(H3PO4)、体积百分比为0.1％至0.7％的H2O2及剩余体积的水的溶液执行在该晶圆上的该凸块下金属层的第一湿蚀刻；在20℃至25℃下以去离子水冲洗该晶圆，并持续60至120秒；以一种包括体积百分比为0.1％至0.49％的氢氟酸(HF)及剩余体积的水的溶液执行该UBM层的第二湿蚀刻；以及在20℃至25℃下以去离子水冲洗该晶圆，并持续60至120秒，其中，由移除该金属凸块所曝露出的该UBM层所形成的在该金属凸块下的该UBM层的底切为1微米。
进一步的方面包括该UBM层包括具有200至400纳米厚度的Cu层以及具有100至200nm厚度的Ti层，且在该第一湿蚀刻及该第二湿蚀刻之后，由该金属凸块所曝露处的该铜层与该钛层是受彻底移除。
本发明的额外的方面及技术功效将从下文的细节描述而对于本领域的技术人士而言为更容易地变为显而易知，其中，本发明的实施例将简单地由所思及的最佳模式的图示说明的方式来描述，以带出本发明。将要明白的是，本发明能有其他及不同的实施例，且其数个细节能在各种明显的方面进行修饰，并皆不悖离本发明。因此，图式及描述是视作本质说明，且不做为限制。
附图说明
本发明是由范例的方式说明，且并不用以限制，在所附图式的图中及在其中类似的参照数字代表类似的组件，且其中；
图1至6示意说明一种用于湿蚀刻UBM层以产生小于1.5微米的底切的方法，其中图6说明根据一范例实施例的图5的细节部分。
符号说明
101       晶圆
103、105  金属层
107       底部部分
109       顶部部分
111       金属凸块
201       酸溶液
301       蚀刻金属层
303       去离子水
401       酸溶液
501       蚀刻金属层
503       去离子水
505       圈出部分
601       底切。
具体实施方式
在以下的描述，为了说明的目的，叙述了数个特定细节以提供对范例实施例的彻底理解。然而，应显而易见的是，在不具有这些特定细节或是具有同等配置的情况下可以实行那些范例实施例。在其他的例子，为了避免不必要地模糊了范例实施例，广为人知的结构及装置是以方块图的形式显示。另外，除非另有指出，所有数字表示的数量、比率和数字化的使用在说明书和权利要求书中成分的性质和反应条件等等是理解成以术语“大约”而在所有例子中用于修饰。
本案发明处理(addresses)以及解决了伴随湿蚀刻UBM层而来的金属凸块底切的当前问题。根据本发明的实施例，使用了酸溶液以产生小于1.5微米的该金属凸块下方底切。
根据本发明的实施例的方法，包括图案成形晶圆的金属凸块，该晶圆上具有至少两金属层，例如UBM层。随后该晶圆曝露至第一酸溶液以移除由图案成形该金属凸块所曝露出的该两金属层中的部分第一层。随后该晶圆曝露至第二酸溶液，以移除由图案成形金属凸块及曝露该晶圆至该第一酸溶液所曝露出的该两金属层中的部分第二层。作为结果，由移除该第一金属层及第二金属层的部分所形成的该金属凸块下方的底切是小于1.5微米。
请注意到图1，根据一范例实施例，一种用于湿蚀刻UBM层的方法是以晶圆101开始。尽管图示说明为单一层，该晶圆101可包括其他层(为了方便说明而未显示)，例如聚酰亚胺(polyimide)层。该晶圆101可更包括金属层103及金属层105。该金属层103可由钛(Ti)所形成，举例来说，以90至110nm的厚度，例如是100nm，而该金属层105可由铜(Cu)所形成，举例来说，以270至330nm的厚度，例如是300nm。合起来，金属层103以及金属层105可构成UBM层。
在金属层105上方的是金属凸块111。金属凸块111可以高度63至77微米形成，例如是70微米，并且以宽度50至70微米形成，例如是60微米。该金属凸块111包括底部部分107以及顶部部分109。该底部部分107可由镍(Ni)以2.7至3.3微米的厚度形成，例如是3微米。该顶部部分109可由锡和银(SnAg)形成，举例来说，以98：2的Sn和Ag的比率。可选择的，金属凸块111可由具有在该Cu上方(为了说明方便而不显示)的薄部分的SnAg的Cu所形成。当金属凸块111是由Cu形成时，金属凸块111的Cu可由电化学沉积(ECD)形成，并且金属层105的Cu可由物理气相沉积(PVD)形成。金属凸块111可进一步为图案成形在金属层105上方的多个金属凸块中的一个。
请注意到图2，金属凸块111及金属层105是曝露至酸溶液201。酸溶液201可包括磷酸(H3PO4)、过氧化氢(H2O2)及水。更特定而言，酸溶液201可包括体积百分比为0.07％至0.36％的H3PO4、体积百分比为0.1％至0.7％的H2O2及剩余体积的水。在酸溶液201中，H2O2作用像是缓冲剂(buffer)以控制在晶圆101上的该层的蚀刻。可使用批次或单一喷出工具在30℃至40℃下曝露金属凸块111以及金属层105至酸溶液201并持续30至60秒。
请注意到图3，酸溶液201彻底移除了由图案成形金属凸块111所曝露出的一部分金属层105，形成了蚀刻金属层301。随后，蚀刻金属层301及金属凸块111以去离子水303清洗，以停止该蚀刻并洗去剩余的蚀刻残余物。去离子水303的清洗可在20℃至25℃下持续60至120秒。
请注意到图4，曝露金属凸块111、蚀刻金属层301及由蚀刻金属层301所曝露处的金属层103至另一酸溶液401。酸溶液401可包括稀释的氢氟酸(HF)，而HF是在有机溶剂或是APFM的混合物中。特定而言，酸溶液401可包括体积百分比为0.1％至0.4％的HF及剩余体积的水。可选择的，酸溶液401可包括在乙二醇(ethyleneglycol)中的HF。金属凸块111、蚀刻金属层301及由蚀刻金属层301所曝露出的金属层103，可在30℃至40℃下曝露至酸溶液401，并持续30到60秒。
如图5所图示说明，酸溶液401彻底移除由蚀刻金属层301所曝露出的金属层103的一部分而形成蚀刻金属层501。随后，蚀刻金属层501、蚀刻金属层301及金属凸块111再一次以去离子水503清洗，以停止蚀刻并洗去任何残留的蚀刻残余物。去离子水503的清洗可使用批次或单独喷出工具在20℃至25℃下持续60至120秒，。
图5所圈出的部分505更加详细说明于图6中，其中图示说明底切601是由金属层103所形成，且金属层105受蚀刻回超过金属凸块111的底部部分107的边缘。基于两种酸溶液201及酸溶液401的化学反应，该底切是小于1.5微米。该底切601可更特定为1微米，或是甚至更小于1微米。一小于1.5微米的底切601，相比于由现有湿蚀刻所形成的2.5至3微米的底切，将产生更稳定的金属凸块111。进一步而言，两种酸溶液201及酸溶液401并不攻击金属凸块111的底部部分107，该底部部分107由Ni形成，或是，如果出现在金属凸块111中则可选择地由Al形成。两种酸溶液201及酸溶液401，特别是第一酸溶液201，也展示了对于由PVD形成的Cu层的选择性，而不是ECD，使得由PVD沉积的Cu所形成的金属凸块是选择性地比由ECD所沉积的Cu受到更多蚀刻。
本发明的实施例实现数个技术功效，包括金属凸块的底切小于1.5微米。本发明享有产业应用性，其关联于设计以及制造任何各种类型的高度集成半导体元件，使用于特别是用于20nm技术节点及以外的微处理器、智慧手机、行动电话、蜂巢式手机(cellular handsets)、机上盒、DVD记录器和拨放器、汽车导航、影印机和周边、网路和电信设备、游戏***及数位相机(digital cameras)。
在上文的描述中，本发明以参照特定的范例实施例的方式而描述。然而，明显的，可对其进行各种修饰及改变，且不悖离如阐述在申请范围中，本发明更广泛的精神及范围。因此，本说明书及图式认为是用以说明性且并非为限制性。请了解本发明能够使用各种其他的组合与实施例，并且能够在本文所表示的发明概念的范围内有任何改变或修饰。

Claims (20)

1.一种方法，包括：
在具有至少两金属层的晶圆上图案化金属凸块；
曝露该晶圆至第一酸溶液，以移除通过图案化该金属凸块所曝露出的该两金属层中的一部分第一层；以及
曝露该晶圆至第二酸溶液，以移除通过图案化该金属凸块与曝露该晶圆至该第一酸溶液所曝露出的该两金属层中的一部分第二层，
其中，通过移除该第一金属层及该第二金属层的该部分所形成在该金属凸块下方的底切是少于1.5微米。
2.根据权利要求1所述的方法，其中，该第一酸溶液包括磷酸(H3PO4)、过氧化氢(H2O2)及水。
3.根据权利要求2所述的方法，其中，该第一酸溶液包括体积百分比为0.07％至0.36％的磷酸、体积百分比为0.1％至0.7％的过氧化氢及剩余体积的水。
4.根据权利要求1所述的方法，包括在30℃至40℃下曝露该晶圆至该第一酸溶液30至60秒。
5.根据权利要求1所述的方法，其中，该第二酸溶液包括稀释的氢氟酸(HF)、在有机溶剂中的氢氟酸、或是氨、过氧化氢、氟及水的混合物(APFM)。
6.根据权利要求5所述的方法，其中，该第二酸溶液包括体积百分比为0.1％至0.49％的氢氟酸及剩余体积的水。
7.根据权利要求1所述的方法，包括在20℃至25℃下曝露该晶圆至该第二酸溶液20至40秒。
8.根据权利要求1所述的方法，还包括在曝露至该第一酸溶液之后，在20℃至25℃下以去离子水清洗该晶圆60至120秒。
9.根据权利要求8所述的方法，还包括在曝露至该第二酸溶液之后，在20℃至25℃下以去离子水清洗该晶圆60至120秒。
10.根据权利要求1所述的方法，其中，通过移除在该金属凸块下方的该金属层的该部分所形成的该底切为1微米。
11.根据权利要求1所述的方法，其中，该第一金属层及该第二金属层分别包括具有200至400纳米(nm)厚度的铜层及具有100至200nm厚度的钛层，以及在曝露至该第一酸溶液及该第二酸溶液后，该铜层和该钛层的该部分被完全地移除。
12.根据权利要求1所述的方法，其中，该金属凸块包括第一铜层，以及该金属层包括第二铜层，以及该第一酸溶液对该第二铜层的选择性超过该第一铜层。
13.根据权利要求12所述的方法，还包括：
由铜的电化学沉积(ECD)形成该第一铜层；以及
由铜的物理气相沉积(PVD)形成该第二铜层。
14.一种装置，包括：
衬底；
金属座体层，在该衬底上方；以及
金属凸块，在该金属座体层上方，
其中，该金属座体层是通过湿蚀刻凸块下金属化层所形成，以及该金属凸块下方的该金属座体层的底切是小于1.5微米。
15.根据权利要求14所述的装置，其中，该金属座体层包括在钛层上方的铜层。
16.根据权利要求15所述的装置，其中，该铜层具有200至400nm的厚度。
17.根据权利要求15所述的装置，其中，该钛层具有100至200nm的厚度。
18.根据权利要求14所述的装置，其中，该金属凸块下方的该金属座体层的该底切为1微米。
19.一种方法，包括：
在晶圆上的凸块下金属化层上图案化金属凸块；
以包括体积百分比为0.07％至0.36％的磷酸(H3PO4)、体积百分比为0.1％至0.7％的过氧化氢(H2O2)及剩余体积的水的溶液在该晶圆上对该凸块下金属化层执行第一湿蚀刻；
在20℃至25℃下以去离子水清洗该晶圆60至120秒；
以包括体积百分比为0.1％至0.49％的氢氟酸(HF)及剩余体积的水的溶液对该凸块下金属化层执行第二湿蚀刻；以及
在20℃至25℃下以去离子水清洗该晶圆60至120秒，
其中，通过移除该金属凸块所曝露出的该凸块下金属化层所形成在该金属凸块下方的该凸块下金属化层的底切为1微米。
20.根据权利要求19所述的方法，该凸块下金属化层包括具有200至400纳米厚度的铜层及具有100至200nm厚度的钛层，以及在该第一湿蚀刻及该第二湿蚀刻之后，由该金属凸块所曝露处的该铜层与该钛层是被完全移除。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109868448A (zh) * 2017-12-04 2019-06-11 天虹科技股份有限公司 金属薄膜镀层机的铝贴附方法及真空传送腔结构

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10987039B2 (en) * 2014-12-03 2021-04-27 Stmicroelectronics S.R.L. Microneedle array device and method of making
GB2538736A (en) * 2015-05-26 2016-11-30 Straumann Holding Ag Process for the preparation of a topography for improved blood coagulation and/or cell attachment on a body made of titanium or a titanium alloy
KR102578794B1 (ko) 2016-06-14 2023-09-18 삼성전자주식회사 반도체 장치 및 그 제조 방법
JP7094693B2 (ja) * 2017-11-27 2022-07-04 キヤノン株式会社 液体吐出ヘッドの製造方法及び液体吐出ヘッド
CN115312408A (zh) * 2021-05-04 2022-11-08 Iqm 芬兰有限公司 用于竖直互连的电镀
CN115995444A (zh) * 2021-10-19 2023-04-21 群创光电股份有限公司 电子组件及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1627512A (zh) * 2003-12-10 2005-06-15 富士通株式会社 半导体器件及其制造方法
CN101211798A (zh) * 2006-12-29 2008-07-02 台湾积体电路制造股份有限公司 焊料凸块结构及其制作方法
US20120009777A1 (en) * 2010-07-07 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. UBM Etching Methods
CN102403243A (zh) * 2010-09-14 2012-04-04 台湾积体电路制造股份有限公司 减少金属凸块结构下金属层底切现象的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6436300B2 (en) * 1998-07-30 2002-08-20 Motorola, Inc. Method of manufacturing electronic components
US6853076B2 (en) * 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
US7547623B2 (en) * 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US6750133B2 (en) 2002-10-24 2004-06-15 Intel Corporation Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps
US20120098124A1 (en) * 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having under-bump metallization (ubm) structure and method of forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1627512A (zh) * 2003-12-10 2005-06-15 富士通株式会社 半导体器件及其制造方法
CN101211798A (zh) * 2006-12-29 2008-07-02 台湾积体电路制造股份有限公司 焊料凸块结构及其制作方法
US20120009777A1 (en) * 2010-07-07 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. UBM Etching Methods
CN102403243A (zh) * 2010-09-14 2012-04-04 台湾积体电路制造股份有限公司 减少金属凸块结构下金属层底切现象的方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109868448A (zh) * 2017-12-04 2019-06-11 天虹科技股份有限公司 金属薄膜镀层机的铝贴附方法及真空传送腔结构

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