CN1615541A - 制备用于应变SiCMOS应用中的高质量弛豫的绝缘体上SiGe的方法 - Google Patents
制备用于应变SiCMOS应用中的高质量弛豫的绝缘体上SiGe的方法 Download PDFInfo
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Abstract
提供一种制备薄、高质量、基本弛豫的绝缘体上SiGe衬底材料(10)的方法,包括:首先在第一单晶Si层(14)的表面上形成SiGe或纯Ge层,所述第一单晶Si层存在于能阻止Ge扩散的阻挡层(12)上。可选地在SiGe或纯Ge层(16)上形成Si帽盖层(18),此后,在允许Ge在整个第一单晶Si层(14)、可选的Si帽盖层(18)以及SiGe或纯Ge层(16)内相互扩散的温度下加热各层,由此在阻挡层(12)上形成基本弛豫的单晶SiGe层。在以上步骤之后进行附加SiGe的再生长和/或应变外延Si层的形成。这里还公开了绝缘体上SiGe衬底材料以及至少包括绝缘体上SiGe衬底材料的结构。
Description
技术领域
本发明涉及制备半导体衬底材料的方法,特别涉及制备薄、高质量、基本弛豫的绝缘体上SiGe衬底材料的方法。本发明的弛豫的绝缘体上SiGe衬底材料可以用作晶格不匹配的模板(template),用于通过随后的Si外延过生长在其上形成应变Si层。这种应变Si层具有高载流子迁移率,并且在高性能的互补金属氧化物半导体(CMOS)应用中很有用。本发明还涉及绝缘体上SiGe衬底材料以及至少包括衬底材料的结构。
背景技术
在半导体工业中,近来广泛使用应变Si基异质结构以获得用于CMOS的高迁移率结构。通常,实现此结构的现有技术的方法是在厚(约1到约5微米数量级)的弛豫的SiGe缓冲层上生长应变Si层。
除了对现有技术异质结构报道的高沟道电子迁移率之外;使用厚SiGe缓冲层具有几个与其相关的显著缺点。第一,厚SiGe缓冲层通常不容易与现有的Si基CMOS技术集成。第二,包括螺旋位错(TD)和错配位错的缺陷密度为从约105到约108缺陷/cm2,对于实际的VSLI(超大规模集成)应用来说仍然太高。第三,现有技术结构的性质妨碍了SiGe缓冲层的选择性生长,由此电路很难采用具有应变Si、无应变Si以及SiGe材料的器件,在有些情况中,几乎不可能集成。
为了在Si衬底上制备弛豫的SiGe材料,现有技术的方法通常生长均匀、缓变或突变的SiGe层到超出亚稳态临界厚度(即,超出形成位错以释放应力的厚度),并通过SiGe缓冲层允许形成错配位错和相关联的螺旋位错。现已使用多种缓冲结构以尝试增加结构中的错配位错部分的长度,并由此降低TD密度。
另一现有技术措施,例如Ek等人的美国专利No.5,461,243和5,759,898中介绍的,提供了具有应变和无缺陷的半导体层的结构,其中新的应变释放机构起作用,由此SiGe缓冲层弛豫,没有在SiGe层中产生TD。
常规的方法以及Ek等人的专利中介绍的可选方法都没有提供基本满足器件应用的材料要求的方案,即足够低的TD密度、基本很小或没有错配位错密度并且可以控制将形成TD缺陷的区域。由此,仍然需要开发一种新的和改进的方法,用来形成热力学稳定以阻止产生缺陷的弛豫绝缘体上SiGe衬底材料。
发明内容
本发明提供了制备薄、高质量、基本弛豫的绝缘体上SiGe衬底材料的方法。本发明还提供了制备热力学稳定以阻止产生如错配和螺旋位错的薄、高质量、基本弛豫绝缘体上SiGe衬底材料的方法。
而且,本发明提供了制备与CMOS工艺步骤兼容的薄、高质量、基本弛豫的绝缘体上SiGe衬底材料的方法。
进而,本发明提供了制备薄、高质量、基本弛豫的绝缘体上SiGe衬底材料的方法,该衬底材料可以用做形成应变Si层的晶格不匹配的模板,即衬底。
此外,本发明提供了应变Si/基本弛豫的绝缘体上SiGe结构,具有高载流子迁移率并且在高性能的CMOS应用中很有用。
在本发明中利用以下方法可以实现以上目的,该方法包括:首先在第一单晶Si层的表面上形成SiGe或纯Ge层,所述第一单晶Si层存在于能阻止Ge扩散的阻挡层上;此后,在允许Ge在整个第一单晶Si层和SiGe或纯Ge层内相互扩散的温度下进行加热步骤,由此在阻挡层上形成基本弛豫的单晶SiGe层。应该注意基本弛豫的单晶层包括SiGe或纯Ge层和第一单晶Si层的同构混合物。
本发明的这些步骤之后,在基本弛豫的单晶SiGe层上外延生长应变Si层,以形成可以用在多种高性能CMOS应用中的应变Si/弛豫的含SiGe的异质结构。
在本发明的一些实施例中,第一单晶Si和阻挡层为绝缘体上硅(SOI)衬底的部件。在其它实施例中,在半导体衬底的表面上形成阻挡层,此后在阻挡层上形成第一单晶Si层。后面的衬底材料为非SOI衬底。
本方法还考虑了使用未构图的(即,阻挡层为连续的)或构图的(即,由半导体材料环绕的分立或隔离的阻挡区或岛)的阻挡层。
在本发明的另一实施例中,在加热结构之前,在SiGe或纯Ge层上形成Si帽盖层。本发明的该实施例提供了热力学稳定的(能阻止产生缺陷)薄、基本弛豫的绝缘体上SiGe衬底材料。应该注意术语“薄”结合高质量基本弛豫的绝缘体上SiGe衬底材料使用时,表示SiGe层具有约2000nm或更小的厚度,更优选从约10到约200nm的厚度。
本发明的另一方面涉及利用上述工艺步骤形成的绝缘体上SiGe衬底材料。具体地,本发明的衬底材料包括含Si衬底;位于含Si衬底上能阻止Ge扩散的绝缘区;以及位于绝缘区上基本弛豫的SiGe层,其中基本弛豫的SiGe层具有约2000nm或更小的厚度。
本发明的另一方面涉及至少包括上述衬底材料的异质结构。具体地,本发明的异质结构包括含Si衬底;位于含Si衬底上能阻止Ge扩散的绝缘区;位于绝缘区上基本弛豫的SiGe层,其中基本弛豫的SiGe层具有约2000nm或更小的厚度;以及形成于基本弛豫的SiGe层上的应变Si层。
本发明另一方面涉及用于至少包括本发明的绝缘体上SiGe衬底材料的其它晶格不匹配结构的超晶格结构以及模板。
附图说明
图1A-1D示出了在制备薄、高质量、基本弛豫的绝缘体上SiGe衬底材料的本发明中使用的基本工艺步骤(剖面图),其中初始的衬底包括未构图的扩散阻挡区;
图2A-2D示出了在制备薄、高质量、基本弛豫的绝缘体上SiGe衬底材料的本发明的可选实施例中使用的基本工艺步骤(剖面图),其中初始的衬底包括构图的扩散阻挡区;
图3A-3B示出了本发明的一个可选实施例(剖面图),其中Si帽盖层形成于Ge或SiGe层上,Ge或SiGe层形成于未构图(3A)或构图(3B)的衬底上;
图4A-4B示出了分别在图1D和2D的薄、高质量、基本弛豫的绝缘体上SiGe衬底材料上应变Si层的形成(剖面图)。
具体实施方式
本发明提供了制备薄、高质量、基本弛豫的绝缘体上SiGe衬底材料的方法,该衬底结构可以用于随后过生长外延Si的晶格不匹配的模板,下面将通过参考本申请的附图更详细地介绍本发明。应该注意用类似的附图标记表示各附图中类似和/或对应的部分。
首先参考图1A和图2A,示出了可以在本发明中使用的初始衬底材料。具体地,图示在图1A和2A中的初始衬底材料每个包括含Si半导体衬底10,位于含Si半导体衬底10表面上阻止Ge扩散的阻挡层12(下文称做“阻挡层”),以及位于阻挡层上具有少于约1×108缺陷/cm2的错配和TD密度的第一单晶Si层14。在附图中示出的两个初始结构之间的差异为:在图1A中,阻挡层连续地存在于整个结构上,而在图2A中,阻挡层为被半导体材料,即层10和14环绕的分立和隔离的区域或岛。应该注意图1A所示的初始结构由此包括未构图的阻挡层,而图2A的初始结构包括构图的阻挡层。
无论阻挡层是否构图或未构图,初始结构可以是常规的绝缘体上硅(SOI)衬底材料,其中区域12为掩埋的氧化物区,它将第一单晶Si层14与含Si的衬底的半导体衬底10电隔离。这里使用的术语“含硅”表示至少包括硅的半导体衬底。示出的例子包括但不限于:Si、SiGe、SiC、SiGeC、Si/Si、Si/SiC、Si/SiGeC、以及其内包括任何数量的掩埋氧化物(连续、不连续或连续和不连续的混合物)区域的所使用的绝缘体上硅。
可以利用如下工艺形成SOI衬底:本领域中公知的常规SIMOX(注氧隔离)工艺,以及以下专利中提到的各种SIMOX工艺:2001年5月21日申请的共同受让的美国专利申请序列号09/861,593;2001年5月21日申请的09/861,594;2001年5月21日申请的09/861,590;2001年5月21日申请的09/861,596;以及2001年6月19日申请的09/884,670,以及Sadana等人的美国专利No.5,930,634,在此引入其整个内容作为参考。应该注意这里使用’590申请中公开的工艺制备图2A所示的构图的衬底。
可选地,可以使用其它常规的工艺制备SOI衬底材料,例如热键合和切割工艺。
除了SOI衬底,图1A和2A所示的初始衬底可以是使用常规的淀积工艺以及光刻和蚀刻(当制备构图的衬底时使用)制备的非SOI衬底。具体地,当使用非SOI衬底时,通过以下形成初始结构:借助常规的淀积或热生长工艺在含Si衬底的表面上淀积Ge扩散阻挡层,可选地利用常规的光刻和蚀刻构图阻挡层;以及此后使用常规的淀积工艺在阻挡层上形成单晶Si层,常规的淀积工艺包括化学汽相淀积(CVD)、等离子体辅助CVD、溅射、蒸发、化学溶液淀积或外延Si生长。
图1A和2A所示的初始结构的阻挡层12包括有效阻挡Ge扩散的任何绝缘材料。这种绝缘和阻挡Ge扩散的材料的例子包括但不限于晶体或非晶体氧化物或氮化物。
根据制备使用的工艺可以改变初始结构的各层的厚度。然而,通常单晶Si层14具有从约1到约2000nm的厚度,更优选从约20到约200nm的厚度。对于阻挡层12(即,Ge扩散阻挡层),具有从约1到约1000nm的厚度,更优选从约20到约200nm的厚度。含Si衬底层,即层10,的厚度,对于本发明不是很重要。应该注意以上提供的厚度仅为示例,并不限定本
发明的范围。
图1B和2B示出了在第一单晶Si层14上形成SiGe或纯Ge层16之后形成的结构。术语“SiGe层”包括达到99.99原子百分比的Ge的SiGe合金,而纯Ge包括含有100原子百分比的Ge的层。当采用SiGe层时,优选SiGe层中的Ge含量从约0.1到约99.9原子百分比,更优选从约10到35的Ge原子百分比。
根据本发明,使用本领域中的技术人员公知的任何常规的外延生长方法,在第一单晶Si层14上形成SiGe或Ge层,这些常规的外延生长方法能够(i)生长热力学稳定的(低于临界厚度)SiGe或纯Ge层,或者(ii)生长亚稳态并且没有缺陷,即错配和TD位错的SiGe或纯Ge层。能够满足条件(i)或(ii)的这种外延生长工艺的示例性例子包括但不限于:低压化学汽相淀积(LPCVD)、超高真空化学汽相淀积(UHVCVD)、常压化学汽相淀积(APCVD)、分子束外延(MBE)和等离子体增强化学汽相淀积(PECVD)。
在本发明的该阶段形成的SiGe或纯Ge层的厚度可以改变,但通常层16具有从约10到约500nm的厚度,更优选从约20到约200nm的厚度。
在本发明的一个可选实施例中,参见图3A-3B,在进行本发明的加热步骤之前,可选在SiGe或纯Ge层16上形成帽盖层18。在本发明中使用的可选的帽盖层包括任何Si材料,但不限于:外延硅(外延Si)、非晶硅(a:Si)、单晶或多晶Si,或者包括多层的它们的任何组合。在优选的实施例中,帽盖层包括外延Si。应该注意层16和18可以或者不可以在相同的反应室中形成。
当存在时,可选的帽盖层18具有从约1到约100nm的厚度,更优选从约1到约30nm的厚度。利用包括上述外延生长工艺的任何公知的淀积工艺形成可选的帽盖层。
在本发明的一个实施例中,优选在单晶Si层的表面上形成具有从约1到约2000nm厚度的纯Ge或SiGe(15到20原子百分比的Ge),此后在Ge或SiGe层上形成具有从约1到约100nm厚度的Si帽盖层。
在初始结构上形成纯Ge或SiGe(或可选的帽盖层)之后,在允许Ge在整个单晶Si层14、SiGe或纯Ge层16和,如果存在,可选的Si帽盖层中相互扩散的温度下加热图1B、2B、3A或3B所示的结构,即退火,由此在所述阻挡层上形成基本弛豫的单晶SiGe层20。应该注意在加热步骤期间在层20上形成氧化层22。在加热步骤后,使用常规的湿蚀刻工艺,通常但不总是从结构上除去该氧化层,其中与SiGe相比,使用具有高选择性的如HF的化学蚀刻剂除去氧化物。
应该注意当除去氧化层时,可以在层20上形成第二单晶Si层,并且可以多次重复本发明的上述工艺步骤制备多层弛豫的SiGe衬底材料。
在本发明的加热步骤之后形成的氧化层具有可变的厚度,范围从约10到约1000nm,更优选从约20到约500nm。
具体地,本发明的加热步骤是在约900℃到约1350℃的温度下进行的退火步骤,更优选从约1200℃到约1335℃的温度。此外,本发明的加热步骤在氧化环境中进行,氧化环境包括至少一种含氧气体,例如O2、NO、N2O、臭氧、空气以及其它类似的含氧气体。含氧气体可以相互混合(例如O2和NO的混合物),或者该气体可以用如He、Ar、N2、Xe、Kr或Ne的惰性气体稀释。
可以在可变的时间段内进行加热步骤,通常在约10到约1800分钟的范围内,更优选从约60到约600分钟的时间段。可以在单个目标温度下进行加热步骤,或者可以采用能使用多种缓变(ramp)率和浸泡时间的各种缓变和浸泡循环。
在氧化环境下进行加热步骤以获得表面氧化层,即层22,作为Ge原子的扩散阻挡层。因此,一旦在结构的表面上形成氧化层,Ge被捕获在阻挡层12和氧化层22之间。随着表面氧化物厚度的增加,在整个层14、16和可选的18中,Ge更均匀地分布,但是它连续并有效地阻止了对氧化层的侵蚀。所以随着在该加热步骤期间各层(现在已均质)的变薄,相对的Ge比例增加。当在稀释的含氧气体中在从约1200℃到约1320℃的温度下进行加热步骤时,在本发明中获得了有效的热混合。
这里同样考虑了使用基于SiGe层的熔点的定制热循环。在这种情况中,把温度调节到低于SiGe层的熔点的区域。
应该注意如果氧化进行得太快,那么Ge不能足够快地扩散远离表面氧化物/SiGe的界面,并被运送穿过氧化物(并失去),或者Ge的界面浓度太高将达到合金的熔点。
本发明的加热步骤的作用是(1)允许Ge原子扩散得更快,由此在退火期间保持均匀的分布;以及(2)对(‘初始’)应变层结构进行热预算(budget),将有助于平衡结构。进行该加热步骤之后,结构包括均匀和基本弛豫的SiGe合金层,即层20,被夹在阻挡层12和表面氧化层22之间。
根据本发明,弛豫的SiGe层20具有约2000nm或更小的厚度,更优选为约10到约100nm的厚度。应该注意在本发明中形成的弛豫的SiGe层比现有技术的SiGe缓冲层薄,并具有小于约108缺陷/cm2的缺陷密度,包括错配和TD。
在本发明中形成的弛豫的SiGe层具有从约0.1到约99.9原子百分比的最终Ge含量,更优选从约10到约35的Ge原子百分比。弛豫的SiGe层22的另一特点是它具有从约1到约100%的测量的晶格弛豫,更优选从约50到约80%的测量的晶格弛豫。
如上所述,在本发明的该阶段可以剥离表面氧化层22,以提供例如图1D或2D所示的绝缘体上SiGe衬底材料(应该注意衬底材料不包括帽盖层,由于在形成弛豫的SiGe层的过程中已使用了该层)。
图4A-4B示出了在图1D和2D的SiGe层上分别形成Si层24之后得到的结构。使用本领域中公知的常规外延淀积工艺形成Si层24。外延Si层24的厚度可以改变,但通常,外延Si层24具有从约1到约100nm的厚度,更优选从约1到约30nm的厚度。
在一些情况中,利用上述工艺步骤,可以在弛豫的SiGe层20上形成附加的SiGe,此后,可以形成外延Si层24。由于与外延Si层24相比,层20具有大的平面内晶格参数,外延Si层24将以拉伸的方式应变。
如上所述,本发明还考虑了至少包括本发明的绝缘体上SiGe衬底材料的超晶格结构和晶格不匹配结构。对于超晶格结构,这种结构将至少包括本发明的基本弛豫的绝缘体上SiGe衬底材料,以及在衬底材料的基本弛豫的SiGe层上形成的Si和SiGe交替层。
对于晶格不匹配结构,将在本发明的绝缘体上SiGe衬底材料的基本弛豫的SiGe层上形成GaAs、GaP或类似的化合物。
虽然通过本发明的优选实施例特别地示出和介绍了本发明,但是本领域中的技术人员应该理解在不脱离本发明的范围和精神的情况下可以对形式和细节进行以上和其它变化。因此本发明不限于所介绍和示出的具体形式和细节,而是落入所附的权利要求书的范围。
Claims (56)
1.一种制备薄、高质量、基本弛豫的绝缘体上SiGe衬底材料的方法,包括以下步骤:
(a)在第一单晶Si层的表面上形成SiGe或纯Ge层,所述第一单晶Si层存在于能阻止Ge扩散的阻挡层上;以及
(b)在允许Ge在整个所述第一单晶Si层和所述SiGe或纯Ge层内相互扩散的温度下加热所述层,由此在所述阻挡层上形成基本弛豫的单晶SiGe层。
2.根据权利要求1的方法,其中所述第一单晶Si层和所述阻挡层为绝缘体上硅(SOI)衬底的部件。
3.根据权利要求1的方法,其中所述第一单晶Si层和所述阻挡层为非SOI衬底的部件。
4.根据权利要求3的方法,其中所述第一单晶Si层具有约1到约2000nm的厚度。
5.根据权利要求1的方法,其中所述阻挡层为构图的阻挡层。
6.根据权利要求1的方法,其中所述阻挡层为未构图的阻挡层。
7.根据权利要求1的方法,其中所述阻挡层包括晶体或非晶体氧化物、或晶体或非晶体氮化物。
8.根据权利要求1的方法,其中所述阻挡层为构图或未构图的掩埋的氧化物区。
9.根据权利要求1的方法,其中所述阻挡层具有从约1到约1000nm的厚度。
10.根据权利要求1的方法,其中在步骤(a)中使用包括高达99.99原子百分比的Ge的SiGe层。
11.根据权利要求10的方法,其中所述SiGe层包括从约10到约35原子百分比的Ge。
12.根据权利要求1的方法,其中通过选自以下的一种外延生长工艺形成所述SiGe或纯Ge层:低压化学汽相淀积、常压化学汽相淀积、超高真空化学汽相淀积、分子束外延以及等离子体增强化学汽相淀积。
13.根据权利要求1的方法,其中在步骤(a)中使用纯Ge层。
14.根据权利要求1的方法,还包括在进行步骤(b)之前在所述SiGe或纯Ge层上形成Si帽盖层。
15.根据权利要求14的方法,其中所述Si帽盖层包括外延Si、a:Si、单晶或多晶Si或它们的任何组合和多层。
16.根据权利要求15的方法,其中所述Si帽盖层包括外延Si。
17.根据权利要求14的方法,其中所述Si帽盖层具有从约1到约100nm的厚度。
18.根据权利要求1的方法,其中在所述加热步骤期间形成表面氧化层。
19.根据权利要求18的方法,其中所述表面氧化层具有从约10到约1000nm的厚度。
20.根据权利要求18的方法,还包括利用湿化学蚀刻工艺除去所述表面氧化层。
21.根据权利要求1的方法,其中多次重复步骤(a)-(b)。
22.根据权利要求1的方法,其中在至少包括一种含氧气体的氧化气氛中进行所述加热步骤。
23.根据权利要求22的方法,其中所述至少一种含氧气体包括O2、NO、N2O、臭氧、空气或它们的混合物。
24.根据权利要求22的方法,还包括惰性气体,所述惰性气体用于稀释所述至少一种含氧气体。
25.根据权利要求1的方法,其中在从约900℃到约1350℃的温度下进行所述加热步骤。
26.根据权利要求25的方法,其中在从约1200℃到约1335℃的温度下进行所述加热步骤。
27.根据权利要求1的方法,其中所述基本弛豫的SiGe层具有约2000nm或更小的厚度。
28.根据权利要求27的方法,其中所述基本弛豫的SiGe层具有约10到约100nm的厚度。
29.根据权利要求1的方法,其中所述基本弛豫的SiGe层具有小于约108缺陷/cm2的缺陷密度。
30.根据权利要求1的方法,其中所述基本弛豫的SiGe层具有从约1到约100%的测量的晶格弛豫。
31.根据权利要求30的方法,其中所述基本弛豫的SiGe层具有从约50到约80%的测量的晶格弛豫。
32.根据权利要求1的方法,还包括在所述基本弛豫的SiGe层上生长附加的SiGe层。
33.根据权利要求32的方法,还包括在所述附加的SiGe层上形成应变Si层。
34.根据权利要求1的方法,还包括在所述基本弛豫的SiGe层上形成应变Si层。
35.一种衬底材料,包括:
含Si衬底;
位于所述含Si衬底上能阻止Ge扩散的绝缘区;以及
位于所述绝缘区上基本弛豫的SiGe层,其中所述基本弛豫的SiGe层具有约2000nm或更小的厚度。
36.根据权利要求35的衬底材料,其中所述绝缘区已构图。
37.根据权利要求35的衬底材料,其中所述绝缘区未构图。
38.根据权利要求35的衬底材料,其中所述绝缘区包括晶体或非晶体氧化物、或晶体或非晶体氮化物。
39.根据权利要求35的衬底材料,其中所述绝缘区为构图或未构图的掩埋氧化物区。
40.根据权利要求35的衬底材料,其中所述绝缘区具有从约1到约1000nm的厚度。
41.根据权利要求35的衬底材料,其中所述基本弛豫的SiGe层具有约10到约100nm的厚度。
42.根据权利要求36的衬底材料,其中所述基本弛豫的SiGe层具有从约1到约100%的测量的晶格弛豫。
43.根据权利要求42的衬底材料,其中所述基本弛豫的SiGe层具有从约50到约80%的测量的晶格弛豫。
44.一种异质结构,包括:
含Si衬底;
位于含Si衬底上能阻止Ge扩散的绝缘区;
位于绝缘区上基本弛豫的SiGe层,其中基本弛豫的SiGe层具有约2000nm或更小的厚度;以及
在基本弛豫的SiGe层上形成的应变Si层。
45.根据权利要求44的异质结构,其中所述绝缘区已构图。
46.根据权利要求44的异质结构,其中所述绝缘区未构图。
47.根据权利要求44的异质结构,其中所述绝缘区包括晶体或非晶体氧化物、或晶体或非晶体氮化物。
48.根据权利要求44的异质结构,其中所述绝缘区为构图或未构图的掩埋氧化物区。
49.根据权利要求44的异质结构,其中所述绝缘区具有从约20到约200nm的厚度。
50.根据权利要求44的异质结构,其中所述基本弛豫的SiGe层具有从约10到约100nm的厚度。
51.根据权利要求44的异质结构,其中所述基本弛豫的SiGe层具有从约1到约100%的测量的晶格弛豫。
52.根据权利要求51的异质结构,其中所述基本弛豫的SiGe层具有从约50到约80%的测量的晶格弛豫。
53.根据权利要求44的异质结构,其中所述应变Si层具有从约1到约100nm的厚度。
54.根据权利要求44的异质结构,其中所述应变Si层包括外延Si层。
55.根据权利要求44的异质结构,其中在所述应变Si层上形成弛豫的SiGe和应变Si的交替层。
56.根据权利要求44的异质结构,其中用选自GaAs和GaP的晶格不匹配化合物代替所述应变Si层。
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US10/055,138 US6805962B2 (en) | 2002-01-23 | 2002-01-23 | Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications |
US10/055,138 | 2002-01-23 |
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EP (1) | EP1479103A4 (zh) |
JP (1) | JP2005516395A (zh) |
KR (1) | KR20040068102A (zh) |
CN (1) | CN1615541A (zh) |
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CN109950153A (zh) * | 2019-03-08 | 2019-06-28 | 中国科学院微电子研究所 | 半导体结构与其制作方法 |
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EP1479103A1 (en) | 2004-11-24 |
US7074686B2 (en) | 2006-07-11 |
US20030139000A1 (en) | 2003-07-24 |
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