CN1577629A - FLASH internal unit testing method - Google Patents
FLASH internal unit testing method Download PDFInfo
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- CN1577629A CN1577629A CN 03150012 CN03150012A CN1577629A CN 1577629 A CN1577629 A CN 1577629A CN 03150012 CN03150012 CN 03150012 CN 03150012 A CN03150012 A CN 03150012A CN 1577629 A CN1577629 A CN 1577629A
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Abstract
The inner unit testing process for great capacity Flash memory includes the following steps: erasing the whole chip; separating the tested inner unit in the Flash memory into several unit blocks; designating one alternate 01...0101 and 10...1010 test data block; increasing one random offset to the initial of each unit block, writing the designated test data block within the unit block and recording the initial address of the test data block in each unit block; reading back the test data block after finishing writing all the unit blocks and completing comparison check; and finishing test and outputting the test result. The present invention has complete test coverage to the faults in Flash memory while ensuring the test efficiency.
Description
Technical field
The present invention relates to communications field measuring technology, refer to a kind of method that the FLASH internal element is tested especially.
Background technology
The fault of FLASH device mainly shows as following form:
(1) open circuit of lead or short circuit;
(2) address decoder can not correct addressing;
(3) multiple writing;
The data of (4) unit are subjected to the influence of the data of other unit or read-write operation and change;
(5) fail after writing to recover, can not get correct information when reading immediately;
(6) and then sense amplifier is read x ' time after reading a series of information x, does not have correctly response;
(7) FLASH can not keep the information that writes.
The basic structure and the fault form of expression in conjunction with FLASH can draw following fault model:
(1) fault in the memory cell array:
1. fixed logic fault (Stuck-at fault): the logical value of a unit does not change with any behavior of unit, is not subjected to the influence of remaining element yet, claims stuck-at fault again, and it comprises and is fixed as 1 or be fixed as 0 two kinds of situations (S-A-1 or S-A-0);
2. stuck-open fault (Stuck-open fault): the fault that open circuit causes;
3. state exchange fault (Transition fault): 0-〉1 or 1-0 state exchange has at least one not to be executed correctly;
4. data keep fault (Data-maintaining fault): storage unit can't keep a logical value to continue the regular hour;
5. state coupling fault (Coupling fault): and if only if unit j is in some particular state y (y ∈ 0, in the time of 1}), unit i be always some determined value x (x ∈ 0,1}), then claim unit i to be coupled in unit j.Coupled relation not necessarily has symmetry, also just says that unit i is coupled in unit j, might not also be coupled in unit I by unit j.
6. multiple Write fault (multiple access fault): to unit i write x (x ∈ 0,1}) cause unit j also to write x, 6. then claim unit i that multiple Write fault is arranged.Multiple Write fault not necessarily has symmetry.
(2) fault in the address decoding circuitry:
1. do not choose arbitrary storage unit;
2. choose selected cell, and chosen other unit.
Fault in the code translator can equivalence be the fault in the memory cell array.1. fault is equivalent to stuck-open fault, and 2. fault is equivalent to multiple Write fault.
(3) fault in the read-write logic:
1. input, one or more fixed logic faults in the output lead;
2. one or more stuck-open faults in impact damper or the latch;
3. the state coupling fault between any two in impact damper or the latch.
The fault of read-write in the logical circuit also can equivalence be the fault in the memory cell array.1. fault is equivalent to the fixed logic fault, and 2. fault is equivalent to stuck-open fault, and 3. fault is equivalent to the state coupling fault.
Can know by above analysis, the test of FLASH is equal to internal element test to FLASH, and the internal element of FLASH has mainly comprised following fault type: fixed logic fault, stuck-open fault, state exchange fault, data keep fault, state coupling fault and multiple Write fault.
For high-capacity FLASH, conventional method of testing is design like this: wipe earlier, increase preface according to the address again and write different data, the comparison of reading back successively then; Wipe again, write different data according to the address descending again, the comparison of reading back successively then.Though this method test is more comprehensive, its test duration can reach a few hours, and time overhead is too big, can't practical requirement.
A kind of method of testing is in addition taken a sample test the part address location exactly, and promptly the picked at random number of address writes different pieces of information, then readback check.This method of testing efficient is very high, but fault coverage is too low, and a lot of faults can't be found, so can not reach test request.
Summary of the invention
In view of the shortcoming of above-mentioned prior art, the invention provides a kind of method of testing to the FLASH internal element, guaranteeing that test imitates under the prerequisite of efficient, the fault of FLASH is compared complete test cover.
The invention provides a kind of FLASH internal element method of testing, comprise the following steps:
1) full wafer is wiped;
2) tested FLASH internal element is divided into several cell blocks;
3) specify one 01 ... 0101 and 10 ... 1010 staggered test data pieces;
4) on the piece first address of each cell block, increase a side-play amount at random, write the test data piece of above-mentioned appointment, and the record test data piece writes the start address of each cell block;
5) after all cell block has been write, according to the start address of each cell block this test data piece is read back, and finish twin check;
6) end of test (EOT) outputs test result.
The invention provides another kind of FLASH internal element method of testing, comprise the following steps:
1) full wafer is wiped;
2) tested FLASH internal element is divided into several cell blocks;
3) specify one 01 ... 0101 and 10 ... 1010 staggered test data pieces;
4) on the piece first address of each cell block, increase a side-play amount at random, write the test data piece of above-mentioned appointment; In each cell block, behind the test data piece that writes for the first time, increase a side-play amount more at random, write above-mentioned test data piece once more, and the record test data piece writes the start address that writes each time of each cell block;
5) after all cell block has been write, according to the start address of noting this test data piece is read back, and finish twin check;
6) end of test (EOT) outputs test result.
In the described step 4), the indegree of writing of test data can be repeatedly in each cell block.
In above-mentioned two methods, the size of described test data piece is less than described cell block.The big I of described several cell blocks equates or is unequal.
The present invention under the prerequisite that guarantees testing efficiency, can improve the fault coverage of test by the above-mentioned specific test data of structure, has particularly improved the detectability of being taken a sample test short trouble between the inner adjacent bit lines in cell block adjacent cells and unit.And this method can determine the size of test data piece flexibly according to the FLASH amount of capacity, obtains the equilibrium between test expense and the fault coverage.
Description of drawings
Fig. 1 is the synoptic diagram of method of testing of the present invention.
Embodiment
For the bigger FLASH device of memory capacity,,, then can consider only the FLASH device to be taken a sample test if this FLASH device is not also supported the write operation mode of Write Buffer owing to the time loss of all reading and writing one time is also bigger.
The described method of taking a sample test is:
1, full wafer is wiped, and FLASH is divided into several pieces;
2, specify a test data piece, this test data piece requires to be the form of checkerboard pattern, and just 01 ... 0101 and 10 ... 1010 staggered data blocks.Data block length determines that according to the requirement of test duration test speed requires fast more, and this data block is also just more little;
3, each piece is done following operation, until finishing taking a sample test to all pieces.
Method of testing is: increase a side-play amount at every turn at random on the basis of piece first address, write the test data piece, the data block that requires to write does not surmount the scope of being write piece, and the record test data piece write each piece start address; After all having write, according to the start address of each piece this data block is read back then, and finish twin check.
4, end of test (EOT) outputs test result.
Because the address section taken a sample test of this method of testing is appointment at random, so the similar checkerboard pattern of test data piece of employing is called after " checkerboard pattern is taken a sample test method at random " here.Its operation chart as shown in Figure 1.In n the cell block of FLASH, every checkerboard pattern data block that all writes appointment, the start address that writes in every are that every first address increases a side-play amount at random, and the address location that promptly writes in every is at random.
Also can be in each piece of FLASH random writing a plurality of little " checkerboard pattern " data block, such test effect is better.Because the memory inside cell failure often takes place in flakes, take a sample test evenly more, find that the probability of fault is just big more.
The benefit of the inventive method maximum is to efficiently solve the excessive problem of test expense, has guaranteed to be taken a sample test part simultaneously well and has reached than higher fault coverage.Suitably regulate the size of test data piece, generally the test duration expense can be controlled at several minutes.The method of testing that the present invention proposes is significantly improved to the fault coverage of being taken a sample test the unit, can both be detected being taken a sample test the adjacent cells short circuit in the piece and the adjacent bit lines short trouble of inside, unit.
Claims (8)
1, a kind of FLASH internal element method of testing comprises the following steps:
1) full wafer is wiped;
2) tested FLASH internal element is divided into several cell blocks;
3) specify the staggered test data piece of a 01...0101 and 10...1010;
4) on the piece first address of each cell block, increase a side-play amount at random, write the test data piece of above-mentioned appointment, and the record test data piece writes the start address of each cell block;
5) after all cell block has been write, according to the start address of each cell block this test data piece is read back, and finish twin check;
6) end of test (EOT) outputs test result.
2, a kind of FLASH internal element method of testing as claimed in claim 1, it is characterized in that: the size of described test data piece is less than described cell block.
3, a kind of FLASH internal element method of testing as claimed in claim 1 or 2 is characterized in that: the equal and opposite in direction of described several cell blocks.
4, a kind of FLASH internal element method of testing as claimed in claim 1 or 2 is characterized in that: described several cell blocks big or small unequal.
5, a kind of FLASH internal element method of testing comprises the following steps:
1) full wafer is wiped;
2) tested FLASH internal element is divided into several cell blocks;
3) specify the staggered test data piece of a 01...0101 and 10...1010;
4) on the piece first address of each cell block, increase a side-play amount at random, write the test data piece of above-mentioned appointment; In each cell block, behind the test data piece that writes for the first time, increase a side-play amount more at random, write above-mentioned test data piece once more, and the record test data piece writes the start address that writes each time of each cell block;
5) after all cell block has been write, according to the start address of noting this test data piece is read back, and finish twin check;
6) end of test (EOT) outputs test result.
6, a kind of FLASH internal element method of testing as claimed in claim 5, it is characterized in that: in the described step 4), the indegree of writing of test data can be repeatedly in each cell block.
7, a kind of FLASH internal element method of testing as claimed in claim 6, it is characterized in that: the size of the test data piece that writes in described each cell block is less than the cell block of being write.
8, as claim 5 or 6 described a kind of FLASH internal element method of testings, it is characterized in that: the size of described several cell blocks can equate also can be unequal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031500129A CN100514499C (en) | 2003-07-29 | 2003-07-29 | FLASH internal unit testing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031500129A CN100514499C (en) | 2003-07-29 | 2003-07-29 | FLASH internal unit testing method |
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| CN1577629A true CN1577629A (en) | 2005-02-09 |
| CN100514499C CN100514499C (en) | 2009-07-15 |
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| CNB031500129A Expired - Fee Related CN100514499C (en) | 2003-07-29 | 2003-07-29 | FLASH internal unit testing method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770813B (en) * | 2008-12-31 | 2013-01-02 | 联咏科技股份有限公司 | Detection method for detecting interference phenomenon of adjacent blocks of non-volatile storage |
| CN105511981A (en) * | 2015-11-24 | 2016-04-20 | 上海斐讯数据通信技术有限公司 | Method for rapidly detecting NAND Flash memory |
| CN107481764A (en) * | 2017-07-31 | 2017-12-15 | 深圳芯邦科技股份有限公司 | A kind of 3D Nand Flash scanning detection methods and system |
| CN110444247A (en) * | 2019-07-31 | 2019-11-12 | 至誉科技（武汉）有限公司 | Store the test device of equipment write error error correcting capability |
| CN110459259A (en) * | 2019-07-31 | 2019-11-15 | 至誉科技（武汉）有限公司 | Store test method, system and the storage medium of equipment write error error correcting capability |
| CN114464242A (en) * | 2022-01-13 | 2022-05-10 | 深圳市金泰克半导体有限公司 | DDR test method, device, controller and storage medium |
-
2003
- 2003-07-29 CN CNB031500129A patent/CN100514499C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770813B (en) * | 2008-12-31 | 2013-01-02 | 联咏科技股份有限公司 | Detection method for detecting interference phenomenon of adjacent blocks of non-volatile storage |
| CN105511981A (en) * | 2015-11-24 | 2016-04-20 | 上海斐讯数据通信技术有限公司 | Method for rapidly detecting NAND Flash memory |
| CN107481764A (en) * | 2017-07-31 | 2017-12-15 | 深圳芯邦科技股份有限公司 | A kind of 3D Nand Flash scanning detection methods and system |
| CN110444247A (en) * | 2019-07-31 | 2019-11-12 | 至誉科技（武汉）有限公司 | Store the test device of equipment write error error correcting capability |
| CN110459259A (en) * | 2019-07-31 | 2019-11-15 | 至誉科技（武汉）有限公司 | Store test method, system and the storage medium of equipment write error error correcting capability |
| CN114464242A (en) * | 2022-01-13 | 2022-05-10 | 深圳市金泰克半导体有限公司 | DDR test method, device, controller and storage medium |
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| Publication number | Publication date |
|---|---|
| CN100514499C (en) | 2009-07-15 |
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